Driving circuit, driving method thereof, display panel and display device

Abstract

Embodiments of the present disclosure provide a driving circuit, a driving method thereof, a display panel and a display device. The driving circuit comprises: a first transistor electrically connected between a signal input end and a light emitting device to be driven; a time length control circuit configured to provide a signal at a time length data signal end to a gate of the first transistor in response to a signal at a time length scanning signal end; and a latch circuit electrically connected to the gate of the first transistor and configured to latch the signal at the gate of the first transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a driving method thereof, a display panel and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED) and other electroluminescent diodes have the advantages of self-luminescence, low energy consumption, etc., and are one of the hotspots in the field of application research of electroluminescent display devices today. In general, a driving circuit is used to drive the electroluminescent diode to emit light in the electroluminescent display device. SUMMARY

[0003] The driving circuit provided by the embodiments of the present disclosure comprises:

[0004] A first transistor is electrically connected between a signal input end and a light emitting device to be driven.

[0005] A time length control circuit is configured to provide a signal of a time length data signal end to a gate of the first transistor in response to a signal of a time length scanning signal end.

[0006] A latch circuit is electrically connected to the gate of the first transistor and is configured to latch the signal of the gate of the first transistor.

[0007] Optionally, in the embodiments of the present disclosure, the driving circuit further comprises a driving signal control circuit.

[0008] The signal input end is electrically connected to the first transistor through the driving signal control circuit, and the driving signal control circuit is configured to generate a driving signal for driving the light emitting device to be driven.

[0009] Optionally, in the embodiments of the present disclosure, the time length control circuit comprises a second transistor.

[0010] The gate of the second transistor is electrically connected to the time length scanning signal end, the first pole of the second transistor is electrically connected to the time length data signal end, and the second pole of the second transistor is electrically connected to the gate of the first transistor.

[0011] Optionally, in the embodiments of the present disclosure, the latch circuit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor.

[0012] The gate of the third transistor is electrically connected with the gate of the first transistor, the first pole of the third transistor is electrically connected with the first reference signal end, and the second pole of the third transistor is electrically connected with the gate of the fifth transistor and the gate of the sixth transistor respectively;

[0013] The gate of the fourth transistor is electrically connected with the gate of the first transistor, the first pole of the fourth transistor is electrically connected with the second reference signal end, and the second pole of the fourth transistor is electrically connected with the gate of the fifth transistor and the gate of the sixth transistor respectively;

[0014] The first pole of the fifth transistor is electrically connected with the first reference signal end, and the second pole of the fifth transistor is electrically connected with the gate of the first transistor.

[0015] The first pole of the sixth transistor is electrically connected with the second reference signal end, and the second pole of the sixth transistor is electrically connected with the gate of the first transistor.

[0016] The display panel provided by the embodiments of the present disclosure comprises:

[0017] A plurality of pixel units, at least one of the plurality of pixel units comprising a plurality of sub-pixels; each of the plurality of sub-pixels comprising one light emitting device and one driving circuit; wherein the driving circuit is the driving circuit provided by the embodiments of the present disclosure.

[0018] Optionally, in the embodiments of the present disclosure, each of the plurality of pixel units comprises a plurality of sub-pixels arranged in an array, the plurality of sub-pixels comprising at least two colors of sub-pixels, and each color of sub-pixels comprising at least two.

[0019] Optionally, in the embodiments of the present disclosure, each of the pixel units comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel.

[0020] The same color sub-pixels are arranged adjacently, and the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in a first direction in sequence.

[0021] Optionally, in the embodiments of the present disclosure, the pixel unit comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; and between the same color sub-pixels in the first direction, other color sub-pixels are arranged.

[0022] Optionally, in the embodiments of the present disclosure, each color of sub-pixel comprises four; in the same pixel unit, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in a two-row six-column structure.

[0023] The first row of the two-row six-column structure, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in sequence.

[0024] The second row of the two-row six-column structure, the third color sub-pixel, the first color sub-pixel, and the second color sub-pixel are arranged in sequence.

[0025] Optionally, in the embodiment of the present disclosure, the display panel further comprises a plurality of time length data lines; the time length data signal end of the driving circuit in the same column of sub-pixels is electrically connected to the same time length data line.

[0026] Optionally, in the embodiment of the present disclosure, the display panel further comprises a plurality of first time length data input lines, a plurality of first phase detectors, and a plurality of first charge pump circuits; wherein one time length data line corresponds to one first phase detector, one first charge pump circuit, and one first time length data input line.

[0027] The first time length data input line is electrically connected to the time length data line through the corresponding first phase detector and the first charge pump circuit in sequence.

[0028] Optionally, in the embodiment of the present disclosure, the display panel further comprises a plurality of second time length data input lines, a plurality of second phase detectors, and a plurality of second charge pump circuits; wherein one second time length data input line is electrically connected to one time length data line.

[0029] One sub-pixel comprises one second phase detector and one second charge pump circuit;

[0030] For each sub-pixel, the time length data line is electrically connected to the time length data signal end of the driving circuit through the corresponding second phase detector and the second charge pump circuit in sequence.

[0031] The embodiment of the present disclosure also provides a display device comprising the above display panel.

[0032] The embodiment of the present disclosure also provides a driving method of the above driving circuit, comprising:

[0033] Driving the driving circuit to work in at least one light-emitting adjustment period within one frame of display time;

[0034] The light-emitting adjustment period comprises:

[0035] In the time length data writing stage, the time length control circuit provides the signal of the time length data signal end to the gate of the first transistor in response to the signal of the time length scanning signal end, to control the first transistor to be turned on or turned off; the latch circuit latches the signal of the gate of the first transistor.

[0036] a light emitting adjustment stage, the latch circuit latches the signal of the gate of the first transistor, so that the first transistor keeps the state of the time length data writing stage.

[0037] Optionally, in the embodiment of the present disclosure, the driving signal control circuit comprises a reset signal terminal, a display scanning signal terminal, a light emitting control signal terminal and a display data signal terminal.

[0038] In a frame display time, and before the light emitting adjustment period, further comprising:

[0039] a reset stage, the driving signal control circuit resets in response to the signal of the reset signal terminal;

[0040] a compensation stage, the driving signal control circuit compensates the threshold value according to the signals of the display scanning signal terminal and the display data signal terminal;

[0041] In the light emitting adjustment stage, further comprising: in a preset time length, the driving signal control circuit turns on the first transistor in response to the signal of the light emitting control signal terminal; and when the first transistor is turned on, a driving signal for driving the light emitting device is generated to drive the light emitting device to emit light; wherein the preset time length is not greater than the time length of the light emitting adjustment stage. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 Structure schematic diagram of some driving circuits provided by the embodiment of the present disclosure;

[0043] Figure 2 Specific structure schematic diagram of some driving circuits provided by the embodiment of the present disclosure;

[0044] Figure 3 Structure schematic diagram of some driving circuits provided by the embodiment of the present disclosure;

[0045] Figure 4 Specific structure schematic diagram of some driving circuits provided by the embodiment of the present disclosure;

[0046] Figure 5 Flow chart of the driving method provided by the embodiment of the present disclosure;

[0047] Figure 6a Some circuit timing diagrams provided by the embodiment of the present disclosure;

[0048] Figure 6b Some circuit timing diagrams provided by the embodiment of the present disclosure;

[0049] Figure 7 Some circuit timing diagrams provided by the embodiment of the present disclosure;

[0050] Figure 8 Yet some other circuit timing diagrams provided for embodiments of the present disclosure;

[0051] Figure 9 Top view structural schematic diagrams of some display panels provided for embodiments of the present disclosure;

[0052] Figure 10 Yet some other top view structural schematic diagrams of display panels provided for embodiments of the present disclosure;

[0053] Figure 11 Yet some other top view structural schematic diagrams of display panels provided for embodiments of the present disclosure;

[0054] Figure 12 Yet some other top view structural schematic diagrams of display panels provided for embodiments of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the usual meaning understood by those with ordinary skills in the art to which the present disclosure belongs. The “first”, “second” and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. “Include” or “contain” and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. “Connected” or “connected” and similar words are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect.

[0057] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0058] Embodiments of the present disclosure provide a driving circuit, as shown in Figure 1 may include:

[0059] The first transistor M1 is electrically connected between the signal input end INP and the to-be-driven light emitting device DL.

[0060] The time length control circuit 10 is configured to provide the signal of the time length data signal end SDATA to the gate of the first transistor M1 in response to the signal of the time length scanning signal end SGATE.

[0061] The latch circuit 20 is electrically connected with the gate of the first transistor M1 and is configured to latch the signal of the gate of the first transistor M1.

[0062] The driving circuit provided by the embodiments of the present disclosure can provide the signal of the time length data signal end SDATA to the gate of the first transistor M1 under the control of the signal of the time length scanning signal end SGATE, so as to control the on time of the first transistor M1, thereby controlling the light emitting time of the to-be-driven light emitting device DL. In this way, the on time of the first transistor M1 can also be controlled independently, so that the light emitting time of the to-be-driven light emitting device DL can be adjusted independently. The latch circuit 20 can latch the signal of the gate of the first transistor M1. The signal of the gate of the first transistor M1 can be latched by the latch circuit, so that the signal of the gate of the first transistor M1 can be kept stable for a long time, thereby making the driving circuit provided by the embodiments of the present disclosure applicable to a display panel with low refresh frequency, so as to ensure the display effect of the display panel. In addition, compared with a capacitor, the latch circuit 20 can reduce the charging time of the signal, thereby making the driving circuit provided by the embodiments of the present disclosure applicable to a display panel with high refresh frequency, so as to ensure the display effect of the display panel.

[0063] In a specific implementation, the to-be-driven light emitting device DL refers to that no light emitting device DL is arranged in the driving circuit. When the driving circuit is applied to a display panel, the light emitting device DL in the display panel can be electrically connected with the driving circuit, so as to drive the light emitting device DL in the display panel by the driving circuit. In this way, when the first transistor M1 is in the on state, the driving signal of the signal input end INP can be provided to the light emitting device DL, so as to drive the light emitting device DL to emit light. In this way, the on time of the first transistor M1 can be controlled, and the time of the driving signal input to the light emitting device DL can be controlled, so as to control the light emitting time of the light emitting device DL. Thus, the light emitting time of the light emitting device DL in one frame can be controlled. Since different light emitting times can correspond to different gray scales, the display of more gray scales can be realized by controlling the light emitting time, and the display effect is improved. The driving signal can be a driving current or a driving voltage for driving the light emitting device DL to emit light.

[0064] In specific implementation, in the embodiment of the present disclosure, the first end of the light emitting device DL is electrically connected with the second electrode of the first transistor M1, and the second end of the light emitting device DL is electrically connected with the second power supply end VSS. Wherein, the first end of the light emitting device DL is the anode thereof, and the second end is the cathode thereof. And the light emitting device DL is generally an electroluminescent diode, for example, the light emitting device DL can include at least one of a micro light emitting diode (Micro LED), an organic electroluminescent diode (OLED), and a quantum dot light emitting diode (QLED). In addition, the light emitting device DL generally has a light emitting threshold voltage, and emits light when the voltage across the light emitting device DL is greater than or equal to the light emitting threshold voltage. In actual application, the specific structure of the light emitting device DL can be designed and determined according to the actual application environment, which is not limited here.

[0065] In specific implementation, in the embodiment of the present disclosure, as shown in Figure 2 The time length control circuit 10 includes a second transistor M2, wherein the gate of the second transistor M2 is electrically connected with the time length scanning signal end SGATE, the first electrode of the second transistor M2 is electrically connected with the time length data signal end SDATA, and the second electrode of the second transistor M2 is electrically connected with the gate of the first transistor M1. Exemplarily, when the second transistor M2 is in the conductive state under the control of the time length scanning signal end SGATE, the signal of the time length data signal end SDATA can be provided to the gate of the first transistor M1.

[0066] In specific implementation, in the embodiment of the present disclosure, as shown in Figure 2 The second transistor M2 can be a P-type transistor. Alternatively, the second transistor M2 can also be an N-type transistor. Of course, in actual application, the specific structure can be designed and determined according to the actual application environment, which is not limited here.

[0067] In specific implementation, in the embodiment of the present disclosure, as shown in Figure 2 The latch circuit 20 can include a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;

[0068] The gate of the third transistor M3 is electrically connected with the gate of the first transistor M1, the first electrode of the third transistor M3 is electrically connected with the first reference signal end V1, and the second electrode of the third transistor M3 is respectively electrically connected with the gate of the fifth transistor M5 and the gate of the sixth transistor M6;

[0069] The gate of the fourth transistor M4 is electrically connected with the gate of the first transistor M1, the first pole of the fourth transistor M4 is electrically connected with the second reference signal end V2, and the second pole of the fourth transistor M4 is electrically connected with the gate of the fifth transistor M5 and the gate of the sixth transistor M6 respectively;

[0070] The first pole of the fifth transistor M5 is electrically connected with the first reference signal end V1, and the second pole of the fifth transistor M5 is electrically connected with the gate of the first transistor M1;

[0071] The first pole of the sixth transistor M6 is electrically connected with the second reference signal end V2, and the second pole of the sixth transistor M6 is electrically connected with the gate of the first transistor M1.

[0072] In the specific implementation, in the embodiments of the present disclosure, when the third transistor M3 is in the conductive state under the control of the signal of the gate of the first transistor M1, the signal of the first reference signal end V1 can be provided to the gate of the fifth transistor M5 and the gate of the sixth transistor M6. When the fourth transistor M4 is in the conductive state under the control of the signal of the gate of the first transistor M1, the signal of the second reference signal end V2 can be provided to the gate of the fifth transistor M5 and the gate of the sixth transistor M6. When the fifth transistor M5 is in the conductive state under the control of the signal of its gate, the signal of the first reference signal end V1 can be provided to the gate of the first transistor M1. When the sixth transistor M6 is in the conductive state under the control of the signal of its gate, the signal of the second reference signal end V2 can be provided to the gate of the first transistor M1. In this way, the effect of latching the signal of the gate of the first transistor M1 can be achieved.

[0073] In the specific implementation, in the embodiments of the present disclosure, as shown in Figure 2 The third transistor M3 and the fifth transistor M5 can be P-type transistors, and the fourth transistor M4 and the sixth transistor M6 can be N-type transistors. Alternatively, the third transistor M3 and the fifth transistor M5 can also be N-type transistors, and the fourth transistor M4 and the sixth transistor M6 can be P-type transistors. Of course, in actual application, the design can be determined according to the actual application environment, which is not limited herein.

[0074] The above is only an example to illustrate the specific structure of each circuit in the driving circuit provided by the embodiments of the present disclosure. In the specific implementation, the specific structure of the above-mentioned circuit is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are within the protection scope of the present disclosure, and are not limited herein.

[0075] In a specific implementation, in the embodiments of the present disclosure, the voltage Vdd of the signal input end INP is generally positive, and the voltage Vss of the second power supply end is generally grounded or negative. In actual applications, the specific values of the voltage Vdd of the signal input end INP and the voltage Vss of the second power supply end can be designed and determined according to the actual application environment, which is not limited herein.

[0076] Further, in a specific implementation, in the embodiments of the present disclosure, the P-type transistor is turned off under the action of a high-level signal and turned on under the action of a low-level signal. The N-type transistor is turned on under the action of a high-level signal and turned off under the action of a low-level signal.

[0077] It should be noted that the transistor mentioned in the above-mentioned embodiments of the present disclosure can be a thin film transistor (TFT) or a metal oxide semiconductor (MOS), which is not limited herein.

[0078] In a specific implementation, according to the type of the transistor and the signal of the gate thereof, the first pole of the transistor can be used as the source thereof, and the second pole thereof can be used as the drain thereof, or vice versa. This can be designed and determined according to the actual application environment, and the specific distinction is not specifically distinguished herein.

[0079] The embodiments of the present disclosure also provide another driving circuit, as shown in Figure 3 The embodiment is transformed for the implementation manner in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments will be described below, and the same parts are not described herein.

[0080] In a specific implementation, in the embodiments of the present disclosure, as shown in Figure 3 The driving circuit can further include a driving signal control circuit 30, wherein the signal input end INP is electrically connected to the first transistor M1 through the driving signal control circuit 30, and the driving signal control circuit 30 is configured to generate a driving signal for driving the light emitting device DL.

[0081] In a specific implementation, in the embodiments of the present disclosure, as shown in Figure 3As shown, the driving signal control circuit 30 can include a reset signal terminal RST, a display scanning signal terminal XGATE, a light-emitting control signal terminal EM, and a display data signal terminal XDATA; wherein the driving signal control circuit 30 is reset in response to the signal of the reset signal terminal RST, threshold compensation is performed according to the signals of the display scanning signal terminal XGATE and the display data signal terminal XDATA, and within a preset time length, the driving signal control circuit 30 responds to the signal of the light-emitting control signal terminal EM to input the signal input terminal INP and turn on the first transistor M1; and when the first transistor M1 is turned on, a driving signal for driving the light-emitting device DL is generated to drive the light-emitting device DL to emit light; wherein the preset time length is not greater than the time length of the light-emitting adjustment stage.

[0082] In specific implementation, in the embodiments of the present disclosure, the driving signal control circuit 30 can include a pixel compensation circuit. Exemplarily, in combination with Figure 4 As shown, the pixel compensation circuit 31 can include a first switch transistor M01, a second switch transistor M02, a third switch transistor M03, a fourth switch transistor M04, a fifth switch transistor M05, a driving transistor M0, and a storage capacitor C0.

[0083] The gate of the first switch transistor M01 is electrically connected with the reset signal terminal RST, the first pole of the first switch transistor M01 is electrically connected with the initialization signal terminal VINIT, and the second pole of the first switch transistor M01 is electrically connected with the gate of the driving transistor M0.

[0084] The gate of the second switch transistor M02 is electrically connected with the display scanning signal terminal XGATE, the first pole of the second switch transistor M02 is electrically connected with the display data signal terminal XDATA, and the second pole of the second switch transistor M02 is electrically connected with the first pole of the driving transistor M0.

[0085] The gate of the third switch transistor M03 is electrically connected with the display scanning signal terminal XGATE, the first pole of the third switch transistor M03 is electrically connected with the gate of the driving transistor M0, and the second pole of the third switch transistor M03 is electrically connected with the second pole of the driving transistor M0.

[0086] The gate of the fourth switch transistor M04 is electrically connected with the light-emitting control signal terminal EM, the first pole of the fourth switch transistor M04 is electrically connected with the second pole of the driving transistor M0, and the second pole of the fourth switch transistor M04 is electrically connected with the first pole of the first transistor M1.

[0087] The gate of the fifth switch transistor M05 is electrically connected with the light-emitting control signal terminal EM, the first pole of the fifth switch transistor M05 is electrically connected with the signal input terminal INP, and the second pole of the fifth switch transistor M05 is electrically connected with the first pole of the driving transistor M0.

[0088] A first terminal of the storage capacitor C0 is electrically connected with the signal input terminal INP, and a second terminal of the storage capacitor C0 is electrically connected with the gate of the driving transistor M0.

[0089] The working process of the pixel compensation circuit can be basically the same as that in the related art, and will not be repeated here. Of course, in actual application, the pixel compensation circuit can also adopt other structures that can compensate the threshold voltage of the driving transistor M0, which is not limited here.

[0090] The present disclosure also provides a driving method of the driving circuit, including: driving the driving circuit to work in at least one light-emitting adjustment period within a frame display time; wherein, as shown in Figure 5 The light-emitting adjustment period includes:

[0091] S501, a time length data writing stage, the time length control circuit provides the signal of the time length data signal terminal to the gate of the first transistor to control the first transistor to be turned on or turned off in response to the signal of the time length scanning signal terminal; the latch circuit latches the signal of the gate of the first transistor;

[0092] S502, a light-emitting adjustment stage, the latch circuit latches the signal of the gate of the first transistor, so that the first transistor remains in the state of the time length data writing stage.

[0093] In specific implementation, in the present disclosure, as shown in Figure 6a and Figure 6b The driving circuit can be driven to work in one light-emitting adjustment period T10 within a frame display time, that is, the frame display time has one light-emitting adjustment period. Next, taking the structure of the driving circuit shown in Figure 2 as an example, the working process of the driving circuit provided by the present disclosure is described in combination with the circuit timing diagram shown in Figure 6a and Figure 6b The signal of the time length scanning signal terminal SGATE is represented by sgate, and the signal of the time length data signal terminal SDATA is represented by sdata.

[0094] Among them, the time length data writing stage T11 and the light-emitting adjustment stage T12 in the circuit timing diagram shown in Figure 6a and Figure 6b It should be noted that the signal of the first reference signal terminal V1 is a high-level signal, and the signal of the second reference signal terminal V2 is a low-level signal. Exemplarily, the voltage of the signal of the first reference signal terminal V1 is the same as that of the high-level signal of the time length data signal terminal SDATA, and the voltage of the signal of the second reference signal terminal V2 is the same as that of the low-level signal of the time length data signal terminal SDATA.

[0095] In combination withFigure 6a As shown, in the time length data writing stage T11, the signal sgate of the time length scanning signal terminal SGATE is a low level signal, the second transistor M2 is turned on to provide the low level signal sdata of the time length data signal terminal SDATA to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is low, thereby controlling the first transistor M1 and the third transistor M3 to be turned on and the fourth transistor M4 to be turned off. The turned-on first transistor M1 provides the driving current of the signal input terminal INP to the light emitting device DL to drive the light emitting device DL to emit light. The turned-on third transistor M3 provides the high level signal of the first reference signal terminal V1 to the gates of the fifth transistor M5 and the sixth transistor M6 to control the fifth transistor M5 to be turned off and the sixth transistor M6 to be turned on. The turned-on sixth transistor M6 provides the low level signal of the second reference signal terminal V2 to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is further low, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0096] In the light emitting adjusting stage T12, the signal sgate of the time length scanning signal terminal SGATE is a high level signal, and the second transistor M2 is turned off. Due to the effects of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, the level of the gate of the first transistor M1 can be latched as low, thereby making the first transistor M1 turned on. The turned-on first transistor M1 provides the driving current of the signal input terminal INP to the light emitting device DL to drive the light emitting device DL to emit light. Specifically, the level of the gate of the first transistor M1 is low, thereby controlling the third transistor M3 to be turned on and the fourth transistor M4 to be turned off. The turned-on third transistor M3 provides the high level signal of the first reference signal terminal V1 to the gates of the fifth transistor M5 and the sixth transistor M6 to control the fifth transistor M5 to be turned off and the sixth transistor M6 to be turned on. The turned-on sixth transistor M6 provides the low level signal of the second reference signal terminal V2 to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is further low, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0097] In combination Figure 6bAs shown, in the time length data writing stage T11, the signal sgate of the time length scanning signal terminal SGATE is a low level signal, the second transistor M2 is turned on to provide the high level signal sdata of the time length data signal terminal SDATA to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is high, thereby controlling the first transistor M1 and the third transistor M3 to be cut off and the fourth transistor M4 to be turned on. The cut-off first transistor M1 disconnects the signal input terminal INP from the light emitting device DL, and the light emitting device DL stops emitting light. The turned-on fourth transistor M4 provides the low level signal of the second reference signal terminal V2 to the gates of the fifth transistor M5 and the sixth transistor M6, so as to control the fifth transistor M5 to be turned on and the sixth transistor M6 to be cut off. The turned-on fifth transistor M5 provides the high level signal of the first reference signal terminal V1 to the gate of the first transistor M1, so as to further make the level of the gate of the first transistor M1 high, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0098] In the light emitting adjusting stage T12, the signal sgate of the time length scanning signal terminal SGATE is a high level signal, and the second transistor M2 is cut off. Due to the effects of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, the level of the gate of the first transistor M1 can be latched as high, thereby making the first transistor M1 cut off and the light emitting device DL not emit light. Specifically, the turned-on fourth transistor M4 provides the low level signal of the second reference signal terminal V2 to the gates of the fifth transistor M5 and the sixth transistor M6, so as to control the fifth transistor M5 to be turned on and the sixth transistor M6 to be cut off. The turned-on fifth transistor M5 provides the high level signal of the first reference signal terminal V1 to the gate of the first transistor M1, so as to further make the level of the gate of the first transistor M1 high, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0099] In summary, the first transistor M1 can be controlled to be turned on in a frame display time, so that the light emitting device DL emits light in the frame display time. The first transistor M1 can also be controlled to be cut off in a frame display time, so that the light emitting device DL does not emit light in the frame display time.

[0100] In a specific implementation, in the embodiments of the present disclosure, the driving circuit can be driven to work in at least two light-emitting adjustment periods within one frame display time F. In the two adjacent light-emitting adjustment periods, the first transistor M1 can be turned on. Alternatively, in the two adjacent light-emitting adjustment periods, the first transistor M1 can be turned off. Alternatively, in the two adjacent light-emitting adjustment periods, the first transistor M1 can be turned on in the former light-emitting adjustment period and turned off in the latter light-emitting adjustment period, or the first transistor M1 can be turned off in the former light-emitting adjustment period and turned on in the latter light-emitting adjustment period, which is not limited herein.

[0101] In a specific implementation, in the embodiments of the present disclosure, as shown in Figure 7 , the driving circuit can be driven to work in two light-emitting adjustment periods T10 and T20 within one frame display time F. Of course, the driving circuit can also be driven to work in three light-emitting adjustment periods within one frame display time, or in four, five or more light-emitting adjustment periods within one frame display time. Of course, in actual application, the design can be determined according to the actual application environment, which is not limited herein.

[0102] Next, the working process of the driving circuit provided by the embodiments of the present disclosure will be described by taking the structure of the driving circuit shown in Figure 2 as an example in combination with the circuit timing diagram shown in Figure 7 . sgate represents the signal of the time length scanning signal end SGATE, and sdata represents the signal of the time length data signal end SDATA.

[0103] Among them, the time length data writing stage T11 in the light-emitting adjustment period T10, the light-emitting adjustment stage T12 in the light-emitting adjustment period T10, the time length data writing stage T21 in the light-emitting adjustment period T20, and the light-emitting adjustment stage T22 in the light-emitting adjustment period T20 in the circuit timing diagram shown in Figure 7 are mainly selected. It should be noted that the signal of the first reference signal end V1 is a high-level signal, and the signal of the second reference signal end V2 is a low-level signal. For example, the voltage of the signal of the first reference signal end V1 is the same as the voltage of the high-level signal of the time length data signal end SDATA, and the voltage of the signal of the second reference signal end V2 is the same as the voltage of the low-level signal of the time length data signal end SDATA.

[0104] In the light-emitting adjustment period T10, the working process of the driving circuit in the time length data writing stage T11 can be basically the same as the working process of the driving circuit in the time length data writing stage T11 shown in Figure 6a , which will not be described in detail herein.

[0105] The working process of the driving circuit in the light-emitting adjustment stage T12 can be basically the same as the working process of the driving circuit in the light-emitting adjustment stage T12 shown inFigure 6a The working process of the driving circuit in the light-emitting adjustment stage T12 is basically the same as that shown in the light-emitting adjustment stage T11, and details are not repeated here.

[0106] In the light-emitting adjustment period T20, the working process of the driving circuit in the time length data writing stage T21 can be basically the same as that shown in the time length data writing stage T11, and details are not repeated here. Figure 6b The working process of the driving circuit in the light-emitting adjustment stage T12 is basically the same as that shown in the light-emitting adjustment stage T11, and details are not repeated here.

[0107] The working process of the driving circuit in the light-emitting adjustment stage T22 can be basically the same as that shown in the light-emitting adjustment stage T12, and details are not repeated here. Figure 6b The working process of the driving circuit in the light-emitting adjustment stage T12 is basically the same as that shown in the light-emitting adjustment stage T11, and details are not repeated here.

[0108] Of course, the order of the light-emitting adjustment period T10 and the light-emitting adjustment period T20 in the one frame display time F is not limited in particular, for example, the light-emitting adjustment period T10 can appear first in the one frame display time F, and then the light-emitting adjustment period T20 appears. Alternatively, the light-emitting adjustment period T20 can appear first in the one frame display time F, and then the light-emitting adjustment period T10 appears.

[0109] In summary, in the same frame display time, the first transistor M1 can be controlled to be turned on to make the light-emitting device DL emit light. The first transistor M1 can also be controlled to be turned off to make the light-emitting device DL not emit light. In this way, the light-emitting time of the light-emitting device DL in the one frame display time can be controlled, thereby realizing the effect of adjusting the light-emitting brightness.

[0110] Further, in the specific implementation, when the driving circuit includes the driving signal control circuit 30, in the one frame display time and before the light-emitting adjustment period, the driving signal control circuit 30 can further include:

[0111] In the reset stage, the driving signal control circuit 30 is reset in response to the signal of the reset signal end RST;

[0112] In the compensation stage, the driving signal control circuit 30 performs threshold compensation according to the signals of the display scanning signal end XGATE and the display data signal end XDATA;

[0113] In the light-emitting adjustment stage, the driving signal control circuit 30 turns on the first transistor M1 in response to the signal of the light-emitting control signal end EM and inputs the signal into the signal input end INP; and when the first transistor M1 is turned on, the driving signal control circuit 30 generates a driving signal for driving the light-emitting device DL to drive the light-emitting device DL to emit light; wherein the preset time length is not greater than the time length of the light-emitting adjustment stage.

[0114] In a specific implementation, in the embodiments of the present disclosure, when the driving circuit is driven to work in at least two light-emitting adjustment periods within one frame display time, the preset time length in each light-emitting adjustment period can be the same, or the preset time length in part of the light-emitting adjustment periods can be the same and the preset time length in the remaining light-emitting adjustment periods can be different.

[0115] Alternatively, the preset time length in each light-emitting adjustment period can be different. For example, in each two adjacent light-emitting adjustment periods, the preset time length in the previous light-emitting adjustment period is greater than the preset time length in the next light-emitting adjustment period. Alternatively, in each two adjacent light-emitting adjustment periods, the preset time length in the previous light-emitting adjustment period is less than the preset time length in the next light-emitting adjustment period. Further, the difference between the preset time lengths in each two adjacent light-emitting adjustment periods can be the same. Alternatively, the ratio between the preset time lengths in each two adjacent light-emitting adjustment periods can be the same. This is not limited herein.

[0116] The working process of the driving circuit provided by the embodiments of the present disclosure will be described below with reference to the structure of the driving circuit shown in Figure 4 and the circuit timing diagram shown in Figure 8 The signal of rst represents the signal of the reset signal end RST, the signal of xgate represents the signal of the display scanning signal end XGATE, the signal of sgate represents the signal of the time length scanning signal end SGATE, the signal of sm represents the signal of the light-emitting control signal end EM, the signal of sdata represents the signal of the time length data signal end SDATA, and the signal of xdata represents the signal of the display data signal end XDATA.

[0117] Among them, mainly selecting the reset stage T01, the compensation stage T02, the light-emitting adjustment period T10, the light-emitting adjustment period T20, and the light-emitting adjustment period T30 in the circuit timing diagram shown in Figure 8 Among them, the light-emitting adjustment period T10 includes the time length data writing stage T11 and the light-emitting adjustment stage T12. The light-emitting adjustment period T20 includes the time length data writing stage T21 and the light-emitting adjustment stage T22. The light-emitting adjustment period T30 includes the time length data writing stage T31 and the light-emitting adjustment stage T32. It should be noted that the signal of the first reference signal end V1 is a high-level signal, and the signal of the second reference signal end V2 is a low-level signal. For example, the voltage of the signal of the first reference signal end V1 is the same as the voltage of the high-level signal of the time length data signal end SDATA, and the voltage of the signal of the second reference signal end V2 is the same as the voltage of the low-level signal of the time length data signal end SDATA.

[0118] In the reset stage T01, the signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. The signal sm of the light emitting control signal end EM is a high level signal, the fourth switch transistor M04 and the fifth switch transistor M05 are cut off. The signal sgate of the time length scanning signal end SGATE is a high level signal, the second transistor M2 is cut off. The signal of the reset signal end RST is a low level signal, the first switch transistor M01 is turned on. The first switch transistor M01 which is turned on provides the signal of the initialization signal end VINIT to the gate of the driving transistor M0, so that the gate of the driving transistor M0 is the voltage Vinit of the signal of the initialization signal end VINIT, so as to reset the gate of the driving transistor M0.

[0119] In the compensation stage T02, the signal sm of the light emitting control signal end EM is a high level signal, the fourth switch transistor M04 and the fifth switch transistor M05 are cut off. The signal sgate of the time length scanning signal end SGATE is a high level signal, the second transistor M2 is cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a low level signal, the second switch transistor M02 and the third switch transistor M03 are turned on. The third switch transistor M03 which is turned on turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode connection mode. The second switch transistor M02 which is turned on provides the signal xdata of the display data signal end XDATA to the first electrode of the driving transistor M0, and charges the gate of the driving transistor M0, until the gate of the driving transistor M0 is charged to Vdata+Vth, the driving transistor M0 is cut off. And the voltage of the gate of the driving transistor M0 is stored through the storage capacitor C0. Wherein, Vth is the threshold voltage of the driving transistor M0. In this way, the threshold voltage of the driving transistor M0 can be written to the gate of the driving transistor M0, so as to realize the compensation of the threshold voltage.

[0120] In the time length data writing stage T11 in the light emitting adjusting period T10, the signal sm of the light emitting control signal end EM is a high level signal, the fourth switch transistor M04 and the fifth switch transistor M05 are cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. The signal sgate of the time length scanning signal end SGATE is a low level signal, the second transistor M2 is turned on to provide the low level signal sdata of the time length data signal end SDATA to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is low, thereby controlling the first transistor M1 and the third transistor M3 to be turned on and the fourth transistor M4 to be cut off. The turned-on first transistor M1 turns on the fourth switch transistor M04 and the light emitting device DL. The turned-on third transistor M3 provides the high level signal of the first reference signal end V1 to the gates of the fifth transistor M5 and the sixth transistor M6 to control the fifth transistor M5 to be cut off and the sixth transistor M6 to be turned on. The turned-on sixth transistor M6 provides the low level signal of the second reference signal end V2 to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is further low, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0121] In the light emitting adjusting stage T12, the signal sgate of the time length scanning signal end SGATE is a high level signal, the second transistor M2 is cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. Due to the effects of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, the level of the gate of the first transistor M1 can be latched as low, thereby making the first transistor M1 turned on. The signal sm of the light emitting control signal end EM is a low level signal within the preset time length t1, so that the fourth switch transistor M04 and the fifth switch transistor M05 are turned on. The turned-on fifth switch transistor M05 provides the voltage Vdd of the signal input end INP to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is Vdd. Through the effect of the storage capacitor C0, the gate voltage of the driving transistor M0 remains Vdata+Vth. Therefore, the driving transistor M0 generates a driving current IL: IL=K[Vdata-Vdd] 2 ; wherein K is a structure parameter, which can be regarded as a constant in the same structure. Since the first transistor M1 is turned on, the driving current IL is provided to the light emitting device DL in the preset time length t1, so that the light emitting device DL can emit light in the preset time length t1.

[0122] In the time length data writing stage T21 in the light emission adjusting period T20, the signal sm of the light emission control signal end EM is a high level signal, the fourth switch transistor M04 and the fifth switch transistor M05 are cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. The signal sgate of the time length scanning signal end SGATE is a low level signal, the second transistor M2 is turned on to provide the high level signal sdata of the time length data signal end SDATA to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is high level, thereby controlling the first transistor M1 and the third transistor M3 to be cut off and the fourth transistor M4 to be turned on. The fourth transistor M4 which is turned on provides the low level signal of the second reference signal end V2 to the gates of the fifth transistor M5 and the sixth transistor M6, so as to control the fifth transistor M5 to be turned on and the sixth transistor M6 to be cut off. The fifth transistor M5 which is turned on provides the high level signal of the first reference signal end V1 to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is further high level, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0123] In the light emission adjusting stage T22, the signal sgate of the time length scanning signal end SGATE is a high level signal, the second transistor M2 is cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. Due to the effects of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, the level of the gate of the first transistor M1 can be latched as high level, thereby making the first transistor M1 cut off and making the light emitting device DL not emit light in the preset time length t2.

[0124] In the time length data writing stage T31 in the light emitting adjusting period T30, the signal sm of the light emitting control signal end EM is a high level signal, the fourth switch transistor M04 and the fifth switch transistor M05 are cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. The signal sgate of the time length scanning signal end SGATE is a low level signal, the second transistor M2 is turned on to provide the low level signal sdata of the time length data signal end SDATA to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is low, thereby controlling the first transistor M1 and the third transistor M3 to be turned on and the fourth transistor M4 to be cut off. The turned-on first transistor M1 turns on the fourth switch transistor M04 and the light emitting device DL. The turned-on third transistor M3 provides the high level signal of the first reference signal end V1 to the gates of the fifth transistor M5 and the sixth transistor M6 to control the fifth transistor M5 to be cut off and the sixth transistor M6 to be turned on. The turned-on sixth transistor M6 provides the low level signal of the second reference signal end V2 to the gate of the first transistor M1, so that the level of the gate of the first transistor M1 is further low, thereby realizing the function of latching the level of the gate of the first transistor M1.

[0125] In the light emitting adjusting stage T32, the signal sgate of the time length scanning signal end SGATE is a high level signal, the second transistor M2 is cut off. The signal of the reset signal end RST is a high level signal, the first switch transistor M01 is cut off. The signal xgate of the display scanning signal end XGATE is a high level signal, the second switch transistor M02 and the third switch transistor M03 are cut off. Due to the effects of the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6, the level of the gate of the first transistor M1 can be latched as low, thereby making the first transistor M1 turned on. The signal sm of the light emitting control signal end EM is a low level signal within the preset time length t3, so that the fourth switch transistor M04 and the fifth switch transistor M05 are turned on. The turned-on fifth switch transistor M05 provides the voltage Vdd of the signal input end INP to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is Vdd. Through the effect of the storage capacitor C0, the gate voltage of the driving transistor M0 remains Vdata+Vth. Therefore, the driving transistor M0 generates a driving current IL: IL=K[Vdata-Vdd] 2 ; wherein K is a structure parameter, which can be regarded as a constant in the same structure. Since the first transistor M1 is turned on, the driving current IL is provided to the light emitting device DL in the preset time length t3, so that the light emitting device DL can emit light in the preset time length t3.

[0126] Therefore, by controlling the on duration of the first transistor in a frame time, the brightness duration of the light emitting device can be controlled, so that multi-gray scale display effect can be realized.

[0127] For example, t1:t2:t3 can be made equal to 4:2:1. Of course, in actual applications, t1:t2:t3 can also be designed and determined according to the actual application environment, which is not limited herein.

[0128] Based on the same inventive concept, the embodiment of the disclosure also provides a display panel, as shown in Figure 9 The display panel comprises: a plurality of pixel units 100, at least one of the plurality of pixel units 100 comprises a plurality of sub-pixels 111-k (1≤k≤K, k and K are integers, K is the total number of sub-pixels in a pixel unit); each of the plurality of sub-pixels 111-k comprises: one light emitting device DL and one driving circuit; wherein the driving circuit is the above-mentioned driving circuit provided by the embodiment of the disclosure. And the structure of the driving circuit can refer to the above-mentioned structure, which will not be repeated here.

[0129] In specific implementation, in the embodiment of the disclosure, K can be made equal to 2, so that the pixel unit can comprise 2 sub-pixels. K can also be made equal to 3, so that the pixel unit can comprise 3 sub-pixels. K can also be made equal to 6, so that the pixel unit can comprise 6 sub-pixels. K can also be made equal to 9, so that the pixel unit can comprise 9 sub-pixels. K can also be made equal to 12, as shown in Figure 9 the pixel unit can comprise 12 sub-pixels. Of course, the value of K can be designed and determined according to the actual application environment, which is not limited herein.

[0130] In specific implementation, in the embodiment of the disclosure, as shown in Figure 9 Each of the plurality of pixel units comprises a plurality of sub-pixels 111-k arranged in an array. The plurality of sub-pixels comprises at least two colors of sub-pixels and each color of sub-pixels comprises at least two. For example, the pixel unit can comprise two colors of sub-pixels and each color of sub-pixels comprises at least two, the pixel unit can also comprise three colors of sub-pixels and each color of sub-pixels comprises at least two, or the pixel unit can comprise four colors of sub-pixels and each color of sub-pixels comprises at least two, which can be designed and determined according to the actual application environment, which is not limited herein.

[0131] In specific implementation, in the embodiment of the disclosure, as shown in Figure 9As shown, each of the pixel units can include sub-pixels of three colors, for example, each color sub-pixel includes four, first color sub-pixels 111-1~111-4, second color sub-pixels 111-5~111-8, third color sub-pixels 111-9~111-12. For example, the first color, the second color and the third color can be selected from red, green and blue to realize image display function by red-green-blue color mixing. For example, the first color can be red, the second color can be green, and the third color can be blue.

[0132] In addition, since the pixel unit includes sub-pixels of at least two colors and each color sub-pixel includes at least two, each sub-pixel has one light emitting device DL and one driving circuit, so that each sub-pixel can emit light independently, thereby realizing the implementation mode of the same color multi-gray scale. For example, when the pixel unit includes red, green and blue color sub-pixels and each color sub-pixel includes four, taking the red color sub-pixel as an example, if the first transistor is off within one frame display time, none of the red color sub-pixels emits light, and then the red color is zero gray scale. If only one red color sub-pixel has the first transistor turned on within one frame display time, the red color sub-pixel emits light, and then the red color is 1 / 4 gray scale. If only two red color sub-pixels have the first transistor turned on, the two red color sub-pixels emit light, and then the red color is 2 / 4 gray scale. If only three red color sub-pixels have the first transistor turned on, the three red color sub-pixels emit light, and then the red color is 3 / 4 gray scale. If only four red color sub-pixels have the first transistor turned on, the four red color sub-pixels emit light, and then the red color is the brightest gray scale. That is, the red color part in one pixel unit can have 5 gray scales from dark state to bright state. Similarly, the green color part in one pixel unit can also have 5 gray scales from dark state to bright state, and the blue color part in one pixel unit can also have 5 gray scales from dark state to bright state. In this way, one pixel unit can display 125 gray scales of colors.

[0133] Alternatively, the first transistor in one sub-pixel is turned on in part of the preset time length and is turned off in the remaining part of the preset time length, so that the gray scale that can be realized by the sub-pixel will be further increased, thereby further increasing the gray scale of the pixel unit, and the pixel unit can realize more colors.

[0134] Taking the red color sub-pixel as an example, if the first transistor is off within one frame display time, the red color sub-pixel does not emit light, i.e., zero gray scale.

[0135] If the first transistor in one red color sub-pixel is turned on only in the preset time length t3 within one frame display time, and is turned off in the preset time lengths t2 and t1, the red color sub-pixel emits light, and then the red color sub-pixel can have 1 / 7 gray scale.

[0136] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0137] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0138] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0139] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0140] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0141] If the first transistor in a red sub-pixel is only turned on in the preset time t2 and turned off in the preset time t1 and t3 in a frame display time, the red sub-pixel emits light, and the red sub-pixel can have 3 / 7 gray scale.

[0142] That is, in a pixel unit, a red sub-pixel can have 8 gray scales from dark state to brightest. Then, in a pixel unit, if there are four red sub-pixels, the red gray scale in the pixel unit can be 8 4 gray scales. Further, in a pixel unit, if there are red, green and blue sub-pixels, and each color has four sub-pixels, the pixel unit can realize 8 12 gray scales.

[0143] In a specific implementation, in the embodiments of the present disclosure, as shown in Figure 9 , the same color sub-pixels are arranged adjacently, and the first color sub-pixels, the second color sub-pixels and the third color sub-pixels are arranged in sequence along the first direction (the direction of the F1 arrow). For example, the first color sub-pixels 111-1 to 111-4 are arranged adjacently to form a 2*2 matrix arrangement. The second color sub-pixels 111-5 to 111-8 are arranged adjacently to form a 2*2 matrix arrangement. The third color sub-pixels 111-9 to 111-12 are arranged adjacently to form a 2*2 matrix arrangement.

[0144] In specific implementation, in the embodiments of the present disclosure, as shown in Figure 2 , Figure 4 and Figure 10 , the display panel can further include a plurality of time-length data lines SD; the time-length data signal end SDATA of the driving circuit in the same column of sub-pixels is electrically connected to the same time-length data line SD. In this way, the electrically connected driving circuit can be provided with signals through the time-length data line SD.

[0145] In specific implementation, in the embodiments of the present disclosure, as shown in Figure 2 , Figure 4 and Figure 10 , the display panel can further include a plurality of time-length scanning lines SG; wherein the time-length scanning signal end XGATE of the driving circuit in the same row of sub-pixels is electrically connected to one time-length scanning line SG. In this way, the electrically connected driving circuit can be provided with signals through the time-length scanning line.

[0146] Generally, the higher the refresh frequency of the display panel is, the shorter the charging time is, and the higher the power consumption of the driving chip is. In order to enable the display panel to adopt a higher refresh frequency, in specific implementation, in the embodiments of the present disclosure, as shown in Figure 10 , the display panel can further include a plurality of first time-length data input lines S1, a plurality of first phase detectors 210 and a plurality of first charge pump circuits 220; wherein one time-length data line SD corresponds to one first phase detector 210, one first charge pump circuit 220 and one first time-length data input line S1. The first time-length data input line S1 is electrically connected to the time-length data line SD through the corresponding first phase detector 210 and first charge pump circuit 220 in sequence. In this way, a signal with a lower voltage can be loaded to the first time-length data input line S1, then the signal loaded to the first time-length data input line S1 is detected through the first phase detector 210, and then the detected signal is input to the first charge pump circuit 220. The first charge pump circuit 220 provides the time-length data line SD with the signal received after voltage boosting. In this way, when the second transistor M2 is turned on, the signal on the time-length data line SD can be provided to the gate of the first transistor M1, so as to realize charging of the gate of the first transistor M1 through a lower voltage. In this way, the power consumption of the driving chip can be reduced.

[0147] In specific implementation, in the embodiments of the present disclosure, as shown in Figure 11As shown, the display panel can further include a plurality of second time length data input lines S2, a plurality of second phase detectors 310 and a plurality of second charge pump circuits 320; one second time length data input line S2 is electrically connected with one time length data line SD; one sub-pixel includes one second phase detector 310 and one second charge pump circuit 320; for each sub-pixel, the time length data line SD is electrically connected with the time length data signal end SDATA of the driving circuit 400 through the corresponding second phase detector 310 and second charge pump circuit 320 in sequence. In this way, a signal with a lower voltage can be loaded on the second time length data input line S2 to charge the time length data line SD. The second phase detector 310 in each sub-pixel detects the signal transmitted by the electrically connected time length data line SD, and then inputs the detected signal to the second charge pump circuit 320. The second charge pump circuit 320 provides the first electrode of the second transistor M2 with the received signal after voltage boosting. In this way, when the second transistor M2 is turned on, the signal at the first electrode of the second transistor M2 can be provided to the gate of the first transistor M1, so as to charge the gate of the first transistor M1 by a lower voltage. In this way, the power consumption of the driving chip can be reduced.

[0148] The display panel can also be used in the display device as shown. Figure 12 The display panel can also be used in the display device as shown.

[0149] In the specific implementation, in the display panel, as shown in the display panel can also be used in the display device as shown. Figure 12As shown, in the first direction F1 (the direction of the F1 arrow), other color sub-pixels are arranged between the same color sub-pixels. For example, between the first color sub-pixel 111-1 and the first color sub-pixel 111-2, the second color sub-pixel 111-5 and the third color sub-pixel 111-9 are arranged. Between the second color sub-pixel 111-5 and the second color sub-pixel 111-6, the third color sub-pixel 111-9 and the first color sub-pixel 111-2 are arranged. Between the third color sub-pixel 111-9 and the third color sub-pixel 111-10, the first color sub-pixel 111-2 and the second color sub-pixel 111-6 are arranged. Between the third color sub-pixel 111-11 and the third color sub-pixel 111-12, the first color sub-pixel 111-3 and the second color sub-pixel 111-7 are arranged. Between the first color sub-pixel 111-3 and the first color sub-pixel 111-4, the second color sub-pixel 111-7 and the third color sub-pixel 111-12 are arranged. Between the second color sub-pixel 111-7 and the second color sub-pixel 111-8, the third color sub-pixel 111-12 and the first color sub-pixel 111-4 are arranged. Since there are multiple sub-pixels of the same color in the same pixel unit, arranging the sub-pixels of the same color together can easily cause a grainy feeling of the display image in vision. In the embodiments of the present disclosure, by arranging other color sub-pixels between the sub-pixels of the same color, the sub-pixels of the same color can be arranged in a segmented manner to alleviate the grainy feeling of the display image in vision.

[0150] In specific implementation, in the embodiments of the present disclosure, as shown in Figure 12 In the same pixel unit 100, the first color sub-pixels 111-1 to 111-4, the second color sub-pixels 111-5 to 111-8, and the third color sub-pixels 111-9 to 111-12 are arranged in a two-row six-column structure. In the first row of the two-row six-column structure, the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged in sequence; for example, the first color sub-pixel 111-1, the second color sub-pixel 111-5, the third color sub-pixel 111-9, the first color sub-pixel 111-2, the second color sub-pixel 111-6, and the third color sub-pixel 111-10 are arranged in sequence.

[0151] In the second row of the two-row six-column structure, the third color sub-pixels, the first color sub-pixels, and the second color sub-pixels are arranged in sequence. For example, the third color sub-pixel 111-11, the first color sub-pixel 111-3, the second color sub-pixel 111-7, the third color sub-pixel 111-12, the first color sub-pixel 111-4, and the second color sub-pixel 111-8 are arranged in sequence.

[0152] Of course, the arrangement of the color sub-pixels in the same pixel unit can also adopt other manners, which are not limited herein.

[0153] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure. The display device solves the problem in the same principle as the display panel, and therefore the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be described here.

[0154] In the implementation, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art, and will not be described here, nor should they be considered as a limitation to the present disclosure.

[0155] The driving circuit, the driving method thereof, the display panel and the display device provided by the embodiments of the present disclosure can provide the signal at the time length data signal end to the gate of the first transistor under the control of the signal at the time length scanning signal end, so as to control the on time of the first transistor, thereby controlling the light emitting time of the light emitting device to be driven. In addition, the on time of the first transistor can also be controlled independently, so as to independently adjust the light emitting time of the light emitting device to be driven. In addition, the signal at the gate of the first transistor can be latched by the latch circuit. Since the signal at the gate of the first transistor can be latched by the latch circuit, the signal at the gate of the first transistor can be kept stable for a long time, so as to apply the driving circuit provided by the embodiments of the present disclosure to the display panel with low refresh frequency, so as to ensure the display effect of the display panel. In addition, compared with the capacitor, the latch circuit can reduce the charging time of the signal, so as to apply the driving circuit provided by the embodiments of the present disclosure to the display panel with high refresh frequency, so as to ensure the display effect of the display panel.

[0156] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A drive circuit, wherein, Comprising: a first transistor electrically connected between a signal input end and a light emitting device to be driven; a time length control circuit configured to provide a signal at a time length data signal end to a gate of the first transistor in response to a signal at a time length scan signal end; a latch circuit electrically connected to the gate of the first transistor and configured to latch the signal at the gate of the first transistor; the latch circuit comprising: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a gate of the third transistor is electrically connected to the gate of the first transistor, a first electrode of the third transistor is electrically connected to a first reference signal end, and second electrodes of the third transistor are respectively electrically connected to gates of the fifth transistor and the sixth transistor; a gate of the fourth transistor is electrically connected to the gate of the first transistor, a first electrode of the fourth transistor is electrically connected to a second reference signal end, and second electrodes of the fourth transistor are respectively electrically connected to the gates of the fifth transistor and the sixth transistor; a first electrode of the fifth transistor is electrically connected to the first reference signal end, and a second electrode of the fifth transistor is electrically connected to the gate of the first transistor; a first electrode of the sixth transistor is electrically connected to the second reference signal end, and a second electrode of the sixth transistor is electrically connected to the gate of the first transistor; and the second electrodes of the third transistor and the fourth transistor are not electrically connected to the gate of the first transistor; the drive circuit further comprises: a drive signal control circuit, the signal input end is electrically connected to the first transistor through the drive signal control circuit; the drive signal control circuit is a pixel compensation circuit, the pixel compensation circuit comprises: a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a drive transistor, and a storage capacitor; a gate of the first switch transistor is electrically connected to a reset signal end, a first electrode of the first switch transistor is electrically connected to an initialization signal end, and a second electrode of the first switch transistor is electrically connected to a gate of the drive transistor; a gate of the second switch transistor is electrically connected to a display scan signal end, a first electrode of the second switch transistor is electrically connected to a display data signal end, and a second electrode of the second switch transistor is electrically connected to a first electrode of the drive transistor; a gate of the third switch transistor is electrically connected to the display scan signal end, a first electrode of the third switch transistor is electrically connected to the gate of the drive transistor, and a second electrode of the third switch transistor is electrically connected to a second electrode of the drive transistor; a gate of the fourth switch transistor is electrically connected to a light emitting control signal end, a first electrode of the fourth switch transistor is electrically connected to the second electrode of the drive transistor, and a second electrode of the fourth switch transistor is electrically connected to a first electrode of the first transistor; A gate of the fifth switch transistor is electrically connected with the light-emitting control signal terminal, a first electrode of the fifth switch transistor is electrically connected with the signal input terminal, and a second electrode of the fifth switch transistor is electrically connected with the first electrode of the driving transistor; A first terminal of the storage capacitor is electrically connected with the signal input terminal, and a second terminal of the storage capacitor is electrically connected with the gate of the driving transistor; The first transistor is configured to control the conduction and disconnection between the second electrode of the fourth switch transistor and the to-be-driven light-emitting device.

2. The drive circuit of claim 1, wherein, The time length control circuit comprises a second transistor; A gate of the second transistor is electrically connected with the time length scanning signal terminal, a first electrode of the second transistor is electrically connected with the time length data signal terminal, and a second electrode of the second transistor is electrically connected with the gate of the first transistor.

3. A display panel, wherein, Comprise: A plurality of pixel units, at least one of the plurality of pixel units comprising a plurality of sub-pixels; Each of the plurality of sub-pixels comprises one light-emitting device and one driving circuit; wherein the driving circuit is the driving circuit as claimed in claim 1 or 2.

4. The display panel of claim 3, wherein, Each of the plurality of pixel units comprises a plurality of sub-pixels arranged in an array, the plurality of sub-pixels comprising at least two different color sub-pixels, and each color sub-pixel comprising at least two.

5. The display panel of claim 4, wherein, Each of the pixel units comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The same color sub-pixels are arranged adjacently, and the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in sequence along a first direction.

6. The display panel of claim 4, wherein, The pixel unit comprises a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; and between the same color sub-pixels in the first direction, other color sub-pixels are arranged.

7. The display panel of claim 6, wherein, Each color sub-pixel comprises four; in the same pixel unit, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in a two-row six-column structure; In the first row of the two-row six-column structure, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged in sequence; In the second row of the two-row six-column structure, the third color sub-pixel, the first color sub-pixel, and the second color sub-pixel are arranged in sequence.

8. The display panel of any of claims 4-7, wherein, The display panel further comprises a plurality of time length data lines; the time length data signal terminals of the driving circuits in the same column of sub-pixels are electrically connected with the same time length data line.

9. The display panel of claim 8, wherein, The display panel further comprises a plurality of first time length data input lines, a plurality of first phase detectors, and a plurality of first charge pump circuits; wherein one time length data line corresponds to one first phase detector, one first charge pump circuit, and one first time length data input line; The first time length data input line is electrically connected with the time length data line through the corresponding first phase detector and the first charge pump circuit in sequence.

10. The display panel of claim 8, wherein, The display panel further comprises a plurality of second time length data input lines, a plurality of second phase detectors, and a plurality of second charge pump circuits; wherein one second time length data input line is electrically connected with one time length data line; one of the second phase detectors and one of the second charge pump circuits are included in one sub-pixel; for each of the sub-pixels, the time length data line is sequentially electrically connected to the time length data signal terminal of the driving circuit through the corresponding second phase detector and the second charge pump circuit.

11. A display device, wherein, The display panel comprises the display panel according to any one of claims 3-10.

12. A driving method of the driving circuit as claimed in claim 1 or 2, wherein, The display panel comprises: driving the driving circuit to work in at least one light-emitting adjustment period in a frame display time; wherein the light-emitting adjustment period comprises: a time length data writing stage, the time length control circuit provides a signal of a time length data signal terminal to a gate of the first transistor to control the first transistor to be turned on or turned off in response to a signal of a time length scanning signal terminal; and the latch circuit latches the signal of the gate of the first transistor; a light-emitting adjustment stage, the latch circuit latches the signal of the gate of the first transistor to make the first transistor keep the state in the time length data writing stage.

13. The driving method of the driving circuit according to claim 12, wherein The driving signal control circuit comprises a reset signal terminal, a display scanning signal terminal, a light-emitting control signal terminal and a display data signal terminal; in a frame display time and before the light-emitting adjustment period, the display panel further comprises: a reset stage, the driving signal control circuit is reset in response to a signal of the reset signal terminal; a compensation stage, the driving signal control circuit performs threshold compensation according to signals of the display scanning signal terminal and the display data signal terminal; in the light-emitting adjustment stage, the driving signal control circuit inputs the signal of the light-emitting control signal terminal to the first transistor to generate a driving signal for driving the light-emitting device to drive the light-emitting device to emit light in a preset time length, and the preset time length is not greater than a time length of the light-emitting adjustment stage.

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