Fan-out structure of light emitting diode (LED) devices and lighting systems

Abstract

Methods of manufacturing systems are described. One method includes attaching a silicon backplane to a carrier and molding the silicon backplane on the carrier such that a molding material surrounds a side surface of the silicon backplane to form a structure including a substrate having an embedded silicon backplane. The structure has a first surface opposite the carrier, a second surface adjacent the carrier, and a side surface. At least one via is formed through the molding material and filled with a metallic material. A metal layer is formed on a central region of the first surface of the structure. A redistribution layer is formed on the first surface of the structure adjacent the metal layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Nonprovisional Application No. 16 / 750824, filed January 23, 2020; European Patent Application No. 20158288.9, filed February 19, 2020; U.S. Provisional Application No. 62 / 951601, filed December 20, 2019; and U.S. Provisional Application No. 62 / 937629, filed November 19, 2019, the contents of which are incorporated herein by reference. Background Technology

[0003] Precision-controlled lighting applications may require the production and manufacturing of small addressable light-emitting diode (LED) lighting systems. The small size of such systems may necessitate unconventional components and manufacturing processes. Summary of the Invention

[0004] An LED lighting system, a vehicle headlight system, and a manufacturing method are described. The LED lighting system includes a silicon backplane having a top surface, a bottom surface, and a side surface, and a substrate surrounding the side surface of the silicon backplane, the substrate having a top surface, a bottom surface, and a side surface. A first redistribution layer is disposed on the top surface of the silicon backplane and the top surface of the substrate. A second redistribution layer is disposed on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one through-hole extends through the substrate between the first and second redistribution layers and is filled with a metallic material. Attached Figure Description

[0005] A more detailed understanding can be obtained by referring to the following description, which is given by way of example in conjunction with the accompanying drawings, wherein:

[0006] Figure 1A This is a top view of an example LED array;

[0007] Figure 1B This is a cross-sectional view of an example LED lighting system;

[0008] Figure 1C yes Figure 1B A top view of an example LED lighting system;

[0009] Figure 1D yes Figure 1B A bottom view of an example LED lighting system;

[0010] Figure 2 It is a combination Figure 1B A cross-sectional view of an example application system of an LED lighting system;

[0011] Figure 3 It is a combination Figure 1B A diagram of an example vehicle headlight system with LED lighting;

[0012] Figure 4 This is a diagram of another example vehicle headlight system;

[0013] Figure 5 It manufactures LED lighting systems (such as...) Figure 1B A flowchart of an example method for an LED lighting system;

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J These are cross-sectional views of an LED lighting system at various stages of the manufacturing process; and

[0015] Figure 7 It means Figure 6E Bottom view of the bottom surface of the LED lighting system. Detailed Implementation

[0016] Examples of various light illumination systems and / or light-emitting diode (“LED”) embodiments will be described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional embodiments. Therefore, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit this disclosure in any way. Similar figures always refer to similar elements.

[0017] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and a second element may be referred to as a first element. As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," there may be no intermediate elements present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements between that element and the other element. It will be understood that these terms are intended to cover different orientations of elements other than those depicted in the accompanying drawings.

[0019] Relative terms such as “below,” “above,” “over,” “under,” “horizontal,” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region illustrated in the accompanying drawings. It will be understood that these terms are intended to cover different orientations of the device other than those described in the accompanying drawings.

[0020] In addition, whether LEDs, LED arrays, electrical components and / or electronic components are housed on one, two or more electronic boards may also depend on design constraints and / or application.

[0021] Semiconductor light-emitting devices (LEDs) or optical power-emitting devices (such as devices that emit ultraviolet (UV) or infrared (IR) light power) are among the most efficient light sources available today. These devices (hereinafter referred to as "LEDs") can include light-emitting diodes, resonant cavity light-emitting diodes, vertical cavity laser diodes, edge-emitting lasers, and so on. For example, LEDs can be attractive candidates for many different applications due to their compact size and low power requirements. For instance, they can be used as light sources (e.g., flashlights and camera flashes) in handheld battery-powered devices such as cameras and mobile phones. They can also be used for applications such as automotive lighting, head-up display (HUD) lighting, garden lighting, street lighting, video torches, general lighting (e.g., lighting for homes, shops, offices, and studios, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, backlighting for displays, and IR spectrometers. A single LED may provide less light than an incandescent light source, and therefore, multi-junction devices or LED arrays (such as monolithic LED arrays, micro-LED arrays, etc.) can be used for applications that expect or require higher brightness.

[0022] Figure 1A This is a top view of example LED array 102. Figure 1AIn the illustrated example, LED array 102 is an array of emitters 120. LED arrays can be used in any application, such as those requiring precise control of the LED array emitters. The emitters 120 in LED array 102 can be individually addressable or can be addressed in groups / subsets.

[0023] Figure 1A An exploded view of a 3×3 portion of the LED array 102 is also shown. As shown in the 3×3 exploded view, the LED array 102 may include emitters 120, each having a width w1. In embodiments, the width w1 may be approximately 100 μm or less (e.g., 40 μm). The width of the channel 122 between the emitters 120 may be w2. In embodiments, the width w2 may be approximately 20 μm or less (e.g., 5 μm). The channel 122 may provide an air gap between adjacent emitters or may contain other materials. The distance d1 from the center of one emitter 120 to the center of an adjacent emitter 120 may be approximately 120 μm or less (e.g., 45 μm). It will be understood that the widths and distances provided herein are merely examples and actual widths and / or dimensions may vary.

[0024] Will understand, although Figure 1A A rectangular emitter arranged in a symmetrical matrix is ​​shown, but emitters of any shape and arrangement can be applied to the embodiments described herein. For example, Figure 1A The LED array 102 may include more than 20,000 emitters in any suitable arrangement (such as a 200×100 matrix, a symmetric matrix, an asymmetric matrix, etc.). It will also be understood that multiple sets of emitters, matrices, and / or boards may be arranged in any suitable form to implement the embodiments described herein.

[0025] As described above, an LED array (such as LED array 102) may include up to 20,000 or more emitters. Such an array may have a 90 mm diameter. 2 These LEDs may have a larger surface area and may require considerable power to power them, such as 60 watts or more. Such LED arrays can be called microLED arrays or simply microLEDs. MicroLEDs can comprise an array of individual emitters disposed on a substrate, or they can be individual silicon wafers or dies divided into segments (forming emitters). The latter type of microLED can be called a monolithic LED.

[0026] To individually drive or control individual LEDs in an array, a silicon backplane can be placed near the LED array, and this backplane can become very hot during operation. Therefore, heat dissipation can be challenging for such devices. While some solutions for heat dissipation in semiconductor devices are known, these solutions typically involve structures that dissipate heat through the top of the device. However, due to light emission, LED arrays (such as…) Figure 1A The LED array 102 may not be able to dissipate heat through the top of the device.

[0027] Additionally, LED arrays (such as LED array 102) can be used in applications such as vehicle headlight systems, and may include passive components (such as resistors and capacitors) that can form drivers, controllers, and other circuitry. It may be desirable to package at least some of the passive components with the LED array.

[0028] The embodiments described herein can provide a low-profile LED array package that can accommodate one or more passive components and enable the dissipation of heat generated by the silicon backplane and the LED array.

[0029] Figure 1B This is a cross-sectional view of an example LED lighting system 100. Figure 1B In the illustrated example, the LED lighting system 100 includes a silicon backplane 104. The silicon backplane 104 has a top surface 101, a bottom surface 103, and a side surface 105. The side surface 105 of the silicon backplane 104 is surrounded by a substrate 106 (formed from a molding material). The substrate 106 has a top surface 107, a bottom surface 109, and a side surface 190. One or more metal layers 110 or redistribution layers (RDLs) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106. Figure 6E (As shown in an alternative embodiment). RDL 117 may be formed on at least a portion of the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106. Figure 1B In the example illustrated, RDL 117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. One or more vias 108 may extend through the substrate 106 and may be filled with a metallic material. The vias thus form a continuous electrical connection between the silicon backplane 104, RDL 117, and the metallized / RDL 110. LED arrays (such as...) Figure 1A The LED array 102 can be disposed on the top surface 101 of the silicon backplane 104 and connected via a metal connector array ( Figure 1B (Not shown in the image) is electrically coupled to it. In an embodiment, electronic component 114 may be disposed on RDL 117 and electrically coupled to LED lighting system 100 via metal layer 112.

[0030] LED array 102 can be miniature LEDs, such as those referenced above. Figure 1A As described, the LED array 102 may have a depth d1. In an embodiment, the depth d1 may be, for example, between 5 μm and 250 μm.

[0031] The silicon backplane 104 may include circuitry and connectors for individually addressable connections to the emitters in the LED array 102. In one embodiment, the silicon backplane may be a complementary metal-oxide-semiconductor (CMOS) integrated circuit, which in another embodiment may be an application-specific integrated circuit (ASIC). The silicon backplane 104 may have a depth d3. In one embodiment, the depth d3 may be, for example, between 100 μm and 1 mm.

[0032] The structure consisting of a silicon backplane 104, a substrate 106, a metallization / RDL 110, an RDL 117, and a via 108 can have a depth d2. In embodiments, the depth d2 can be, for example, between 100 μm and 1 mm. Because the silicon backplane 104 is integrated into the substrate and the LED array 102 is disposed on top of the silicon backplane 104, the LED lighting system 100 can have a lower profile compared to systems that vertically stack one or more of these elements.

[0033] exist Figure 1B In the illustrated example, RDL 117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. The first layer 116a of the two dielectric material layers 116 may be on at least a portion of the top surface 107 of the substrate 106 and the top surface 101 of the silicon backplane 104. The metal layer 112 may be patterned on the first layer 116a of the dielectric material 116, such as by copper plating and copper etching. The second layer 116b of the dielectric material 116 may be on top of the patterned metal layer 112 and on the exposed portion of the first layer 116a of the dielectric material 116. Although in Figure 1B The diagram illustrates an RDL consisting of two layers of dielectric material and a single layer of metal; however, those skilled in the art will recognize that, depending on design constraints, RDL 117 may include more or fewer dielectric material layers and / or more metal layers. Dielectric material 116 can be any suitable dielectric material. In embodiments, the dielectric material may be a polymer dielectric material (such as polyimide).

[0034] RDL 117 can extend from the peripheral region of the silicon backplane 104 toward the side surface 190 of the substrate 106. This both accommodates the LED array 102 (attached to the top surface 101 of the silicon backplane 104) in the central region and aids in heat dissipation by including a dielectric material that can further isolate the LED lighting system 100 from areas of highest heat remote from the center of the LED lighting system 100. Metal layer 112 may have portions exposed from the dielectric material 116 to form bonding pads. Metal layer 112 may include portions extending between the peripheral region of the silicon backplane 104 and the bonding pads to create a continuous electrical connection between them. The bonding pads may be electrically coupled to via 108 to create a continuous electrical connection between the top and bottom surfaces of the LED lighting system 100. The bonding pads may be placed in the peripheral region of the substrate or spaced apart from but closer to the array (e.g., as shown in the image). Figure 1C (As shown).

[0035] Metallization / RDL 110 can be formed in a variety of different ways. Figure 1B In the illustrated example, the metallization / RDL 110 is a metal layer comprising a first portion electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region, and a second portion fanning out from the peripheral region of the silicon backplane 104 toward the side surface 190 of the substrate 106. In an embodiment, the first and second portions may be electrically insulated from each other. Although in Figure 1B While not visible in the foreground, the second portion extends from the silicon backplane 104 and engages with a separate via 108 at a bonding pad, thereby electrically coupling the silicon backplane 104 to a metal layer 112 on the top surface. Both the first and second portions of the metal layer 110 can be coupled to an external circuit board (not shown), such as by soldering. This enables a direct connection between the LED lighting system 100 and the external circuit board, providing improved heat dissipation through the bottom of the LED lighting system. Additionally, this structure enables communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106, and any electronic components on the external circuit board.

[0036] In another example (which will be referenced later) Figure 6E and Figure 7 (To be described in more detail), metallization / RDL 110 can be a combination of a metal layer and an RDL. As... Figure 1B In the illustrated embodiment, the metal layer can be electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in the central region. However, this fan-out can be achieved using an RDL instead of a metal layer. In this embodiment, the LED lighting device 100 can have RDLs on both the top and bottom surfaces.

[0037] In both cases, the metallized / RDL 110 can be a thin structure and can include significantly less dielectric material compared to conventional silicon device packages. For example, Figure 1B In the illustrated embodiment, metal layer 100 may be a single metal layer, and the RDL may include as few dielectric layers as possible. This can improve heat dissipation efficiency in such a package and enable the encapsulation of microLEDs and CMOS backplanes that may emit considerable heat.

[0038] exist Figure 1B In the illustrated LED lighting system 100, the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106 are coplanar. Similarly, the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106 are coplanar. This arrangement allows for the thinnest possible package and ease of fabrication. However, those skilled in the art will recognize that because the substrate 106 is molded, it can take any shape—such as, for example, having a top surface 107 above the top surface 101 of the silicon backplane 104—to further space the electronic components 114 from the high-heat areas of the LED lighting system 100. Therefore, in this embodiment, these surfaces may not be coplanar.

[0039] Figure 1C It shows Figure 1B A top view of the top surface 130 of an example LED lighting system 100. Figure 1C In the illustrated example, the top surface 130 of the LED lighting system includes the top layer 116b of the dielectric material 116 in the RDL 117. Electronic components 114 are electrically coupled to metal 112 in the RDL and exposed from the dielectric material 116. In an embodiment, electronic components 114 may not be electrically coupled to all areas of the metal 112, and therefore, in an embodiment, the top surface 130 may also include some areas of the metal 112 exposed from the dielectric material 116. At least a portion of the top surface of the silicon backplane 104 is in… Figure 1C The diagram shows, and includes, a portion of the top surface of the silicon backplate 104 that is not covered by the LED array 102 or the dielectric material 116. The top surface of the LED array 102 is also shown as being mounted on the top surface of the silicon backplate 104.

[0040] like Figure 1CAs shown, the LED lighting system 100 has a length l1 and a width w1. In an embodiment, the length l1 may be approximately 20 mm and the width w1 may be approximately 15 mm. The silicon backplane 104 may have a length l2 and a width w2. In an embodiment, the length l2 may be approximately 15.5 mm and the width w2 may be approximately 6.5 mm. The LED array 102 may have a length l3 and a width w3. In an embodiment, the length l3 may be approximately 11 mm and the width w3 may be approximately 4.4 mm.

[0041] Given these example dimensions, it is possible to provide a relatively large surface area (300 mm in the example above). 2 The LED array package contains a relatively large amount of surface area that is not occupied by the LED array (in the example above, the LED array has approximately 100 mm²). 2 (Surface area). Therefore, this design provides ample space for attaching electronic components to the LED array package.

[0042] Figure 1D It shows Figure 1B Bottom view of the bottom surface 140 of an example LED lighting system 100. Figure 1D In the illustrated example, the bottom surface 140 includes a region of the substrate 106 exposed from the molding material 106 and a region of the metal 110 or pads coupled thereto. In embodiments, some regions of the substrate may be partially covered by the metallization and / or RDL of the interconnect silicon backplane and bonding pads (although these are not in the...). Figure 1D (As shown in the figure). In some embodiments, the interconnect metal region and / or RDL may be covered by dielectric material or other encapsulation or protective material (as shown in the figure). Figure 1D (Not shown in the image).

[0043] Figure 2 It is a combination Figure 1B A cross-sectional view of an application system 200 of the LED lighting system 100. The application system 200 may include a circuit board 150 having a plurality of bonding pads 152. Figure 2In the illustrated example, the exposed metal area / bonding pads of the RDL / metallization 110 of the LED lighting system 100 are directly bonded to the bonding pads 152 of the circuit board 150. As described above, the direct bonding between the metal layer 110 on the bottom surface of the silicon backplane 104 and the circuit board 150 enables efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat dissipation purposes, without requiring additional heat dissipation structures on top of the LED lighting system 100 (or elsewhere) (which would otherwise potentially block light emission from the LED array 102, for example). The circuit board 150 can be used in specific applications—such as vehicle lighting or flashing applications (an example vehicle lighting system is shown below). Figure 3 and Figure 4 (As described) – part of a larger system used. In such a system, some passive components used in the application may be component 114 and may be directly mounted on the LED lighting system 100 before being attached to the circuit board 150. In addition to the heat sink, the circuit board 150 may include other circuit elements required by the larger system. RDL 117, RDL / metallization 110, and through-hole 108 can provide a continuous electrical connection between component 114, silicon backplane 104, and circuit board 150.

[0044] Figure 3 It can be combined Figure 1B A diagram of an example vehicle headlight system 300 with an LED lighting system 100. Figure 3 The illustrated example vehicle headlight system 300 includes a power line 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED DC-DC (DC / DC) module 312, a logic low-dropout (LDO) module 314, a microcontroller 316, and an active headlight 318. In an embodiment, the active headlight 318 may include an LED lighting system (such as...) Figure 1B The LED lighting system 100, as described above, provides ample space and bonding pads on the top surface of the substrate, enabling... Figure 3 One, more, or all of the modules illustrated can be housed on the top surface of the LED lighting system 100. Modules not disposed on the top surface of the LED lighting system 100 can be disposed on the circuit board 150 (e.g., Figure 2 (As shown). In some embodiments, some electronic components of some or all modules of the vehicle lighting system 300 may be housed on the top surface of the LED lighting system 100, and some may be mounted on the circuit board 150 (e.g., Figure 2 (As shown).

[0045] Power line 302 may have an input for receiving power from the vehicle, and data bus 304 may have input / output terminals through which data can be exchanged between the vehicle and the vehicle headlight system 300. For example, the vehicle headlight system 300 may receive commands from other locations within the vehicle, such as commands to turn on turn signals or turn on headlights, and may send feedback to other locations within the vehicle if needed. Sensor module 310 may be communicatively coupled to data bus 304 and may provide additional data to the vehicle headlight system 300 or other locations within the vehicle, such additional data relating to environmental conditions (e.g., time of day, rain, fog, or ambient light level), vehicle status (e.g., parked, moving, speed, or direction of movement), and the presence / location of other objects (e.g., vehicles or pedestrians). A headlight controller separate from any vehicle controller (communically coupled to the vehicle data bus) may also be included in the vehicle headlight system 300. Figure 3 In this case, the headlight controller can be a microcontroller, such as a microcontroller (μc) 316. The microcontroller 316 can be communicatively coupled to a data bus 304.

[0046] The input filter and protection module 306 can be electrically coupled to the power line 302 and can, for example, support various filters to reduce conducted emissions and provide power immunity. Furthermore, the input filter and protection module 306 can provide electrostatic discharge (ESD) protection, load drop protection, alternator field attenuation protection, and / or reverse polarity protection.

[0047] LED DC / DC module 312 can be coupled between filter and protection module 306 and active headlamp 318 to receive filtered power and provide drive current to power the LEDs in the LED array in active headlamp 318. LED DC / DC module 312 can have an input voltage between 7 and 18 volts, with a nominal voltage of approximately 13.2 volts, and an output voltage that can be slightly higher (e.g., 0.3 volts) than the maximum voltage of the LED array (e.g., determined by factory or local calibration and operating condition adjustments due to load, temperature, or other factors).

[0048] The logic LDO module 314 can be coupled to the input filter and protection module 306 to receive filtered power. The logic LDO module 314 can also be coupled to the microcontroller 314 and the active headlight 318 to provide power to the silicon backplane (e.g., CMOS logic) in the microcontroller 314 and / or the active headlight 318.

[0049] Bus transceiver 308 may have, for example, a Universal Asynchronous Receiver / Transmitter (UART) or Serial Peripheral Interface (SPI) interface and may be coupled to microcontroller 316. Microcontroller 316 may convert vehicle inputs based on or including data from sensor module 310. The converted vehicle inputs may include video signals that can be passed to an image buffer in active headlight module 318. Furthermore, microcontroller 316 may load a default image frame and perform tests for open / short-circuit pixels during startup. In an embodiment, the SPI interface may load the image buffer in CMOS. The image frame may be a full frame, differential, or partial frame. Other features of microcontroller 316 may include a control interface monitoring CMOS states and logic LDO outputs, including die temperature. In an embodiment, the LED DC / DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlight functions—such as complementary use with sidemarkers or turn signals and / or activation of daytime running lights—may also be controlled.

[0050] Figure 4 This is a diagram of another example vehicle headlight system 400. Figure 4 The illustrated example vehicle headlight system 400 includes an application platform 402, two LED lighting systems 406 and 408, and optics 410 and 412. The two LED lighting systems 406 and 408 can be LED lighting systems (such as...) Figure 1B LED lighting system 100), or may include LED lighting system 100 plus Figure 3 All or some of the other modules in the vehicle headlight system 300. In a later embodiment, LED lighting systems 406 and 408 may be vehicle headlight subsystems.

[0051] LED lighting system 408 can emit beam 414 (in) Figure 4 (Indicated between arrows 414a and 414b). The LED lighting system 406 can emit a beam 416 (in... Figure 4 (Indicated between arrows 416a and 416b). Figure 4 In the illustrated embodiment, secondary optics 410 are adjacent to LED lighting system 408, and light emitted from LED lighting system 408 passes through secondary optics 410. Similarly, secondary optics 412 are adjacent to LED lighting system 406, and light emitted from LED lighting system 412 passes through secondary optics 406. In an alternative embodiment, secondary optics 410 / 412 are not provided in the vehicle headlight system.

[0052] In cases including secondary optics 410 / 412, the secondary optics 410 / 412 may be one or more light guides or may include one or more light guides. The one or more light guides may be edge-illuminating or may have internal openings defining internal edges of the light guides. LED lighting systems 408 and 406 (or active headlights of a vehicle headlight subsystem) may be embedded in the internal openings of the one or more light guides, such that they inject light into the internal edges (internal opening light guides) or external edges (edge-illuminating light guides) of the one or more light guides. In embodiments, the one or more light guides may shape the light emitted by LED lighting systems 408 and 406 in a desired manner (e.g., with a gradient, chamfered distribution, narrow distribution, wide distribution, or angular distribution).

[0053] Application platform 402 can provide power and / or data to LED lighting systems 406 and / or 408 via line 404, which may include Figure 3 One or more of the power line 302 and data bus 304. One or more sensors (which may be sensors in system 300 or other additional sensors) may be inside or outside the housing of application platform 402. Alternatively or additionally, such as Figure 3 As shown in the example LED lighting system 300, each LED lighting system 408 and 406 may include its own sensor module, connection and control module, power supply module and / or LED array.

[0054] In an embodiment, the vehicle headlight system 400 may represent a car with a controllable beam of light, wherein LEDs can be selectively activated to provide controllable light. For example, an LED array (e.g., LED array 102) may be used to define or project a shape or pattern, or to illuminate only selected portions of a road. In an example embodiment, infrared camera or detector pixels within LED systems 406 and 408 may be sensors (e.g., similar to...) that identify portions of a scene that require illumination (e.g., a road or pedestrian crossing). Figure 3 (The sensor in sensor module 310).

[0055] Figure 5 It manufactures LED lighting systems (such as...) Figure 1B A flowchart of an example method 500 for an LED lighting system 100. Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6JThese are cross-sectional views of the LED lighting system at various stages of the manufacturing process. In this embodiment, method 500 can produce a high-density LED lighting system in a panel-level package.

[0056] exist Figure 5 In example method 500, a silicon backplane may be attached to a first carrier (502) to form a first structure. In embodiments, the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material (such as tape or temporary adhesive). Example 600A of the first structure is... Figure 6A The diagram shows a silicon backplane 104, a first carrier 602, and an optional adhesive material 604.

[0057] The silicon backplane attached to the first carrier can be molded (504) to form a second structure. Example 600B of the second structure is shown in... Figure 6B The diagram in the middle, and includes Figure 6A The first structure 600A includes a molding material surrounding the side of a silicon backplane 104. The molding material forms a substrate 106 with the embedded silicon backplane 104. In an embodiment, a mold can be placed on top of structure 600A, filled with the molding material, and cured. Any excess molding material can be removed from the top surface of the silicon backplane if desired. In an embodiment, molding can be panel-level molding, the molding material can be a polymer material, and the second structure 600B can be a plastic substrate with an embedded silicon backplane on a temporary substrate.

[0058] One or more vias (506) can be formed through the substrate to form a third structure. In an embodiment, the one or more vias can be formed using a laser or drilling. Example 600C of the third structure is... Figure 6C The diagram shows a silicon backplane 104 embedded in a substrate 106, with two through-holes 108 formed through the substrate 106. At this stage, the silicon backplane 104 and the substrate 106 with the through-holes 108 can remain attached to a first temporary carrier 602. The through-holes 108 can be filled with a metallic material.

[0059] At least one metal layer (508) can be formed on one surface of the silicon backplane and on the substrate. This can be done in a variety of different ways.

[0060] In some embodiments, a metal layer may be patterned or electroplated on one surface of the silicon backplane and the substrate to form a fourth structure. Figure 6D Example 600D of the fourth structure is illustrated, which includes a third structure with a metal layer 110. From Figure 6D As can be seen, the metal layer 110 forms bonding pads over the vias and regions extending from the peripheral region of the silicon backplane 104. The metal layer is also disposed on the central region of one surface of the silicon backplane 104. Figure 1DThe bottom view of the illustrated LED lighting system 100 shows such an example.

[0061] In other embodiments, a metal layer may be formed on one surface of a silicon backplane in the central region, and a redistribution layer may be formed adjacent to a single metal layer on one surface of the silicon backplane and on the substrate to form a fifth structure. Figure 6E An example 600E of the fifth structure is illustrated, which includes a third structure having a single metal layer 618 and a redistribution layer 616. Figure 6E In the illustrated example, the redistribution layer 616 comprises a layer of dielectric material 614 and a metal layer 612. Although in Figure 6E The diagram shows three metal layers, but due to design constraints, one, two, or more metal layers can be used if desired. For example, a redistribution layer can be formed by alternately depositing layers of dielectric material, selectively removing portions of the dielectric material (if desired), and patterning the top metal layer. Figure 6E As can be seen, metal layer 612 begins in the peripheral region of one surface of the silicon backplane and extends toward the side surface of the substrate. Metal layer 612 is electrically coupled between silicon backplane 104 and via. A portion of metal layer 612 is exposed from dielectric material 614 to form pads, or individual pads may be formed on the outermost surface of the outermost dielectric layer.

[0062] Figure 7 It means Figure 6E A bottom view of the bottom surface 700 of the LED lighting system. Line 702 represents the outermost periphery of the substrate. Line 104 represents the outermost periphery of the area occupied by the silicon backplane 104 relative to the outermost periphery of the substrate. Dashed line 704 represents the boundary of the area between line 704 and the outermost periphery of the silicon backplane 104, which may be referred to herein as the peripheral region of the silicon backplane 104. The metal layer 612 of the redistribution layer 616 may begin in this peripheral region and extend toward the side surface of the substrate (described by line 702). A gap exists between the boundary 704 of the peripheral region of the silicon backplane and a single metal layer 618 formed on one surface of the silicon backplane. This gap may be filled with a dielectric material, such as... Figure 6E What is reflected.

[0063] The structure formed as a result of 508 (e.g., a fourth or fifth structure) can be flipped and attached to a second carrier (510) to form a sixth structure. In an embodiment, the structure (e.g., a fourth or fifth structure) can be attached to a temporary (e.g., plastic) carrier via an adhesive material (such as tape or a temporary adhesive). The structure can be placed together with at least one metal layer adjacent to the second carrier. Example 600G of the sixth structure is shown in... Figure 6GThe diagram shows a second carrier 608 and an optional adhesive material 606. Once the structure is attached to the second carrier, the first carrier can be removed (512) to form the seventh structure. Figure 6G Example 600G of the seventh structure is shown in the figure.

[0064] A redistribution layer and a metal connector array (514) can be formed on the surface exposed by removing the second carrier to form an eighth structure. In an embodiment, the metal connector array can be formed by electroplating or otherwise patterning or forming an array of copper pillar bumps on the surface. Example 600H of the eighth structure is shown in... Figure 6H The diagram shows a metal connector 640 and a redistribution layer 117, the redistribution layer 117 comprising at least one metal layer 112 and a dielectric material 116. (Refer to the above text.) Figure 6E The redistribution layer can be formed by alternating layers of dielectric material, selectively removing portions of the dielectric material (if desired), and patterning a metal layer on top. In an embodiment, more than 20,000 (e.g., approximately 28,000) metal connectors can be formed on the surface.

[0065] The LED array can be attached to a silicon backplane (516) via an electrical connector to form the ninth structure. In an embodiment, this can be performed by aligning the silicon backplane with the electrical connector and applying heat to reflow the solder copper material in the copper pillar bumps. The reflow creates underfill beneath the LED array. In an embodiment, the LED array can be a monolithic LED array. Example 600I of the ninth structure is shown in... Figure 6I The diagram shows the LED array 102 and the bottom filler.

[0066] The LED array can undergo a laser lift-off (LLO) process and phosphor integration (518). Any passive component can be mounted on the exposed metal region in the redistribution layer 117 to form a tenth structure. An example 600J of the tenth structure is illustrated in Figure 600J and includes an LED array 102 with phosphor material 610 and passive component 114.

[0067] Optionally, the tenth structure (which may be an LED lighting system, such as...) Figure 1B The LED lighting system 100 can be mounted on an external circuit board (520) so as to integrate the LED lighting system 100 into vehicle headlights or other application systems, for example.

[0068] The embodiments have been described in detail, and those skilled in the art will appreciate that, given this specification, modifications can be made to the embodiments described herein without departing from the spirit of the inventive concept. Therefore, it is intended that the scope of the invention is not limited to the specific embodiments illustrated and described.

Claims

1. A method for manufacturing a system, the method comprising: Attach the silicon backplane to the carrier; The silicon backplate is molded on the carrier such that molding material surrounds the side surface of the silicon backplate to form a structure including a substrate having an embedded silicon backplate, the structure having a first surface opposite to the carrier, a second surface adjacent to the carrier, and a side surface; At least one through-hole is formed through the molding material; The at least one through hole is filled with a metallic material; A metal layer is formed on the central region of the first surface of the structure, such that the metal layer is electrically and thermally coupled to the silicon backplane; A redistribution layer is formed on a first surface of the structure adjacent to the metal layer, such that the redistribution layer is electrically insulated from the metal layer; Remove the carrier; as well as A copper pillar bump array is formed on the surface of the silicon backplane exposed by removing the carrier.

2. The method of claim 1, wherein forming the redistribution layer comprises: A first layer of dielectric material is formed on the first surface of the structure. A metal layer is patterned on the first layer of the dielectric material such that at least a portion of the metal layer remains in contact with the at least one via, and at least another portion of the metal layer remains in contact with the silicon backplane. A second layer of the dielectric material is formed on the first layer of the dielectric material and the metal layer, and Remove a portion of the second layer of the dielectric material that covers the area of ​​the first metal layer corresponding to the bonding pad location.

3. The method of claim 2, further comprising attaching another carrier to the redistribution layer prior to removing the carrier.

4. The method of claim 3, further comprising forming other redistribution layers on the second surface of the structure.

5. The method of claim 1, further comprising: Align the LED array with the copper pillar bump array; as well as Heat is applied to recirculate the copper pillar bumps.

6. The method of claim 5, further comprising: Laser stripping is performed on the LED array; as well as Phosphor integration is performed on the LED array.

7. The method of claim 5, wherein aligning the LED array with the copper pillar bump array comprises aligning the LED array comprising up to 20,000 emitters with the copper pillar bump array comprising at least one copper pillar bump for each emitter.

8. A method for manufacturing a system, the method comprising: Attach the silicon backplane to the carrier; The silicon backplate is molded on the carrier such that molding material surrounds the side surface of the silicon backplate to form a structure including a substrate having an embedded silicon backplate, the structure having a first surface opposite to the carrier, a second surface adjacent to the carrier, and a side surface; At least one through-hole is formed through the molding material; The at least one through hole is filled with a metallic material; A metal layer is patterned on a first surface of the structure, the metal layer having a first portion thermally coupled to the bottom surface of the silicon backplane in a central region and a second portion extending between the peripheral region of the silicon backplane and at least one bonding pad and electrically insulated from the first portion. Remove the carrier; as well as A copper pillar bump array is formed on the surface of the silicon backplane exposed by removing the carrier.

9. The method of claim 8, further comprising attaching another carrier to the metal layer prior to removing the carrier.

10. The method of claim 9, further comprising forming additional redistribution layers on the second surface of the structure.

11. The method of claim 8, further comprising: Align the LED array with the copper pillar bump array; as well as Heat is applied to recirculate the copper pillar bumps.

12. The method of claim 11, further comprising: Laser stripping is performed on the LED array; as well as Phosphor integration is performed on the LED array.

13. The method of claim 11, wherein aligning the LED array with the copper pillar bump array comprises aligning the LED array comprising up to 20,000 emitters with the copper pillar bump array comprising at least one copper pillar bump for each emitter.

14. The method of claim 12, further comprising attaching at least one electronic component to at least one redistribution layer on the surface of the silicon backplane exposed by removing the carrier and on the molding material.

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