Conductive enhancement layer for electrical contact areas in power devices

Abstract

A power switching device includes a semiconductor layer structure, a plurality of unit cell transistors electrically connected in parallel, and a gate connector, each unit cell transistor including gate fingers having longitudinal axes extending in a first direction on the semiconductor layer structure, the gate fingers being spaced apart from each other in a second direction, the gate connector having a longitudinal axis extending in the second direction, the gate connector being connected to the gate fingers of the plurality of unit cell transistors.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 863,797, filed April 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices, and more particularly, to power semiconductor switching devices. Background Technology

[0004] A metal-insulating semiconductor field-effect transistor (“MISFET”) is a well-known semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having a gate terminal, a drain terminal, and a source terminal, as well as a semiconductor body. The source and drain regions are formed in the semiconductor body, separated by a channel region, and the gate electrode (which can act as a gate terminal or be electrically connected to a gate terminal) is positioned adjacent to the channel region. The MISFET can be turned on or off by applying a bias voltage to the gate electrode. When the MISFET is turned on (i.e., it is in its “on state”), current flows through the channel region of the MISFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current flow stops through the channel region. For example, an n-type MISFET has an n-type source region and an n-type drain region, as well as a p-type channel. Therefore, an n-type MISFET has an “npn” design. An n-type MISFET is turned on when a gate bias voltage is applied to the gate electrode sufficient to generate a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and n-type drain regions, thereby allowing the conduction of majority carriers between the n-type source and n-type drain regions.

[0005] The gate electrode of a power MISFET is typically separated from the channel by a thin gate insulator. In most cases, the gate insulator is an oxide (e.g., silicon oxide). MISFETs with oxide gate insulators are called metal-oxide-semiconductor field-effect transistors (“MOSFETs”). Since oxide gate insulators are almost always used due to their superior properties, the discussion herein will focus on MOSFETs rather than MISFETs; however, it will be appreciated that the techniques described herein according to embodiments of the invention are equally applicable to devices having gate insulators formed of materials other than oxides.

[0006] Because the gate electrode of a MOSFET is insulated from the channel region through a gate insulator, a minimum gate current is required to keep the MOSFET in its on state or to switch it between its on and off states. Since the gate and channel region form a capacitor, the gate current remains small during switching. Therefore, only minimal charging and discharging current is required during switching, allowing for simpler gate drive circuitry and faster switching speeds. A MOSFET can be a standalone device or combined with other circuitry. For example, an insulated-gate bipolar transistor (“IGBT”) is a semiconductor device that combines a MOSFET and a bipolar junction transistor (“BJT”), combining the high-impedance gate electrode of the MOSFET with the small on-state conduction losses that can be provided by the BJT. For example, an IGBT can be implemented as a Darlington pair comprising a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, allowing for simplified external drive circuitry (since the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0007] The demand for high-power semiconductor switching devices that can carry large currents in their "on" state and block large voltages (e.g., thousands of volts) in their reverse blocking state is increasing. To support high current densities and block such high voltages, power MOSFETs and IGBTs typically have a vertical structure where the source and drain are located on opposite sides of a thick semiconductor layer structure to block higher voltage levels. In very high-power applications, semiconductor switching devices are typically formed in wide-bandgap semiconductor material systems (here, the term "wide-bandgap semiconductor" includes any semiconductor having a bandgap of at least 1.4 eV), such as, for example, silicon carbide ("SiC"), which has several advantageous characteristics, including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Compared to devices formed using other semiconductor materials (such as, for example, silicon), electronic devices formed using silicon carbide can have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities. Summary of the Invention

[0008] According to some embodiments of the present invention, a semiconductor device includes: a semiconductor layer structure; a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor including a gate finger on the semiconductor layer structure having a longitudinal axis extending in a first direction, the gate fingers being spaced apart from each other in a second direction; and a gate connector having a longitudinal axis extending in the second direction, the gate connector being connected to the gate fingers of the plurality of unit cell transistors.

[0009] In some embodiments, the gate connector includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

[0010] In some embodiments, the thickness of the gate connector is between 10 nm and 500 nm.

[0011] In some embodiments, the gate connector is a first portion of the gate connector, and the gate connector further includes a second portion extending in the first direction to contact the upper surface of the gate finger of one of the plurality of unit cell transistors.

[0012] In some embodiments, the gate connector further includes a third portion extending in the first direction below the upper surface of the semiconductor layer structure.

[0013] In some embodiments, the lower surface of the gate connector contacts the surface of the gate finger.

[0014] In some embodiments, the gate electrode of one of the gate fingers extends below the upper surface of the semiconductor layer structure.

[0015] In some embodiments, the gate electrode contacts a portion of the gate connector.

[0016] In some embodiments, the semiconductor device further includes a connector insulating layer between the gate connector and the semiconductor layer structure.

[0017] In some embodiments, the connector insulating layer extends in the second direction between adjacent gate fingers on the upper surface of the semiconductor layer structure.

[0018] In some embodiments, the gate connector is physically connected to a corresponding gate finger among the gate fingers.

[0019] According to some embodiments of the present invention, a semiconductor device includes: a semiconductor layer structure; a gate pad on the semiconductor layer structure; and a gate electrode structure on the semiconductor layer structure and electrically coupled to the gate pad. The gate electrode structure includes: a plurality of gate fingers, each gate finger including a first material extending in a first direction on the semiconductor layer structure; and a gate connector including a second material extending on and connected to one of the plurality of gate fingers.

[0020] In some embodiments, the first conductivity of the first material of the gate is lower than the second conductivity of the second material of the gate connector.

[0021] In some embodiments, the first material includes polycrystalline silicon or silicide.

[0022] In some embodiments, the second material includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

[0023] In some embodiments, the gate connector extends in a second direction intersecting the first direction, and the gate connector extends over the plurality of gate fingers.

[0024] In some embodiments, the gate connector includes a first portion and a second portion, the first portion of the gate connector extending over the plurality of gate fingers in a first direction, and the second portion of the gate connector extending over the plurality of gate fingers in a second direction.

[0025] In some embodiments, the gate connector further includes a third portion extending in the first direction below the upper surface of the semiconductor layer structure.

[0026] In some embodiments, the gate connector extends in the first direction and extends over one of the plurality of gate fingers.

[0027] In some embodiments, the respective gate electrodes of the plurality of gate fingers extend below the upper surface of the semiconductor layer structure.

[0028] In some embodiments, the semiconductor device further includes a connector insulating layer extending between adjacent gate fingers among the plurality of gate fingers, and the connector insulating layer is located between the gate connector and the semiconductor layer structure.

[0029] In some embodiments, the semiconductor device further includes a connector electrode layer between the connector insulating layer and the gate connector.

[0030] According to some embodiments of the present invention, a semiconductor device includes: a semiconductor layer structure; a first gate electrode and a second gate electrode on the semiconductor layer structure; and a gate connector extending on and connected to the first gate electrode, extending on and connected to the second gate electrode, and extending over a portion of the semiconductor layer structure between the first gate electrode and the second gate electrode.

[0031] In some embodiments, the semiconductor device further includes a connector insulating layer between the gate connector and the semiconductor layer structure.

[0032] In some embodiments, the connector insulating layer extends between the first gate electrode and the second gate electrode.

[0033] In some embodiments, the gate connector includes a first material, and the first gate electrode and the second gate electrode include a second material different from the first material.

[0034] In some embodiments, the first conductivity of the first material of the first gate electrode and the second gate electrode is lower than the second conductivity of the second material of the gate connector.

[0035] In some embodiments, the first material includes polycrystalline silicon or silicide.

[0036] In some embodiments, the second material includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

[0037] In some embodiments, the gate connector includes multiple layers.

[0038] In some embodiments, the gate connector is a first portion of the gate connector, and the gate connector further includes a second portion that intersects with the first portion to contact the upper surface of the first gate electrode.

[0039] In some embodiments, the gate connector further includes a third portion that contacts the first gate electrode below the upper surface of the semiconductor layer structure.

[0040] In some embodiments, the gate connector is physically connected to the first gate electrode and the second gate electrode. Attached Figure Description

[0041] Figure 1A This is a schematic plan view of a semiconductor wafer including multiple power switching devices according to an embodiment of the present invention.

[0042] Figure 1B Is included Figure 1A A schematic plan view of one of the power switching devices on a semiconductor wafer.

[0043] Figure 1C yes Figure 1B A schematic plan view of an example power switching device, in which the source and gate metallization have been removed. Figure 1D yes Figure 1BA schematic plan view of an additional example of a power switching device.

[0044] Figure 2A This is a schematic plan view of a power switching device according to some embodiments of the present disclosure. Figure 2B yes Figure 2A A schematic enlarged perspective view of part 'A'. Figure 2C It is along Figure 2B A schematic cross-sectional view taken from line 2C-2C. Figure 2D It is along Figure 2B A schematic cross-sectional view of the line cut in 2D-2D. Figure 2E This is a schematic cross-sectional view of an additional configuration of the gate electrode according to some embodiments of the present disclosure.

[0045] Figures 3A to 3F The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 2A to 2D A schematic cross-sectional view of a method for power switching devices.

[0046] Figure 4A This is a schematic perspective view of a portion of a power switching device according to some embodiments of the present disclosure. Figure 4B It is along Figure 4A A schematic cross-sectional view taken from line 4B-4B. Figure 4C It is along Figure 4A A schematic cross-sectional view taken from line 4C-4C.

[0047] Figures 5A to 5D The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 4A to 4C A schematic cross-sectional view of a method for power switching devices.

[0048] Figure 6A This is a schematic plan view of a power switching device according to some embodiments of the present disclosure. Figure 6B yes Figure 6A A schematic enlarged perspective view of part 'B'. Figure 6C It is along Figure 6B A schematic cross-sectional view taken from line 6C-6C. Figure 6D It is along Figure 6B A schematic cross-sectional view taken from line 6D-6D. Figure 6E This is a schematic perspective view of an additional configuration of a power switching device according to some embodiments of the present disclosure.

[0049] Figure 7A This is a schematic perspective view of a portion of a power switching device according to some embodiments of the present disclosure. Figure 7B It is along Figure 7A A schematic cross-sectional view taken from line 7B-7B. Figure 7C It is along Figure 7A A schematic cross-sectional view taken from line 7C-7C. Figure 7D This is a schematic perspective view of an additional configuration of a power switching device according to some embodiments of the present disclosure.

[0050] Figures 8A to 8D The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 7A to 7C A schematic cross-sectional view of a method for power switching devices.

[0051] Figure 9A This is a schematic perspective view of a portion of a power switching device according to some embodiments of the present disclosure. Figure 9B It is along Figure 9A A schematic cross-sectional view taken from line 9B-9B. Figure 9C It is along Figure 9A A schematic cross-sectional view taken from line 9C-9C.

[0052] Figure 10A This is a schematic perspective view of a portion of a power switching device according to some embodiments of the present disclosure. Figure 10B It is along Figure 10A A schematic cross-sectional view taken from line 10B-10B. Figure 10C It is along Figure 10A A schematic cross-sectional view taken from line 10C-10C. Figure 10D This is a schematic perspective view of an additional configuration of a power switching device according to some embodiments of the present disclosure. Detailed Implementation

[0053] Currently, power silicon carbide MOSFETs are used in applications requiring high voltage blocking (such as 5,000 volts or higher). For example, a rated current density of 10 A / cm² is used. 2Silicon carbide MOSFETs, capable of blocking voltages of at least 10 kV or higher, are commercially available. To form such devices, multiple "unit cell" structures are typically formed, each containing a MOSFET transistor. In high-power applications, a large number of these unit cells (e.g., hundreds or thousands) are typically provided on a single semiconductor substrate, with a gate electrode formed on the top side of the substrate, serving as the gate electrode for all unit cells. The opposite (bottom) side of the semiconductor substrate serves as the common drain for all unit cells of the device. Multiple source contacts are formed on source regions in the semiconductor layer structure, exposed within openings in the gate electrode. These source contacts are also electrically connected to each other to serve as a common source. The resulting device has three terminals: a common source terminal, a common drain terminal, and a common gate electrode, which serve as terminals for hundreds or thousands of individual unit cell transistors. It will be appreciated that the above description is for n-type MOSFETs; for p-type MOSFETs, the drain and source positions are reversed.

[0054] The gate electrode of a power MOSFET can be implemented by forming a patterned conductive layer comprising a plurality of elongated gate fingers extending through the active region of the device. The patterned conductive layer may include a semiconductor layer, such as, for example, a polysilicon layer and / or doped silicon (Si). The patterned conductive layer may also include gate pads in the passive region of the device, and each gate finger may be connected to the gate pad directly or through one or more gate buses and / or conductive vias.

[0055] This disclosure describes a method for better control of the gate resistance of power MOSFETs and / or IGBTs (e.g., gate control devices). The embodiments described herein can be helpful for both planar gate devices and trench gate devices. For example, some device structures provide only a small volume or region for the gate electrode, such as in a narrow, filled trench. Therefore, a method is needed to properly connect them so that the gate signal can be applied uniformly and quickly (in a timely manner) throughout the device.

[0056] The methods described herein can provide a device with lower gate resistance associated with the gate electrode by using vertical interconnects coupled to the top surface of the gate electrode and by using a material that is more conductive than the material used for the gate electrode. For example, a gate connector comprising a material that is more conductive than the material of the gate electrode can be used. The material of the gate electrode can include, but is not limited to, polycrystalline silicon (Si) (also referred to herein as "polysilicon" or "poly"). The embodiments described herein can help reduce gate resistance in gate control devices, including trench devices and / or planar devices, and improve the ability to switch efficiently at high frequencies.

[0057] Figure 1A This is a schematic plan view of a wafer 10 including a plurality of power switching devices 100 according to an embodiment of the present invention. (See reference) Figure 1A The wafer 10 may be a thin planar structure comprising a semiconductor layer structure on which other material layers, such as insulating layers and / or metal layers, are formed. The semiconductor layer structure may include a semiconductor substrate and / or multiple other semiconductor layers. Multiple power switching devices 100 may be formed using the wafer 10. The switching devices 100 may be formed in rows and columns and may be spaced apart from each other, such that the wafer 10 may subsequently be monolithized (e.g., diced) to separate the individual switching devices 100 for packaging and testing. In some embodiments, the wafer 10 may include a silicon carbide substrate on which one or more silicon carbide layers (e.g., by epitaxial growth) are formed. Other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers may be formed on the silicon carbide semiconductor layer structure to form the power switching device 100. In some embodiments, the silicon carbide substrate and the silicon carbide layers formed thereon may be 4H silicon carbide, but this disclosure is not limited thereto. Figure 1A The number and arrangement of the power switching devices 100 shown are merely examples of exaggerated dimensions of the power switching devices 100 for ease of description.

[0058] Figure 1B Is included Figure 1A A schematic plan view of one of the power switching devices 100 on a semiconductor wafer 10. Figure 1C and Figure 1D yes Figure 1B This is a schematic plan view of an example of a power switching device 100, in which the source and gate metallization have been removed. In the following description, it is assumed that the power switching device 100 is an n-type power MOSFET 100, but the invention is not limited thereto. The embodiments described herein can also be applied to p-type devices.

[0059] like Figure 1BAs shown, the protective layer 110 covers most of the top surface of the power MOSFET 100. The protective layer 110 may be formed of, for example, polyamide. Various bonding pads may be exposed through openings 112 in the protective layer 110. The bonding pads may include a gate bonding pad 120 and one or more source bonding pads 122. Figure 1B The configuration, shape, and structure of the gate bonding pad 120 and source bonding pad 122 shown are merely examples, and the embodiments described herein are not limited thereto. Figure 1B The image shows two source bonding pads, 122-1 and 122-2. Although in... Figure 1B While not visible, drain contacts and / or bonding pads 124 may be provided on the bottom side of MOSFET 100. Bonding pads 120, 122, and 124 may be formed of metal (such as aluminum), and bonding lines may be easily attached to them via conventional techniques such as thermoforming or soldering. Source contacts may be provided to the semiconductor layer structure of the MOSFET 100. The source contacts may be the lower portion of the source metal layer 123 extending across a large portion of the upper surface of MOSFET 100 (e.g., all of the upper surface of MOSFET 100 except for the portion occupied by gate bonding pad 120). Source bonding pads 122-1 and 122-2 may include portions of the source metal layer 123 exposed by openings 112 in the protective layer 110. Bonding lines 20 in... Figure 1B As shown, it can be used to connect the gate bonding pad 120 and the source pads 122-1, 122-2 to an external voltage source (not shown), such as terminals of other circuit elements.

[0060] like Figure 1C As shown, the MOSFET 100 includes a semiconductor layer structure comprising an active region 102 and a passive region 104. The active region 102 is the area of ​​the device that includes operable transistors (e.g., unit cell transistors discussed herein), while the passive region 104 is the area that does not include such operable transistors. The unit cell transistors of the MOSFET 100 are formed in the active region 102. The positions of the plurality of unit cells are determined by… Figure 1C Box 105 in the diagram is shown to provide context.

[0061] In some embodiments, the active region 102 may generally correspond to the region beneath the source metal layer 123. The passive region 104 includes a gate pad portion 106 and a termination portion 108. The gate pad portion 106 of the passive region 104 may generally correspond to the portion of the semiconductor layer structure beneath the gate bonding pad 120. The termination portion 108 of the passive region 104 may extend around the periphery of the MOSFET 100 and may include one or more termination structures, such as junction termination extensions and / or guard rings that can reduce electric field congestion that may occur around the edges of the device. The termination structures (shown as guard ring 109) can disperse the electric field along the periphery of the MOSFET 100, thereby reducing electric field congestion. Edge termination structures can be used to increase the reverse blocking voltage, at which a phenomenon known as "avalanche breakdown" occurs, where the increased electric field causes runaway generation of charge carriers within the semiconductor device, resulting in a sharp increase in current that can damage or even destroy the device.

[0062] like Figure 1C As further shown, a gate electrode structure 130 may be provided, including a gate pad 132, a plurality of gate fingers 134, and one or more gate buses 136 electrically connecting the gate fingers 134 to the gate pad 132. The gate pad 132 of the gate electrode structure 130 may be below the gate bonding pad 120 in the gate pad portion 106 of the passive region 104, and the gate fingers 134 may extend (e.g., horizontally) across the active region 102. An insulating layer (not shown) may cover the gate fingers 134 and the gate buses(s) 136(s). A source metal layer 123 may be provided over the gate fingers 134 and the insulating layer, wherein source contacts of the source metal layer contact corresponding source regions in the semiconductor layer structure in the openings between the gate fingers 134.

[0063] refer to Figure 1C The gate finger 134 can distribute the gate signal of the power switching device 100 throughout the active region 102. In some embodiments, the gate finger and / or bar 134 of the gate electrode can be in a common direction (e.g., Figure 1C It extends in the X direction. In some embodiments, gate finger 134 may include a conductive material (e.g., polysilicon or silicide). In some embodiments, gate finger 134 may be connected to gate bus 136. Thus, a gate signal applied to power switching device 100 can be transmitted from gate bonding pad 120 to gate pad 132, to gate bus 136, and then to gate finger 134. In some embodiments, the connection between gate finger 134 and gate bus 136 may occur only at opposite ends of gate finger 134.

[0064] The gate finger 134 can be implanted in a trench configuration, wherein a portion of the gate finger 134 extends below the upper surface of the semiconductor layer structure, and / or the gate finger 134 can be implanted in a planar configuration, wherein the gate finger 134 extends on the upper surface of the semiconductor layer structure.

[0065] Generally, the material used in the gate bus 136 (which may be or comprise, for example, a metal) can have a lower resistivity than the material used in the gate finger 134 (which may be or comprise, for example, polysilicon or silicide). The transition from the lower resistivity of the material in the gate bus 136 to the higher resistivity of the gate finger 134 tends to increase the gate resistance of the device. Furthermore, the gate resistance of the device also increases based on the length of the transmission distance of the gate signal along the length of the gate finger 134. In some embodiments, a top metal (e.g., a gate runner) may be used to transmit the gate signal across device 100 to the gate finger, but this occupies an active area of ​​the device.

[0066] One method that can be used to reduce the gate resistance of a device is to increase the number of gate fingers using a mesh layout. Figure 1D The diagram shows Figure 1B An alternative example of the power switching device 100, which incorporates this mesh layout. For example... Figure 1D As shown, the gate electrode structure 130 may be included in a first direction (e.g., Figure 1D The first gate finger 134a extends in the X direction and in the second direction (e.g., Figure 1D A second gate finger 134b extends in the Y direction. The first gate finger 134a and the second gate finger 134b can be interconnected in a mesh layout. By using a mesh layout, the overall resistance of the gate region can be reduced, but low-resistance connectors (e.g., gate buses) are still used to help distribute current. The gate mesh can trade off lower gate connection resistance and space occupation on the device in exchange for ohmic contact with the source. Moreover, the additional gate fingers 134a, 134b can be combined with additional processing during manufacturing and can utilize a large surface area of ​​the device.

[0067] To address the shortcomings of conventional devices, the embodiments described herein provide a gate connector that allows for a simple reduction in the gate resistance of the device. The gate connector connects to multiple gate fingers and / or one or more gate buses to allow for increased conductivity of the gate electrodes. In some embodiments, portions of the gate connector may be integrated with the gate structure of one or more unit cell transistors of the device.

[0068] Figure 2A This is a schematic plan view of a power switching device 200 according to some embodiments of the present disclosure. Reference Figure 2AThe power switching device 200 includes a semiconductor layer structure comprising an active region 102 and a passive region 104. The active region 102 is the region of the device that includes operable transistors (e.g., unit cell transistors discussed herein), while the passive region 104 is the region that does not include such operable transistors. The power switching device 200 may be related to the present document's description of... Figures 1A-1D The power switching device 100 discussed has many similarities. Therefore, Figure 2A The description will focus on relative to Figures 1A-1D The differences.

[0069] like Figure 2A As shown, the gate electrode structure 230 may include a gate pad 132, a plurality of gate fingers 134, one or more gate buses 136, and one or more gate connectors 234 electrically interconnecting the gate fingers 134. The gate connectors 234 may include metals and / or metal nitrides, such as, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W), but this disclosure is not limited thereto.

[0070] like Figure 2A As shown, gate connector 234 can be coupled into power switching device 200 to turn on and / or contact one or more of gate fingers 134. In some embodiments, gate fingers 134 can be in a first direction (e.g., Figure 2A The gate connector 234 extends in the X direction (as in the first direction), and the gate connector 234 can extend in a second direction (e.g., intersecting the first direction) that intersects the first direction. Figure 2A It extends in the Y direction. Gate connector 234 can be connected to one or more gate buses 136. For example, gate connector 234 can be connected to gate bus 136 at either end of gate connector. In some embodiments, gate connector 234 can be electrically connected to gate fingers 134 that they pass over.

[0071] Although gate connector 234 is illustrated as extending from one side of power switching device 200 to the other, it will be appreciated that this embodiment is not limited thereto. In some embodiments, one or more of the gate connectors 234 may be connected to the gate bus 136 and / or the gate pad 132 only at one end of the gate connector 234. Similarly, in some embodiments, the gate connector 234 may not be connected to the gate bus 136 and / or the gate pad 132, but may instead be connected to another gate connector 234.

[0072] Furthermore, although the gate connectors 234 are illustrated as being distributed at regular intervals, this embodiment is not limited thereto. In some embodiments, the density of the gate connectors 234 may vary at different locations on the power switching device 200.

[0073] To better describe the structure of the gate connector 234, a subset of the power switching device 200 indicated by box 'A' will be described. Figure 2B yes Figure 2A A schematic enlarged perspective view of part 'A'. Figure 2C It is along Figure 2B A schematic cross-sectional view taken from line 2C-2C. Figure 2D It is along Figure 2B A schematic cross-sectional view of the line cut in 2D-2D.

[0074] refer to Figures 2B to 2D The power switching device 200 may include a plurality of unit cell transistors 205. The power switching device 200 and therefore the unit cell 205 may include an n-type wide-bandgap semiconductor substrate 210. The substrate 210 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the substrate 210 may be or include different semiconductor materials (e.g., group III nitride-based materials, Si, GaAs, ZnO, InP) or non-semiconductor materials (e.g., sapphire). The substrate 210 may be heavily doped with n-type impurities (i.e., an n+ silicon carbide substrate). Impurities may include, for example, nitrogen or phosphorus. The doping concentration of the substrate 210 may, for example, be 1 × 10⁻⁶. 18 atoms / cm 3 and 1×10 21 atoms / cm 3 Between these ranges, but other doping concentrations can also be used. In some embodiments, the substrate can be relatively thick (e.g., over 100 micrometers), but... Figures 2B-2D In (and other figures) the substrate is shown as a thin layer to allow for the amplification of other layers and areas of the device.

[0075] Lightly doped n-type (n - The silicon carbide drift region 220 can be provided on the substrate 210. The n-type silicon carbide drift region 220 can be formed, for example, by epitaxial growth on the substrate 210. The n-type silicon carbide drift region 220 can have, for example, 1×10⁻⁶. 16 Up to 5×10 17 Dopant / cm 3 The doping concentration is specified. The n-type silicon carbide drift region 220 can be a thick region with a vertical height of, for example, 3-100 micrometers above the substrate 210. In some embodiments, the upper portion of the n-type silicon carbide drift region 220 may include, in some embodiments, a more heavily doped n-type silicon carbide current diffusion layer than the lower portion of the n-type silicon carbide drift region 220. In some embodiments, a p-type shielding region (not shown) may be formed in the drift region 220.

[0076] The p-well 240 may be formed on and / or in the drift region 220. In some embodiments, the p-well 240 may have, for example, a diameter of 5 × 10⁻⁶. 16 / cm 3 and 5×10 19 / cm 3 The doping concentration between. The upper portion 242 of each p-well 240 (see...) Figure 2C It can be more heavily doped with p-type dopant. The upper portion 242 of each p-well 240 can have, for example, a dopant density of 2 × 10⁻⁶. 18 / cm 3 and 1×10 20 / cm 3 The doping concentration between them.

[0077] Heavily doped (n) + The n-type silicon carbide source / drain region 250 can be formed in the upper portion of the p-well 240. Heavily doped (n...) + The n-type silicon carbide region 250 can serve as the source region of the unit cell transistor 205. The drift region 220 and the substrate 210 together serve as the common drain region of the unit cell transistor 205.

[0078] In some embodiments, the p-well 240 (including its more heavily doped upper portion 242) and the n-type source / drain region 250 may be formed via ion implantation in the drift layer 220. In some embodiments, the p-well 240 may be formed from a layer deposited on the upper surface of the drift layer 220, into which the n-type source / drain region 250 is implanted. As known to those skilled in the art, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating the ions as an ion beam toward the surface of the semiconductor layer in the ion implantation target chamber with a predetermined kinetic energy. Based on the predetermined kinetic energy, the desired ion species can penetrate to a certain depth in the semiconductor layer. The p-well 240 (including its more heavily doped upper portion 242), the n-type source / drain region 250, the drift region 220, and the substrate 210 may form a semiconductor layer structure 255.

[0079] A trench 265 may be formed in the drift layer 220. In some embodiments, the bottom surface of the trench 265 may extend into the drift layer 220 below the bottom surface of the p-well 240 and / or the source / drain region 250. A gate insulator 270 may be formed on the sidewalls and bottom of the trench 265. The gate insulator 270 may comprise, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 may also be used. x N y Si x N yAl2O3 and / or high-k dielectrics such as hafnium oxide, etc. Gate electrode 272 may be formed in trench 265 on gate insulator 270. Gate electrode 272 may include, for example, silicide, doped polysilicon (poly-Si or poly), and / or a stable conductor. Gate insulator 270 and gate electrode 272 may be formed in trench 265 in drift layer 220 between p-well 240 and n-type source / drain region 250, and in some embodiments may extend to the surface of drift layer 220. In some embodiments, a portion of the upper surface of gate insulator 270 and a portion of the upper surface of gate electrode 272 may be coplanar with the upper surface of semiconductor layer structure 255, but the embodiments described herein are not limited thereto. It will be appreciated that gate electrode 272 may be a continuous gate electrode structure 230 including gate pad 132 and one or more gate buses 136 (see...). Figure 2A The gate of 134 is a portion of the gate electrode structure 230. In some embodiments, the gate electrode structure 230 may include, for example, a semiconductor (e.g., polysilicon) and / or a metal.

[0080] Because in Figures 2A to 2D In the gate trench implementation shown, the gate electrode 272 penetrates into the upper surface of the semiconductor layer structure 255, thus applying a bias voltage to the gate electrode 272 to form a vertical channel that extends through the portion of the p-well 240 below the n-type source / drain region 250.

[0081] A portion 247 of the p-well 240 (e.g., the more heavily doped upper portion 242 of the p-well 240) may expose a surface contact portion (not shown) to which a surface can be attached. For example, the surface contact portion may comprise a metal and may form the source contact portion of the power switching device 200. (Refer to the above...) Figures 2A-2B As described, the source contact may be part of a continuous source metal layer 123 extending across the upper surface of the silicon carbide semiconductor layer structure 255. For simplicity of the figures, Figures 2A to 2D The source metal layer (and the insulating layer electrically isolating the gate electrode 272 from the source metal layer) are not shown. The source contact may include, for example, a metal (such as nickel, titanium, tungsten, or aluminum) or an alloy, or a thin stack of these or similar materials. A drain contact 224 may be formed on the lower surface of the substrate 210. The drain contact 224 may include, for example, a material similar to the source contact, which may form an ohmic contact with the substrate 210. When a voltage is applied to the gate electrode 272, current can flow from the n-type source region 250 through the drift region 220 adjacent to and below the gate electrode 272.

[0082] Multiple gate connectors 234 may extend perpendicularly to the gate finger 134. Multiple gate connectors 234 may be separated from each other in a direction parallel to the gate finger 134. For example, as... Figure 2B and Figure 2D As shown, gate fingers 134 may extend in the X direction, and a plurality of gate connectors 234 may extend in the Y direction. The plurality of gate connectors 234 may be arranged in the X direction to periodically lie on and / or directly contact the gate fingers 134. Gate connectors 234 may extend on and / or directly contact adjacent gate electrodes in the gate electrodes 272, and a given gate electrode 272 may be connected to and / or contact more than one gate connector 234. Gate connectors 234 may include metals and / or metal nitrides, such as, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W), but this disclosure is not limited thereto. Gate connectors 234 may be formed as a single layer or multiple layers. The thickness of gate connectors 234 may be between 10 nm and 500 nm.

[0083] In some embodiments, one or more layers may separate the gate connector 234 from the top surface of the semiconductor layer structure 255. A portion of the gate connector 234 may be insulated from the underlying semiconductor layer structure 255. For example, in some embodiments, a connector insulating layer 236 may be deployed between the gate connector 234 and the top surface of the semiconductor layer structure 255. The connector insulating layer 236 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 may be used. x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc. In some embodiments, the connector insulating layer 236 may be physically connected to and / or integral with the gate insulator 270. Therefore, the gate insulator 270 and the connector insulating layer 236 may form a continuous layer, wherein a portion of the gate insulator 270 is located on the sidewalls and bottom of the trench 265, and a portion of the connector insulating layer 236 extends on the surface of the semiconductor layer structure 255. The thickness of the connector insulating layer 236 may be between 25 nm and 75 nm. In some embodiments, the thickness of the connector insulating layer 236 may be equal to or greater than the thickness of the gate insulator 270. In some embodiments, the connector insulating layer 236 may be made of the same material as the gate insulator 270 and / or may include additional dielectrics applied before or after the gate insulator 270.

[0084] In some embodiments, connector electrode layer 235 may be deployed between gate connector 234 and connector insulating layer 236. Connector electrode layer 235 may include, for example, silicide, doped polysilicon (poly-Si or poly), and / or a stable conductor. Connector electrode layer 235 may reduce the interaction between connector insulating layer 236 and gate connector 234. In some embodiments, connector electrode layer 235 may be physically connected to and / or integrated with gate electrode 272. In some embodiments, connector electrode layer 235 may be made of the same material as gate electrode 272. In some embodiments, connector electrode layer 235 may contact a portion of gate electrode 272 extending above the top surface of semiconductor layer structure 255. The thickness of connector electrode layer 235 may be between 25 nm and 800 nm. Therefore, the gate electrode 272 and the connector electrode layer 235 can form a continuous layer, wherein a portion of the gate electrode 272 is on and / or within the trench 265, while a portion of the connector electrode layer 235 extends on the surface of the semiconductor layer structure 255 and on the connector insulating layer 236.

[0085] Because of the high-temperature processing operation following gate formation, the power switching device 200 can include polysilicon or silicide as the gate electrode 272. Since silicon is chemically inert at the interface with the gate insulator 270, it can be used as part of the gate finger 134 to form a higher quality gate electrode. However, polysilicon can have a higher resistivity than other metals. For example, the conductivity of the material constituting the gate connector 234 can be higher than the conductivity of the material constituting the gate finger 134 (or conversely, the resistivity of the material constituting the gate finger 134 can be higher than the resistivity of the material constituting the gate connector 234). By incorporating an additional gate connector 234, for example, making the gate connector 234 contact the gate electrode 272, the resistance of the gate electrode structure 230 can be reduced. In trench devices, if the trench is made very narrow and shallow, the volume of the gate electrode 272 within the trench can be very small. Therefore, including a more conductive metal in the gate connector 234 is beneficial for these devices.

[0086] Although the power switching device 200 is shown as an n-type device having a source region 250 on its upper surface and a drain contact 224 on its bottom surface, it will be appreciated that in a p-type device, these positions are reversed. Therefore, in the following description (including the claims), the source contact and drain contact may generally refer to either the source contact or the drain contact.

[0087] As described above, in some embodiments, a portion of the upper surface of the gate insulator 270 and a portion of the upper surface of the gate electrode 272 may be coplanar with the upper surface of the semiconductor layer structure 255, such as... Figure 2C As shown in the figure. However, in some embodiments, the upper surface of the gate electrode 272 may extend above the upper surface of the semiconductor layer structure 255. Figure 2E From and Figure 2C A schematic cross-sectional view taken at a similar angle (e.g., along line 2C-2C) but illustrating an alternative configuration of the gate electrode 272' and the gate insulator 270'. Figure 2E As shown, in some embodiments, the gate electrode 272' and the gate insulator 270' can be formed such that at least a portion of the gate electrode 272' and / or the gate insulator 270' is at a higher level than the upper surface of the semiconductor structure 255 (e.g., further away from the substrate 210). In other aspects, Figure 2E The configuration of the devices in the middle can be basically similar to Figures 2A to 2D The device configuration shown is illustrated. It will be understood that other configurations of the gate electrode 272' and / or gate insulator 270' may be possible without departing from the present invention.

[0088] Figures 3A to 3F The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 2A to 2D A schematic cross-sectional view of a method for a power switching device 200. Figure 3A , Figure 3C and Figure 3E It is along Figure 2B The cross section cut by line 2C-2C. Figure 3B , Figure 3D and Figure 3F It is along Figure 2B A 2D-to-2D cross-sectional view of the line. For simplicity, details will be omitted. Figures 3A to 3F Zhongyu Figures 2A to 2D Descriptions of those elements that are the same or similar. Therefore, Figures 3A to 3F The description will focus on the differences from the previously described device.

[0089] refer to Figure 3A and Figure 3B A substrate 210 is provided, and a drift region 220 is formed on the substrate 210 via epitaxial growth. In some embodiments, the substrate 210 is heavily doped (n... + n-type silicon carbide and the drift region 220 is lightly doped (n - Silicon carbide drift region 220. In some embodiments, an n-type silicon carbide current diffusion layer including the upper portion of the drift layer 220 may be formed.

[0090] p-wells 240 can be formed in a portion of the active region 102 that will become the final device. In the active region 102, the upper portion 242 of each p-well 240 can be more heavily doped with p-type dopant, and the heavily doped (n...) + The n-type silicon carbide source region 250 can be formed in the upper portion of the p-well 240, directly adjacent to and in contact with the heavily doped portion 242 of the p-well 240. Heavily doped (n... + The n-type silicon carbide region 250 serves as the source region of the unit cell transistor 205. In some embodiments, ion implantation may be used to form p-wells 240, 242 and the n-type source region 250. The p-well 240 (including its more heavily doped upper portion 242), the n-type source / drain region 250, the drift region 220, and the substrate 210 may form a semiconductor layer structure 255. The semiconductor layer structure 255 may be patterned and etched to form trenches 265.

[0091] refer to Figure 3C and Figure 3D A gate insulating layer 336 can be formed on the upper surface of the semiconductor layer structure 255 and in the trench 265. In some embodiments, a first portion 336a of the gate insulating layer 336 can be formed (e.g., deposited and / or grown) on the sidewalls and bottom of the trench 265. In some embodiments, a second portion 336b of the gate insulating layer 336 can be formed (e.g., deposited and / or grown) on the semiconductor layer structure 255 between the trenches 265. In some embodiments, the first portion 336a and the second portion 336b of the gate insulating layer 336 can be physically connected to each other. The gate insulating layer 336 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 can be used. x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc. In some embodiments, the composition of the first portion 336a of the gate insulating layer 336 may differ from that of the second portion 336b. For example, the second portion 336b of the gate insulating layer 336 may include an additional dielectric layer applied before or after the material used to form the first portion 336a of the gate insulating layer 336.

[0092] Electrode layer 335 may be formed on gate insulating layer 336. Electrode layer 335 may also be formed within trench 265, and in some embodiments, trench 265 may be filled. Electrode layer 335 may include, for example, silicide, doped polysilicon (polysilicon or poly), and / or a stable conductor.

[0093] refer to Figure 3E and Figure 3FA gate connector layer 334 may be formed on the upper surfaces of the electrode layer 335 and the gate insulating layer 336. In some embodiments, the gate connector layer 334 may be deposited as a blanket layer. The gate connector layer 334 may include metals and / or metal nitrides, such as, for example, Ti, TiN, Ta, TaN, and / or W, but this disclosure is not limited thereto. The gate connector layer 334 may be formed as a single layer or multiple layers. The gate connector layer 334 may be formed in a single step or in multiple steps. The thickness of the gate connector layer 334 may, for example, be between 10 nm and 500 nm.

[0094] Return to reference Figures 2B to 2D The gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned and etched to form the gate connector 234, connector electrode layer 235, connector insulating layer 236, gate insulator 270, and gate electrode 272. For example, the gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned to leave multiple portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 extending perpendicular to the trench 265. The remaining portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 can form the gate connector 234, connector electrode layer 235, and connector insulating layer 236. The connector electrode layer 235 can be physically connected to and / or integrated with the gate electrode 272. The connector insulating layer 236 can be physically connected to and / or integrated with the gate insulator 270.

[0095] Portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 may be removed in other portions of the active region 102. For example, above the region where a source contact is to be formed, portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 on the top surface of the semiconductor layer structure 255 may be removed to expose the top surface of the semiconductor layer structure 255. Conventional processing may be performed thereto to provide source and / or drain contacts (e.g., drain contact 224). In regions of the active region 102 separated from the gate connector 234, the electrode layer 335 and gate insulating layer 336 may be removed to form a gate electrode 272 and a gate insulator 270 having an upper surface coplanar with the upper surface of the semiconductor layer structure 255, but the embodiments described herein are not limited thereto. In some embodiments, the gate electrode 272 and / or gate insulator 270 may extend above the upper surface of the semiconductor layer structure 255 (e.g., as a "T-gate" or other configuration, such as...). Figure 2E (Configuration).

[0096] Figure 4AThis is a schematic perspective view of a portion of a power switching device 200' according to some embodiments of the present disclosure. Figure 4B It is along Figure 4A A schematic cross-sectional view taken from line 4B-4B. Figure 4C It is along Figure 4A A schematic cross-sectional view taken from line 4C-4C. For simplicity, details will be omitted. Figures 4A to 4C The descriptions of those elements that are the same as or similar to those described in the previous figures. Therefore, Figures 4A to 4C The description will focus on the differences from the previously described device.

[0097] refer to Figures 4A to 4C The gate connector 234 can be separated from the top surface of the semiconductor layer structure 255 via the connector insulating layer 236. The connector electrode layer 235 may not be present between the gate connector 234 and the connector insulating layer 236, but may be present between the gate connector 234 and the gate electrode 272. In some embodiments, the gate electrode 272 may extend through the connector insulating layer 236 beneath the gate connector 234 to contact the gate connector 234. In some embodiments, the gate electrode 272 may extend above the top surface of the semiconductor layer structure 255 in the region beneath the gate connector 234. For example, residues of the deposited electrode layer 335 (see...) Figure 5B It can be retained as the upper part of the gate electrode 272.

[0098] Figures 5A to 5D The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 4A to 4C A schematic cross-sectional view of a method for a power switching device 200'. Figure 5A and Figure 5C It is along Figure 4A The cross-section of line 4B-4B (e.g., along the exposed portion 247 of p-well 242). Figure 5B and Figure 5D From and Figure 4A The cross-section taken from the same angle as line 4C-4C (e.g., along gate connector 234). For simplicity, details regarding... Figures 5A to 5D The description of those elements that are the same as or similar to those in the previously described diagram. Therefore, Figures 5A to 5D The description will focus on the differences from the previously described devices and / or methods.

[0099] form Figures 4A to 4C The initial steps of the power switching device 200' can be similar to those regarding... Figures 3A to 3D Those illustrated and described will be omitted, and repeated descriptions of them will be omitted.

[0100] refer to Figure 5A and Figure 5BThe electrode layer 335 can be removed from the upper surface of the gate insulating layer 336. For example, the electrode layer 335 can be planarized and / or patterned / etched to leave a portion of the electrode layer 335 on the trench 265. The electrode layer 335 can be planarized to leave a portion of the electrode layer 335 between the portions of the gate insulating layer 336. For example, in some embodiments, the upper surface of the electrode layer 335 can be coplanar with the upper surface of the gate insulating layer 336, but the embodiments described herein are not limited thereto. The electrode layer 335 can form the upper portion of the gate electrode 272 (see [link to documentation]). Figure 4A and Figure 4C ).

[0101] refer to Figure 5C and Figure 5D The gate connector layer 334 can be formed on the upper surfaces of the electrode layer 335 and the gate insulating layer 336. In some embodiments, the gate connector layer 334 can be deposited as a capping layer. The gate connector layer 334 may include metals and / or metal nitrides, such as, for example, Ti, TiN, Ta, TaN and / or W, but this disclosure is not limited thereto. The gate connector layer 334 can be formed as a single layer or multiple layers. The gate connector layer 334 can be formed in a single step or in multiple steps. The thickness of the gate connector layer 334 can be between 10 nm and 500 nm.

[0102] Return to reference Figures 4A to 4C The gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned and etched to form the gate connector 234, connector insulating layer 236, gate insulator 270, and gate electrode 272. For example, the gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned to leave multiple portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 extending perpendicular to the trench 265. The remaining portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 can form the gate connector layer 234 and connector insulating layer 236. The connector insulating layer 236 can be physically connected to and / or integral with the gate insulator 270. At least a portion of the gate connector 234 can be directly on the connector insulating layer 236 without the connector electrode layer 235 in between.

[0103] Portions of the gate connector layer 334, electrode layer 335, and gate insulating layer 336 may be removed in other portions of the active region 102. For example, above the region where a source contact is to be formed, the gate connector layer 334, electrode layer 335, and gate insulating layer 336 may be removed to expose the top surface of the semiconductor layer structure 255. Conventional processing may be performed thereto to provide source and / or drain contacts (e.g., drain contact 224). In the region of the active region 102 separated from the gate connector 234, the electrode layer 335 and gate insulating layer 336 may be removed to form a gate electrode 272 and a gate insulator 270 having an upper surface coplanar with the upper surface of the semiconductor layer structure 255, but the embodiments described herein are not limited thereto. In some embodiments, the gate electrode 272 and / or gate insulator 270 may extend above the upper surface of the semiconductor layer structure 255 (e.g., as a "T-gate" or other configuration, such as...). Figure 2E (Configuration).

[0104] Figure 6A This is a schematic plan view of a power switching device 600 according to some embodiments of the present disclosure. Reference Figure 6A The power switching device 600 includes a semiconductor layer structure comprising an active region 102 and a passive region 104. The power switching device 600 can be related to the present document's description of... Figures 2A-2D The power switching devices 200 discussed have many similarities. Therefore, Figures 6A-6D The description will focus on relative to Figures 2A-2D The differences.

[0105] like Figure 6A As shown, the gate electrode 630 may include a gate pad 132, a plurality of gate fingers 134, one or more gate buses 136, and one or more gate connectors 634A, 634B electrically interconnecting the gate fingers 134. The gate connector 634B may be in a second direction (e.g., Figure 6A Deployed on the surface of the power switching device 600 in the Y direction to be on and / or in contact with one or more of the gate fingers 134, such as Figures 2A-2D As in the middle. Furthermore, the gate connector 634A can be in the first direction (e.g., Figure 6A Extending in the X direction, and in some embodiments, may cover the surface of the gate finger 134. Gate connectors 634A and 634B may be collectively referred to herein as gate connectors 634. Thus, a plurality of gate connectors 634 may be included in the first direction (e.g., Figure 6A The first portion 634A of the gate connector extends in the X direction and in the second direction (e.g., in the X direction) intersecting the first direction. Figure 6AThe second part 634B of the gate connector extends in the Y direction.

[0106] Gate connector 634 may be connected to one or more gate buses 136. For example, gate connector 634 may be connected to gate bus 136 at either end. In some embodiments, gate connector 634 may be electrically connected to gate fingers 134 that pass through it.

[0107] To better describe the structure of the gate connector 634, a subset of the power switching device 600 indicated by box 'B' will be described. Figure 6B yes Figure 6A A schematic enlarged perspective view of part 'B'. Figure 6C It is along Figure 6B A schematic cross-sectional view taken from line 6C-6C. Figure 6D It is along Figure 6B A schematic cross-sectional view taken from line 6D-6D.

[0108] refer to Figures 6B to 6D Power switching equipment 600 and, for example Figures 2A-2D The difference may be that the gate connector 634 can extend along the gate finger 134 and between adjacent gate fingers 134. For example, the gate finger 134 may include a gate electrode 272 and a gate insulator 270. The gate connector 634 may include metals and / or metal nitrides, such as, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W), but this disclosure is not limited thereto. The gate connector 634 may be formed as a single layer or multiple layers. The thickness of the gate connector 634 may be between 10 nm and 500 nm. The gate connector 634 may include a first portion 634A extending in a first direction (e.g., the X direction) and a second portion 634B extending in a second direction (e.g., the Y direction). The first portion 634A and the second portion 634B of the gate connector 634 may be electrically connected to each other.

[0109] A first portion 634A of the gate connector 634 may extend above and parallel to the gate finger 134. In some embodiments, the first portion 634A of the gate connector 634 may directly contact the gate electrode 272. The gate electrode 272 may, for example, include silicide, doped polysilicon (polysilicon or poly), and / or a stable conductor.

[0110] In some embodiments, a portion of the connector insulating layer 636 may be located between the first portion 634A of the gate connector 634 and the top surface of the semiconductor layer structure 255. The connector insulating layer 636 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 may be used.x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc. In some embodiments, the connector insulating layer 636 may be physically connected to and / or integral with the gate insulator 270. Therefore, the gate insulator 270 and the connector insulating layer 636 may form a continuous layer.

[0111] The second portion 634B of the gate connector 634 may extend above and perpendicular to the gate finger 134. The second portion 634B of the gate connector 634 may extend over an adjacent gate electrode 272 and, in some embodiments, directly contact the adjacent gate electrode 272, and may be electrically coupled to and integral with the first portion 634A of the gate connector 634. The second portion 634B of the gate connector 634 may be similar to the portion 634B of the gate connector 634. Figures 2A-2D The gate connector 234 is oriented as shown. Therefore, the second portion 634B of the gate connector 634 can be separated from the semiconductor layer structure 255 via the connector insulating layer 636, where the connector electrode layer 635 is located. The connector electrode layer 635 may include, for example, silicide, doped polysilicon (poly-Si or poly), and / or a stable conductor. In some embodiments, the connector electrode layer 635 may be physically connected to and / or integrated with the gate electrode 272. For example, in some embodiments, the connector electrode layer 635 may form the upper surface of the gate electrode 272. In some embodiments, the connector electrode layer 635 may be made of the same material as the gate electrode 272.

[0112] The first portion 634A and the second portion 634B of the gate connector 634 may intersect each other. For example, the first portion 634A and the second portion 634B of the gate connector 634 may intersect over a plurality of gate fingers 134. At the intersection of the first portion 634A and the second portion 634B of the gate connector 634, the first portion 634A and the second portion 634B of the gate connector 634 may directly contact and / or be electrically connected to the gate electrode 272.

[0113] The addition of the first portion 634A of the gate connector 634 allows for additional conductivity enhancement to the gate finger 134. By covering the gate electrode 272 with the first portion 634A of the gate connector 634 and connecting the adjacent gate finger 134 to the second portion 634B of the gate connector 634, the overall resistance of the gate finger 134 can be reduced due to the increased conductivity of the gate connector 634.

[0114] manufacture Figures 6A to 6DThe steps for power switching device 600 can be similar to those regarding... Figures 3A to 3F The steps illustrated and described begin. However, after depositing the gate connector layer 334, electrode layer 335, and gate insulating layer 336 (see, for example...), Figure 3E and Figure 3F Subsequently, the gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned / etched to form a gate connector 634 including a first portion 634A and a second portion 634B. As a result of the patterning / etching, the portions of the electrode layer 335 and the gate insulating layer 336 deployed between the first portion 634A and the second portion 634B can be retained as the connector electrode layer 635 and the connector insulating layer 636.

[0115] Although Figures 6A to 6D An embodiment of a power switching device 600 in which the gate connector 634 includes both a first portion 634A and a second portion 634B is illustrated, but it will be understood that the embodiments described herein are not limited thereto. Figure 6E This is a schematic perspective view of an additional configuration of a power switching device 600' according to some embodiments of the present disclosure. In the power switching device 600', only the first portion 634A of the gate connector 634 is present. That is, the second portion 634B extending between adjacent gate fingers 134 is omitted.

[0116] Similar to the power switching device 600, the first portion 634A of the gate connector 634 may extend above and parallel to the gate finger 134. In some embodiments, the first portion 634A of the gate connector 634 may directly contact the gate electrode 272.

[0117] Although it does not have a second part 634B to interconnect adjacent gate fingers 134, the power switching device 600' can still be improved compared to conventional devices because the gate connector 634 can increase the conductivity of the gate fingers 134, thereby increasing the gate resistance of the device.

[0118] manufacture Figure 6E The steps of the power switching device 600' can be similar to those of the power switching device 600. However, after depositing the gate connector layer 334, electrode layer 335 and gate insulating layer 336 (see, for example...), Figure 3E and Figure 3F The gate connector layer 334, electrode layer 335, and gate insulating layer 336 can be patterned / etched to form a gate connector 634 comprising only the first portion 634A. As a result of the patterning / etching, portions of the electrode layer 335 and the gate insulating layer 336 deployed between the first portion 634A and the semiconductor layer structure 255 can be integrated with the gate electrode 272 and the gate insulator 270.

[0119] Figure 7A This is a schematic perspective view of a portion of a power switching device 700 according to some embodiments of the present disclosure. Figure 7B It is along Figure 7A A schematic cross-sectional view taken from line 7B-7B. Figure 7C It is along Figure 7A A schematic cross-sectional view taken from line 7C-7C. For simplicity, details will be omitted. Figures 7A to 7C The description of those elements that are the same as or similar to those described in the previous figures. Therefore, Figures 7A to 7C The description will focus on the differences from the previously described device.

[0120] refer to Figures 7A to 7C Power switchgear 700 and related Figures 6A to 6D The power switching device 600 shown differs in that an additional third portion 634C of the gate connector 634 contacts and / or is within the gate electrode 272. The third portion 634C of the gate connector 634 may be formed within the gate electrode 272 on the top surface of the semiconductor layer structure 255 and below the top surface of the gate electrode 272. A portion of the gate electrode 272 may be on the sidewall of the third portion 634C of the gate connector 634. In some embodiments, the bottom surface of the third portion 634C of the gate connector 634 may extend below the bottom surface of the source / drain region 250. The first portion 634A, the second portion 634B, and the third portion 634C of the gate connector 634 may be integrally connected. Therefore, the gate connector 634 may extend on the surface of the gate electrode 272 of the gate finger 134, below the upper surface of the gate electrode 172, and between adjacent gate fingers 134. By using a gate connector comprising a material (e.g., a metal) having a higher conductivity than the material of the gate electrode 272 (e.g., polysilicon), the gate resistance of the power switching device 700 can be reduced and the device performance can be improved.

[0121] Figure 7DThis is a schematic perspective view of an additional configuration of a power switch 700' according to some embodiments of the present disclosure. The power switch 700' is similar to the power switch 600', except that a third portion 634C of the gate connector 634 is added. In other words, the power switch 700' may omit the second portion 634B of the gate connector 634 connecting to the adjacent gate finger 134. As with the power switch 700, a first portion 634A of the gate connector 634 may extend above and parallel to the gate finger 134. The first portion 634A of the gate connector 634 may be integrally connected to the third portion 634C of the gate connector 634. The third portion 634C of the gate connector 634 may extend below the upper surface of the gate electrode 172. In some embodiments, the first portion 634A of the gate connector 634 may directly contact the gate electrode 272.

[0122] Figures 8A to 8D The illustration shows the manufacture according to some embodiments of the present disclosure. Figures 7A to 7C A schematic cross-sectional view of a method for a power switching device 700. Figure 8A and Figure 8C It is along Figure 7A A cross-section taken along line 7B-7B (e.g., along the exposed portion 247 of p-well 242). Figure 8B and Figure 8D It is along Figure 7A The cross-section taken from line 7C-7C (e.g., along gate connector 634). For simplicity, details will be omitted. Figures 8A to 8D The description of those elements that are the same as or similar to those in the previously described diagram. Therefore, Figures 8A to 8D The description will focus on the differences from the previously described devices and / or methods.

[0123] form Figures 7A to 7C The initial steps of the power switching device 700 can be similar to those regarding... Figure 3A and Figure 3B Those illustrated and described will be omitted, and repeated descriptions of them will be omitted.

[0124] refer to Figure 8A and Figure 8B A gate insulating layer 336 can be formed on the upper surface of the semiconductor layer structure 255 and in the trench 265. In some embodiments, the gate insulating layer 336 can be formed (e.g., deposited and / or grown) on the sidewalls and bottom of the trench. The gate insulating layer 336 may include, for example, a silicon (SiO2) layer, but other insulating materials such as SiO2 can be used. x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc.

[0125] Electrode layer 835 can be formed on gate insulating layer 336. Electrode layer 835 can also be formed within trench 265, such that electrode layer 835 can be formed on the sidewalls and bottom surface of trench 265. Electrode layer 835 and Figure 3C and Figure 3D The difference with electrode layer 335 is that electrode layer 835 may not completely fill trench 265. Therefore, voids may exist between the sidewalls of trench 265 where electrode layer 835 is not present. For example, electrode layer 835 can be formed by conformal or near-conformal deposition of the electrode layer material. Electrode layer 835 may include, for example, silicides, doped polysilicon (poly-Si or poly) and / or stable conductors.

[0126] refer to Figure 8C and Figure 8D A gate connector layer 834 may be formed on the upper surfaces of the electrode layer 835 and the gate insulating layer 336. In some embodiments, the gate connector layer 834 may be deposited as a capping layer. The gate connector layer 834 may include metals and / or metal nitrides, such as, for example, Ti, TiN, Ta, TaN, and / or W, but this disclosure is not limited thereto. The gate connector layer 834 may be formed as a single layer or multiple layers. The gate connector layer 834 may be formed in a single step or in multiple steps. The thickness of the portion of the gate connector layer 834 located on the semiconductor layer structure 255 may be between 10 nm and 500 nm. The gate connector layer 834 may also be formed within a trench 265. For example, the gate connector layer 834 may be located within the trench 265 between the sidewalls of the trench 265 and / or fill the remaining space in the trench 265. A portion of the gate connector layer 834 may extend below the upper surface of the semiconductor layer structure 255.

[0127] Return to reference Figures 7A to 7CThe gate connector layer 834, electrode layer 835, and gate insulating layer 336 can be patterned and etched to form the gate connector 634, connector electrode layer 635, connector insulating layer 636, gate insulator 270, and gate electrode 272. For example, the gate connector layer 834, electrode layer 835, and gate insulating layer 336 can be patterned to leave multiple portions of the gate connector layer 834, electrode layer 835, and gate insulating layer 336 extending perpendicularly to and parallel to trench 265. The remaining portions of the gate connector layer 834, electrode layer 835, and gate insulating layer 336 can form a first portion 634A, a second portion 634B, and a third portion 634C of the gate connector 634, the connector electrode layer 635, and the connector insulating layer 636. The connector electrode layer 635 can be physically connected to and / or integrated with the gate electrode 272. The connector insulating layer 636 can be physically connected to and / or integrated with the gate insulator 270. The first portion 634A, the second portion 634B, and the third portion 634C of the gate connector 634 can be physically connected to each other and / or integrated with each other, such that the gate connector 634 extends below the top surface of the semiconductor layer structure 255 and contacts the gate electrode 272.

[0128] Return to reference Figure 7D The manufacturing steps of power switch device 700' differ from those of power switch device 700 in that the gate connector layer 834, electrode layer 835, and gate insulating layer 336 can be patterned to leave multiple portions of the gate connector layer 834, electrode layer 835, and gate insulating layer 336 extending parallel to trench 265. The remaining portions of the gate connector layer 834, electrode layer 835, and gate insulating layer 336 can form the first portion 634A and the third portion 634C of the gate connector 634, the connector electrode layer 635, and the connector insulating layer 636.

[0129] Although Figures 6A to 8D The examples focus on an example where the gate connector 634 has a first portion 634A and a second portion 634B, and a connector electrode layer 635 is present between the second portion 634B and the connector insulating layer 636; however, it will be understood that this embodiment is not limited thereto. For example, those skilled in the art will recognize that, regarding... Figures 4A to 5D The modification of removing the connector electrode layer 235 between the gate connector 234 and the connector insulating layer 236 in the illustrated and described power device 200' can be equivalently applied to the following after necessary modifications: Figures 6A to 8D The described embodiments.

[0130] While the previous examples focused primarily on using gate connectors for trench devices, the embodiments described herein are not limited thereto. Figure 9AThis is a schematic perspective view of a portion of a power switching device 900 according to some embodiments of the present disclosure. Figure 9B It is along Figure 9A A schematic cross-sectional view taken from line 9B-9B. Figure 9C It is along Figure 9A A schematic cross-sectional view taken from line 9C-9C. For simplicity, details will be omitted. Figures 9A to 9C The descriptions of those elements that are the same as or similar to those described in the previous figures. Therefore, Figures 9A to 9C The description will focus on the differences from the previously described device.

[0131] The power switching device 900 differs from previous power switching devices primarily in its planar gate structure. For example, the gate finger 134 can be formed as a portion of the gate electrode 972 formed on the gate insulator 970. The gate finger 134 can be arranged in the active region of the device and in a manner similar to... Figure 2A It extends in parallel as shown.

[0132] Gate finger 134 can be formed on semiconductor layer structure 955. As previously described, semiconductor layer structure 955 may include n-type wide bandgap semiconductor substrate 210 and lightly doped n-type (n... - Silicon carbide drift region 220. In some embodiments, the upper portion of the n-type silicon carbide drift region 220 may include an n-type silicon carbide current diffusion layer, which is more heavily doped than the lower portion of the n-type silicon carbide drift region 220.

[0133] The upper portion of the n-type silicon carbide drift region 220 can be p-type doped by ion implantation to form a p-well 940. The upper portion 942 of each p-well 940 can be more heavily doped with p-type dopant. Heavily doped (n... + The n-type silicon carbide source region 950 can be formed in the upper portion of the p-well 940 that is directly adjacent to and in contact with the more heavily doped portion 942 of the p-well 940. The drain contact portion 224 can be formed on the lower surface of the substrate 210. When a voltage is applied to the gate electrode 972, current can flow from the n-type source region 950 through the drift region 220 below the gate electrode 972.

[0134] Gate electrode 972 may be formed on gate insulator 970 to form gate finger 134. Gate electrode 972 may include, for example, silicide, doped polysilicon (poly-Si or poly) and / or a stable conductor. Figure 9AAs shown, gate connector 934 can be deployed on the surface of power switching device 900 to be located on and / or contact one or more of gate fingers 134. Gate connector 934 can extend perpendicular to gate fingers 134 and can be separated from each other in a direction parallel to gate fingers 134. For example, as Figures 9A to 9C As shown, gate fingers 134 may extend in the X direction and a plurality of gate connectors 934 may extend in the Y direction. The plurality of gate connectors 934 may be arranged in the X direction to periodically lie on and / or contact gate fingers 134. Gate connectors 934 may extend on adjacent gate electrodes 972, and a given gate electrode 972 may be connected to and / or directly contact more than one gate connector 934. Gate connectors 934 may comprise metals and / or metal nitrides, such as, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W), but this disclosure is not limited thereto. Gate connectors 934 may be formed as a single layer or multiple layers. The thickness of gate connectors 934 may be between 10 nm and 500 nm.

[0135] In some embodiments, one or more layers can separate the gate connector 934 from the top surface of the semiconductor layer structure 955. For example, in some embodiments, a connector insulating layer 936 may be deployed between the gate connector 934 and the top surface of the semiconductor layer structure 955. The connector insulating layer 936 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 may be used. x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc. In some embodiments, the connector insulating layer 936 may be physically connected to and / or integrated with the gate insulator 970. Thus, the gate insulator 970 and the connector insulating layer 936 may form a continuous layer, wherein portions of the gate insulator 970 and portions of the connector insulating layer 936 extend on the surface of the semiconductor layer structure 955.

[0136] In some embodiments, a connector electrode layer 935 may be deployed between a gate connector 934 and a connector insulating layer 936. The connector electrode layer 935 may include, for example, silicides, doped polysilicon (poly-Si or poly), and / or stable conductors. In some embodiments, the connector electrode layer 935 may be physically connected to and / or integrated with the gate electrode 972. In some embodiments, the connector electrode layer 935 may include portions of the gate electrode 972 extending above the top surface of the semiconductor layer structure 255 between adjacent gate fingers 134.

[0137] Similar to the aforementioned devices, the use of gate connector 934 allows for higher conductivity of the material of gate connector 934, thereby reducing the overall gate resistance of power switching device 900. It will be understood that variations of the power switching devices previously described herein can be similarly applied to power switching device 900. For example, those having features such as Figures 6A to 6D The gate connectors of the first and second intersecting portions can also be used in planar switching devices.

[0138] Figure 10A This is a schematic perspective view of a portion of a power switching device 1000 according to some embodiments of the present disclosure. Figure 10B It is along Figure 10A A schematic cross-sectional view taken from line 10B-10B. Figure 10C It is along Figure 10A A schematic cross-sectional view taken from line 10C-10C. For simplicity, details will be omitted. Figures 10A to 10C The descriptions of those elements that are the same as or similar to those described in the previous figures. Therefore, Figures 10A to 10C The description will focus on the differences from the previously described device.

[0139] refer to Figures 10A to 10C Gate connector 934 can be deployed on the surface of power switching device 1000 to contact one or more of gate fingers 134, such as Figures 9A-9C As in the example. Furthermore, the gate connector 934 may extend on the surface of the gate finger 134, and in some embodiments cover the surface of the gate finger 134. Therefore, a plurality of gate connectors may include the gate connector 934 in a first direction (e.g., Figure 9A The first portion 934A extending in the X direction and the gate connector 934 in the second direction (e.g., intersecting the first direction) are in the X direction. Figure 9A The second part 934B extends in the Y direction.

[0140] Gate connector 934 may include gate electrode 972 and gate insulator 970. Gate connector 934 may include metal and / or metal nitride, such as, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W), but this disclosure is not limited thereto. Gate connector 934 may be formed as a single layer or multiple layers. The thickness of gate connector 934 may be between 10 nm and 500 nm.

[0141] Power switching device 1000 and, for example Figures 9A-9CThe difference lies in that the gate connector 934 can extend along the gate finger 134 and between adjacent gate fingers 134. The gate connector 934 may include a first portion 934A extending in a first direction (e.g., the X direction) and a second portion 934B extending in a second direction (e.g., the Y direction). The first portion 934A and the second portion 934B of the gate connector 934 can be electrically connected to each other.

[0142] A first portion 934A of the gate connector 934 may extend above and parallel to the gate finger 134. The first portion 934A of the gate connector 934 may be separated from the gate electrode 972 by a connector electrode layer 935. The connector electrode layer 935 may include, for example, silicide, doped polysilicon (poly-Si or poly), and / or a stable conductor. In some embodiments, the connector electrode layer 935 may be physically connected to and / or integral with the gate electrode 972. In some embodiments, the connector electrode layer 935 may be a portion of the gate electrode 972 extending between adjacent gate fingers 134.

[0143] In some embodiments, a portion of the connector insulating layer 936 may be located between the connector electrode layer 935 and the top surface of the semiconductor layer structure 955. The connector insulating layer 936 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiO2 may be used. x N y Si x N y Al2O3 and / or high-k dielectrics (such as hafnium oxide), etc. In some embodiments, the connector insulating layer 936 may be physically connected to and / or integrated with the gate insulator 970. Therefore, the gate insulator 970 and the connector insulating layer 936 may form a continuous layer.

[0144] The second portion 934B of the gate connector 934 may extend above and perpendicular to the gate finger 134. The second portion 934B of the gate connector 934 may extend on an adjacent gate electrode 972 and may be electrically coupled to and integral with the first portion 934A of the gate connector 934. Figures 9A to 9C The gate connector 934 shown is similarly oriented. Therefore, the second portion 934B of the gate connector 934 can be separated from the semiconductor layer structure 955 via the connector insulating layer 936, in which the connector electrode layer 935 is located.

[0145] The first portion 934A and the second portion 934B of the gate connector 934 may intersect each other. For example, the first portion 934A and the second portion 934B of the gate connector 934 may intersect above and / or directly contact the respective gate fingers 134.

[0146] Although Figures 10A to 10C An embodiment of a power switching device 1000 in which the gate connector 934 includes both a first portion 934A and a second portion 934B is illustrated, but it will be understood that the embodiments described herein are not limited thereto. Figure 10D This is a schematic perspective view of an additional configuration of a power switching device 1000' according to some embodiments of the present disclosure. In the power switching device 1000', only the first portion 934A of the gate connector 934 is present. That is, the second portion 934B extending between adjacent gate fingers 134 is omitted.

[0147] Similar to the power switching device 1000, the first portion 934A of the gate connector 934 may extend above and parallel to the gate finger 134. In some embodiments, the first portion 934A of the gate connector 934 may directly contact the gate electrode 972.

[0148] Although it does not have a second part 934B to interconnect adjacent gate fingers 134, the power switching device 1000' can still be improved compared to conventional devices because the gate connector 934 can improve the conductivity of the gate fingers 134, thereby improving the gate resistance of the device.

[0149] Although not explicitly shown, those skilled in the art will recognize that Figures 9A to 10D The device can be manufactured similarly to those previously described. That is, the insulating layer, electrode layer, and connector layer can be deposited on the surface of the semiconductor layer structure 255. The connector layer can be patterned / etched together with the insulating layer and electrode layer to form... Figures 9A to 10D The equipment.

[0150] The power switching devices according to the embodiments disclosed herein can provide significantly improved performance. The use of gate connectors as described herein can increase the conductivity of the device and allow for reduced gate resistance. Reduced gate resistance can improve, for example, the switching performance of the device.

[0151] It will be appreciated that the specific layer structures, doping concentrations, materials, conductivity types, etc., shown in the figures and / or described herein are provided merely as examples to illustrate the structures of specific exemplary embodiments. Therefore, the specific details discussed below are not limited to the present invention.

[0152] While the preceding figures illustrate the structure of a unit cell of an n-channel MOSFET, it will be appreciated that, according to further embodiments of the invention, the polarity of each semiconductor layer in each device can be reversed to provide a corresponding p-channel MOSFET.

[0153] In this document, embodiments of the invention are described with respect to cross-sectional views showing one or two unit cells of a power switching device. It will be appreciated that practical implementations will typically include a much larger number of unit cells. However, it will also be appreciated that the invention is not limited to such devices, and the appended claims also cover MOSFETs and other power switching devices comprising, for example, a single unit cell. Furthermore, while this disclosure focuses on silicon carbide devices, it will be appreciated that embodiments of the invention are also applicable to devices formed using other wide-bandgap semiconductors, such as, for example, gallium nitride, zinc selenide, or any other II-VI or III-V wide-bandgap compound semiconductors.

[0154] The invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. It will be understood that when an element or layer is referred to as “on another element or layer,” “connected to another element or layer,” or “coupled to another element or layer,” it may be directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as “directly on another element or layer,” “directly connected to another element or layer,” or “directly coupled to another element or layer,” there are no intermediate elements or layers present. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The same reference numerals always refer to the same element.

[0155] It will be understood that while the terms "first" and "second" are used herein to describe various regions, layers, and / or elements, these regions, layers, and / or elements should not be limited by these terms. These terms are used only to distinguish one region, layer, or element from another. Therefore, the first region, layer, or element discussed below may be referred to as the second region, layer, or element, and similarly, the second region, layer, or element may be referred to as the first region, layer, or element without departing from the scope of the invention.

[0156] Relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that relative terms are intended to cover different orientations of the device other than those depicted in the figures. For example, if the device in the figure is flipped, then the element described as being “below” the other element will be oriented “above” the other element. Thus, the exemplary term “lower” can include both “down” and “up” orientations depending on the specific orientation of the figure. Similarly, if one of the devices in the figures is flipped, then the element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can include both “up” and “down” orientations.

[0157] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used herein, the terms “comprising,” “including,” “containing,” and / or “including” specify the presence of the stated feature, element, and / or component, but do not exclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0158] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic diagrams. Accordingly, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, shape deviations caused by manufacturing processes. For instance, an injection region illustrated as rectangular will typically have rounded or curved features at its edges and / or an injection concentration gradient, rather than a binary change from an injection region to a non-injection region. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0159] It will be understood that the embodiments disclosed herein can be combined. Therefore, features depicted and / or described with respect to the first embodiment can also be included in the second embodiment, and vice versa.

[0160] While the embodiments described above have been referenced to specific accompanying drawings, it should be understood that some embodiments of the invention may include additional and / or intermediate layers, structures, or elements, and / or certain layers, structures, or elements may be omitted. Although several exemplary embodiments of the invention have been described, those skilled in the art will readily recognize that many modifications can be made to the exemplary embodiments without materially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the following claims, including equivalents of the claims.

Claims

1. A semiconductor device, comprising: Semiconductor layer structure; A plurality of unit cell transistors are electrically connected in parallel, each unit cell transistor including a gate finger having a longitudinal axis extending in a first direction below the upper surface of the semiconductor layer structure, the gate fingers being spaced apart from each other in a second direction; as well as A gate connector having a longitudinal axis extending in the second direction, wherein the gate connector is connected to the gate fingers of the plurality of unit cell transistors, and the gate connector extends in the active region of the semiconductor device over the portion of the semiconductor layer structure located between the gate fingers.

2. The semiconductor device according to claim 1, wherein, The gate connector includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

3. The semiconductor device according to claim 1, wherein, The thickness of the gate connector is between 10 nm and 500 nm.

4. The semiconductor device according to any one of claims 1-3, wherein, The gate connector is the first part of the gate connector, and The gate connector further includes a second portion that extends in the first direction to contact the upper surface of the gate finger of one of the plurality of unit cell transistors.

5. The semiconductor device according to claim 1, wherein, The gate connector further includes a third portion that extends in the first direction below the upper surface of the semiconductor layer structure.

6. The semiconductor device according to any one of claims 1-3, wherein, The lower surface of the gate connector contacts the surface of the gate finger.

7. The semiconductor device according to any one of claims 1-3, further comprising a connector insulating layer between the gate connector and the semiconductor layer structure.

8. The semiconductor device according to claim 7, wherein, The connector insulating layer extends in the second direction between adjacent gate fingers on the upper surface of the semiconductor layer structure.

9. The semiconductor device according to any one of claims 1-3, wherein, The gate connector is physically connected to the corresponding gate finger among the gate fingers.

10. A semiconductor device, comprising: Semiconductor layer structure; Gate pads on the semiconductor layer structure; as well as A gate electrode structure on the semiconductor layer structure and electrically coupled to the gate pad, wherein the gate electrode structure includes: A plurality of gate fingers, each gate finger comprising a first material extending in a first direction on the semiconductor layer structure, wherein the plurality of gate fingers are spaced apart in a second direction, and A gate connector, the gate connector comprising a second material extending over and connected to the plurality of gate fingers. The gate connector includes a first portion extending in the first direction over the plurality of gate fingers, a second portion extending in the second direction over the portion of the semiconductor layer structure located between the gate fingers in the active region of the semiconductor device, and a third portion extending in the first direction below the upper surface of the semiconductor layer structure.

11. The semiconductor device according to claim 10, wherein, The first conductivity of the first material of the gate is lower than the second conductivity of the second material of the gate connector.

12. The semiconductor device according to claim 10, wherein, The first material includes polycrystalline silicon or silicide.

13. The semiconductor device according to any one of claims 10-12, wherein, The second material includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

14. The semiconductor device according to claim 10, wherein, The respective gate electrodes of the plurality of gate fingers extend below the upper surface of the semiconductor layer structure.

15. The semiconductor device of claim 10, further comprising a connector insulating layer extending between adjacent gate fingers of the plurality of gate fingers. in, The connector insulating layer is located between the gate connector and the semiconductor layer structure.

16. The semiconductor device of claim 15, further comprising a connector electrode layer between the connector insulating layer and the gate connector.

17. A semiconductor device, comprising: Semiconductor layer structure; The first gate electrode and the second gate electrode on the semiconductor layer structure; as well as Gate connector, the gate connector comprising a first part and a second part, Wherein, the first portion extends on and connects to the first gate electrode, extends on and connects to the second gate electrode, and extends in the active region of the semiconductor device on the portion of the semiconductor layer structure located between the first gate electrode and the second gate electrode. The second part intersects with the first part and contacts the upper surface of the first gate electrode.

18. The semiconductor device of claim 17, further comprising a connector insulating layer between the gate connector and the semiconductor layer structure.

19. The semiconductor device according to claim 18, wherein, The connector insulating layer extends between the first gate electrode and the second gate electrode.

20. The semiconductor device according to any one of claims 17-19, wherein, The first gate electrode and the second gate electrode comprise a first material, and the gate connector comprises a second material different from the first material.

21. The semiconductor device according to claim 20, wherein, The first conductivity of the first material of the first gate electrode and the second gate electrode is lower than the second conductivity of the second material of the gate connector.

22. The semiconductor device according to claim 20, wherein, The first material includes polycrystalline silicon or silicide.

23. The semiconductor device according to claim 20, wherein, The second material includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and / or tungsten (W).

24. The semiconductor device according to any one of claims 17-19, wherein, The gate connector comprises multiple layers.

25. The semiconductor device according to claim 17, wherein, The gate connector further includes a third portion that contacts the first gate electrode below the upper surface of the semiconductor layer structure.

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