Convolution data cache and real-time release method, device, equipment and medium

Abstract

The present application discloses a method, device, equipment and medium for caching convolution data and its real-time release, which belongs to the field of artificial intelligence. The method includes: when receiving a target convolution operation instruction, determining the width of the corresponding convolution matrix and the preset strip operation length, wherein the convolution matrix includes multiple basic blocks; determining a caching method based on the strip operation length and the width; based on the caching method, caching the data of the basic block to a preset cache space, and releasing it in real time based on the caching method. In the present application, the caching method to be adopted is determined based on the size relationship between the strip operation length and the width of the convolution matrix, wherein the caching method is related to the convolution operation law. The caching scheme selected according to the situation adapts to the corresponding situation, so that the data that is no longer reused in the same intermediate convolution operation can be released in batches in a timely manner without waiting for the data to be reused, thereby improving the cache space utilization rate of the convolution operation.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence, and in particular to a method, apparatus, device, and medium for caching convolution data and its real-time release. Background Art

[0002] At present, when performing a convolution operation on convolution data, the convolution data must first be read out from the storage space and then cached in the cache space. After some of the cache data in the cache space participates in the convolution operation, if it does not need to be reused, the cache data in the cache space will be released, and the cache space occupied by the cache data will be released, and the remaining available cache space will increase. However, when the current convolution data cache and its real-time release unit perform a convolution operation on the convolution data, some of the cache data in the cache space will not need to be reused after participating in the intermediate convolution operation, and some will be reused multiple times. The cache data that needs to be reused multiple times and the cache data that does not need to be reused generally cannot be released from the cache space at the same time, and the cache data that does not need to be reused cannot be released in time. Therefore, the existing technology has the problem of low cache space utilization when performing convolution operations.

[0003] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of the present invention is to provide a convolution data cache and real-time release method thereof, aiming to solve the problem in the prior art that the cache space utilization rate is low when performing convolution operations.

[0005] To achieve the above objectives, the present application provides a method for caching convolution data and its real-time release, which is applied to a device for caching convolution data and its real-time release, and the method includes:

[0006] Upon receiving a target convolution operation instruction, determining a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks;

[0007] determining a cache mode based on the bar operation length and the width;

[0008] Based on the cache mode, the data of the basic block is cached in a preset cache space, and is released in real time based on the cache mode.

[0009] In a possible implementation manner of the present application, the caching mode is a first caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0010] If the length of the operation bar is less than the width, determining the cache occupied area of the linked list to be built;

[0011] If it is determined based on the cache occupied area that a linked list does not need to be established, then based on the target convolution operation instruction, a convolution scan order and specifications of a configured multiplication-addition matrix are determined;

[0012] Based on the specification, the convolution matrix is channel grouped to obtain multiple channel groups;

[0013] Determining a mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the plurality of channel groups;

[0014] Reading the data of the basic block according to the mapping order, and caching the data of the basic block into the cache space according to the mapping order;

[0015] In the mapping order, the data of the basic blocks that have completed the intermediate calculation and do not need to be reused are released from the cache space.

[0016] In a possible implementation manner of the present application, after the step of determining the cache occupied area of the to-be-built linked list if the stripe operation length is smaller than the width, the following steps are included:

[0017] If it is determined based on the cache occupied area that a linked list needs to be established, then a linked list is established for the basic blocks corresponding to the stripe operation length;

[0018] When it is determined that the basic block has completed the intermediate operation and does not need to be reused, the basic block data is released from the cache space in real time based on the linked list.

[0019] In a possible implementation of the present application, the step of determining the mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple groups of channel groups includes:

[0020] Determining a mapping order of the basic blocks in a first channel group based on the convolution scan order, wherein a mapping end point in the first channel group is determined based on the stripe operation length;

[0021] Determining a first mapping order of the basic blocks per channel group based on the channel grouping order, wherein the mapping order in the second and subsequent channel groups is consistent with the mapping order in the first channel group;

[0022] Grouping the convolution matrix into stripes based on the strip operation length, and determining a stripe-by-strip second mapping order of the basic blocks based on an order of the strip grouping;

[0023] A mapping order of the basic blocks is determined based on the first mapping order and the second mapping order.

[0024] In a possible implementation manner of the present application, the caching mode is a second caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0025] If the stripe operation length is an integer multiple of the width, reading data of multiple rows and all channel basic blocks in the convolution matrix in a row-by-row order, and buffering the data in the buffer space, wherein the integer multiple is a first integer and the number of rows is equal to the first integer;

[0026] When it is determined that the data has completed intermediate operations and does not need to be reused, the data of the basic block is released from the cache space, wherein the data of all channel basic blocks of the first integer row are released.

[0027] In a possible implementation manner of the present application, the caching mode is a third caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0028] If the stripe operation length is greater than the width, and the stripe operation length includes a second integer multiple of the width and a remainder, reading data of a plurality of rows and all channel basic blocks in the convolution matrix in a row-by-row order, and buffering the data in the buffer space, wherein the number of rows is one greater than the second integer;

[0029] When it is determined that the data has completed intermediate calculations and does not need to be reused, releasing the data of the basic block from the cache space, wherein the data of all channel basic blocks of the second integer row are released;

[0030] When the basic block data is read out next time and cached in the cache space, the basic block data corresponding to the remainder is merged with the data that completes the intermediate operation next time and does not need to be reused, and released from the cache space together.

[0031] In a possible implementation of the present application, when it is determined that the data has completed intermediate calculations and does not need to be reused, releasing the data of the basic block from the cache space, wherein after the step of releasing the data of all channel basic blocks of the second integer row, the method further includes:

[0032] Creating a linked list for basic block data corresponding to the remainder;

[0033] When it is determined that the basic block data corresponding to the remainder has completed the intermediate calculation and does not need to be reused, the basic block data corresponding to the remainder is released from the cache space based on the linked list.

[0034] In addition, to achieve the above-mentioned purpose, the present application also provides a convolution data cache and real-time release device, which includes:

[0035] A first determining module is configured to determine, upon receiving a target convolution operation instruction, a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks;

[0036] a second determining module, configured to determine a cache mode based on the stripe operation length and the width;

[0037] The cache and release module is used to cache the data of the basic block to a preset cache space based on the cache method, and release the data in real time based on the cache method.

[0038] In addition, to achieve the above-mentioned purpose, the present application also provides a convolution data cache and real-time release device, which is a physical node device, and the convolution data cache and real-time release device includes: a memory, a processor, and a convolution data cache and real-time release program stored on the memory and runnable on the processor, and the processor executes the convolution data cache and real-time release program to implement the steps of the convolution data cache and real-time release method.

[0039] In addition, to achieve the above-mentioned purpose, the present application also provides a medium, on which is stored a program for implementing a method for caching convolution data and its real-time release. When the program for caching convolution data and its real-time release is executed by a processor, the steps of the above-mentioned method for caching convolution data and its real-time release are implemented.

[0040] The present application provides a method, apparatus, device, and medium for caching and real-time release of convolution data. Compared to the prior art, which suffers from low cache space utilization during convolution operations, the present application determines the width of a corresponding convolution matrix and a preset stripe length upon receiving a target convolution operation instruction, wherein the convolution matrix comprises multiple basic blocks; determines a caching method based on the stripe length and the width; and caches the data of the basic blocks in a preset cache space based on the caching method and releases the data in real time based on the caching method. The present application determines the caching method based on the relationship between the stripe length of the convolution operation and the width of the convolution matrix, wherein the caching method is related to the convolution operation rules. The caching scheme selected based on the situation adapts to the specific situation, allowing cached data that participates in the same intermediate convolution operation and does not need to be reused to be released from the cache space in a centralized and timely manner without waiting for the cached data to be reused. This accelerates cache release without affecting subsequent intermediate convolution operations and improves cache space utilization during convolution operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a flow chart of a first embodiment of a method for caching and real-time releasing convolution data of the present application;

[0042] Figure 2 This is a basic structural diagram of the artificial intelligence chip in the first embodiment of the convolution data caching and real-time release method of this application;

[0043] Figure 3 This is a flow chart of the convolution processing algorithm in the artificial intelligence chip in the first embodiment of the method for caching and real-time releasing convolution data of this application;

[0044] Figure 4 This is a schematic diagram of the convolution matrix in the first embodiment of the method for caching convolution data and releasing it in real time;

[0045] Figure 5 This is a schematic diagram of the convolution weight matrix sliding in the first embodiment of the method for caching and real-time releasing convolution data of this application;

[0046] Figure 6 This is a schematic diagram of data release in the first embodiment of the convolution data cache and real-time release method of the present application;

[0047] Figure 7 This is a schematic diagram of data release in the first embodiment of the convolution data cache and real-time release method of the present application;

[0048] Figure 8 This is a schematic diagram of the convolution matrix in the first embodiment of the method for caching convolution data and releasing it in real time;

[0049] Figure 9 Schematic diagram of a convolution data caching and real-time release device in a third embodiment of the convolution data caching and real-time release method of the present application;

[0050] Figure 10 This is a schematic diagram of the device structure of the hardware operating environment involved in the fourth embodiment of the convolution data caching and real-time release method of this application. DETAILED DESCRIPTION

[0051] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0052] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0053] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are used solely to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if," as used herein, may be interpreted as "upon," "when," or "in response to a determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising" and "including" indicate the presence of the recited features, steps, operations, elements, components, items, types, and / or groups, but do not preclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or," "and / or," "including at least one of the following," etc., as used herein, may be interpreted as inclusive, meaning any one or any combination. For example, “comprising at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”; and for another example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.

[0054] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0055] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0056] It should be noted that in this article, step codes such as S10 and S20 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the scope of protection of this application.

[0057] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0058] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0059] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0060] Example 1

[0061] The embodiment of the present application provides a convolution data cache and a real-time release method thereof. In the first embodiment of the convolution data cache and a real-time release method thereof, referring to Figure 1 , applied to a convolution data cache and real-time release device, the method comprising:

[0062] Step S10, upon receiving a target convolution operation instruction, determining a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks;

[0063] Step S20, determining a cache mode based on the stripe operation length and the width;

[0064] Step S30: caching the data of the basic block into a preset cache space based on the cache mode, and releasing the data in real time based on the cache mode.

[0065] As an example, the convolution operation system includes a cache of convolution data and its real-time release unit, storage space, a multiplication and addition matrix of convolution operations, an activation unit, a pooling unit and a fully connected unit.

[0066] As an example, the storage space may be a memory.

[0067] In this embodiment, the activation unit is used to fine-tune the feature matrix to prevent the gradient of the feature matrix from disappearing.

[0068] In this embodiment, the role of the pooling unit is to reduce the dimension of the feature matrix to compress the features. When the dimension of the feature matrix is high, the computational difficulty increases sharply. By reducing the dimension of the feature matrix through the pooling unit, the required computing power can be reduced.

[0069] In this embodiment, the function of the fully connected unit is to convert all feature matrices of the pooling unit into a one-dimensional feature vector.

[0070] As an example, the convolution data includes a convolution matrix. The convolution matrix can be two-dimensional or three-dimensional. In this embodiment, the convolution matrix is a three-dimensional stereo matrix. The convolution matrix has multiple layers of channels, and the specific number of layers is not limited.

[0071] As an example, the method for caching convolution data and its real-time release can be applied to a device for caching convolution data and its real-time release, which is a subordinate convolution operation system and is integrated into an artificial intelligence chip.

[0072] As an example, Figure 2, which is the basic structure diagram of the artificial intelligence chip, which is configured with convolution data cache unit, convolution parallel computing multiplication and addition array, activation, pooling, shaping and other units, as well as memory interface and DDR SDRAM.

[0073] As an example, Figure 3 , which is a flow chart of the convolution processing algorithm in the artificial intelligence chip, including 1 convolution data cache unit write mapping, 2 convolution data cache unit, 3 convolution data cache unit read control, 4 convolution parallel operation multiplication and addition array, 5 accumulation of partial results, and 6 convolution data cache unit status management.

[0074] In this embodiment, the application scenarios are:

[0075] When the AI chip receives a target convolution operation instruction, it determines the convolution matrix and convolution weight matrix involved in the convolution operation from the target convolution operation instruction. As an example, the convolution matrix and the convolution weight matrix are three-dimensional, the convolution matrix has multiple layers of channels, the convolution weight matrix also has multiple layers of channels, and the number of channels of the convolution weight matrix is the same as the number of channels of the convolution matrix. After the AI chip determines the convolution matrix and the convolution weight matrix involved in the convolution operation from the target convolution operation instruction, it reads the data in all channels of the convolution matrix and the data in all channels of the convolution weight matrix from the storage space and then caches them in the cache space. After caching the data in all channels, the convolution operation begins. The convolution matrix is divided into multiple parts, and the convolution weight matrix is also divided into multiple parts. Each convolution matrix part performs an intermediate convolution operation with the corresponding convolution weight matrix part, wherein each layer of channels in the convolution matrix part corresponds to each layer of channels in the convolution weight matrix part, and the convolution operation is performed on the convolution data and the convolution weight data on the same channel. Based on this, the convolution operation is performed on each layer of channels until the data of the last layer of channels participates in the convolution operation, and the intermediate convolution result is obtained. The intermediate convolution result is then saved as part of the data of the final convolution result for operations such as activation or pooling. When the convolution operation is performed on the convolution matrix, the intermediate convolution results after the convolution operation is performed on the data in all channels are saved. Since the amount of data in the convolution matrix is large when the number of channels is large, the data in all channels of the convolution matrix needs to be cached before the convolution operation, which places higher requirements on the cache space size. Moreover, the data in all channels can only be released after the operation is completed. The data in all channels occupies the cache space for a long time, and the utilization rate of the cache space is not high.

[0076] This embodiment aims to improve the utilization of cache space when performing convolution operations.

[0077] In this embodiment, the convolution matrix contains multiple basic blocks, each of which has corresponding data. Furthermore, based on the characteristic of convolution operations that split the convolution matrix, the convolution matrix is striped, where each strip is composed of multiple basic blocks. The number of strips corresponds to the number of basic blocks, i.e., the strip length.

[0078] As an example, Figure 4 This is a schematic diagram of the convolution matrix. The convolution matrix is three-dimensional, with three dimensions: height, width, and channel.

[0079] The specific steps are as follows:

[0080] Step S10, upon receiving a target convolution operation instruction, determining a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks;

[0081] As an example, when a target convolution operation instruction is received, the convolution matrix and the convolution weight matrix participating in the target convolution operation are determined, and the width of the convolution matrix and the strip operation length of the target convolution operation are determined, wherein the convolution matrix includes multiple basic blocks.

[0082] Step S20, determining a cache mode based on the stripe operation length and the width;

[0083] If the stripe operation length is smaller than the width, the cache mode is determined to be the first cache mode.

[0084] If the stripe operation length is an integral multiple of the width, the cache mode is determined to be the second cache mode.

[0085] If the stripe operation length is greater than the width, and the stripe operation length includes a second integer multiple of the width and a remainder, the cache mode is determined to be the third cache mode.

[0086] As an example, the stripe operation length is 16, the width of the convolution matrix is 8, and the stripe operation length is twice the width, that is, an integer multiple, and the cache mode is determined to be the second cache mode.

[0087] Step S30: caching the data of the basic block into a preset cache space based on the cache mode, and releasing the data in real time based on the cache mode.

[0088] As an example, the caching mode is the first caching mode. Step S30, based on the caching mode, caches the data of the basic block to a preset cache space, and releases the data in real time based on the caching mode, includes steps A1 to A6:

[0089] Step A1: if the length of the bar operation is smaller than the width, determining the cache area occupied by the linked list to be built;

[0090] As an example, the strip operation length is 16, the convolution matrix width is 256, the strip operation length is not an integer multiple of the convolution matrix width, and the strip operation length is less than the width, then the second cache method is used to first determine the cache area occupied by the linked list to be built.

[0091] Step A1, if the length of the bar operation is smaller than the width, after the step of determining the cache occupied area of the linked list to be built, includes steps a1 to a2:

[0092] Step a1: if it is determined based on the cache occupied area that a linked list needs to be established, then a linked list is established for the basic blocks corresponding to the stripe operation length;

[0093] Step a2: When it is determined that the basic block has completed the intermediate operation and does not need to be reused, the basic block data is released from the cache space in real time based on the linked list.

[0094] As an example, if it is determined that a linked list needs to be established based on the cache occupied area, a linked list is established for the basic block corresponding to the strip operation length. When it is determined that the basic block has completed the intermediate operation and does not need to be reused, the basic block data is released from the cache space in real time based on the linked list.

[0095] Step A2: If it is determined based on the cache occupied area that a linked list does not need to be established, then based on the target convolution operation instruction, a convolution scan order and a specification of a configured multiplication-addition matrix are determined;

[0096] As an example, whether it is not necessary to establish a linked list is determined based on the cache occupied area. If the cache occupied area is smaller than the area occupied when establishing the linked list, it indicates that the area consumed by establishing the linked list is large, then there is no need to establish a linked list. Otherwise, a linked list needs to be established.

[0097] As an example, if it is determined based on the cache occupied area that there is no need to establish a linked list, then based on the target convolution operation instruction, the convolution scan order and the specifications of the configured multiplication-addition matrix are determined.

[0098] As an example, the convolution scanning order is the order in which the convolution weight matrix slides on the convolution matrix. The convolution weight matrix is scanned while sliding. Figure 5 This is a schematic diagram of the convolution weight matrix sliding on the convolution matrix. The convolution weight matrix is 16*5*5, so the scanning window is 5*5.

[0099] In this embodiment, the multiply-add matrix is a matrix configured for convolution operations. As an example, the AI chip can be configured with more than one multiply-add matrix size, including 8*8 and 32*64. According to the convolution calculation method, multiplication and addition calculations are performed on the input convolution matrix and the convolution weight matrix. Based on the data from the convolution matrix in the multiply-add matrix and the convolution weights from the convolution weight matrix in the multiply-add matrix, corresponding parallel multiplication and addition calculations are performed to obtain the convolution result.

[0100] If the strip operation length is not an integer multiple of the width, and the strip operation length is smaller than the width, the convolution scan order is determined based on the target convolution operation instruction, and the size of the multiplication-addition matrix is 8*8.

[0101] Step A3: performing channel grouping on the convolution matrix based on the specification to obtain multiple channel groups;

[0102] As an example, when a target convolution operation instruction is received, the convolution matrix is channel-grouped based on the number of columns of the multiplication-addition matrix to obtain multiple channel groups whose number of channels is equal to the number of columns.

[0103] As an example, the AI chip is configured with multiply-add matrices for both small-scale convolution operations and large-scale convolution operations. The 8x8 multiply-add matrix for small-scale convolution operations has 8 rows and 8 columns, while the 32x64 multiply-add matrix for large-scale convolution operations has 32 rows and 64 columns.

[0104] As an example, if the artificial intelligence chip is configured for an 8*8 multiplication-addition matrix for a preset small-scale convolution operation, upon receiving the target convolution operation instruction, the convolution matrix is grouped into channels based on the number of columns of the multiplication-addition matrix, which is 8, to obtain multiple channel groups with 8 channels each on average. As an example, the channels of the convolution matrix are divided into 15 groups, namely the first channel group to the fifteenth channel group, and the channel grouping order is the first channel group to the fifteenth channel group, and each channel group contains 8 channels.

[0105] Step A4: determining a mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple channel groups;

[0106] In this embodiment, the mapping order is the order in which data is read from the storage space and the order in which the read data is cached in the preset cache space.

[0107] Wherein, step A4, the step of determining the mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple channel groups, includes steps b1 to b4:

[0108] Step b1, determining a mapping order of the basic blocks in a first channel group based on the convolution scan order, wherein a mapping end point in the first channel group is determined based on the stripe operation length;

[0109] As an example, the convolution scan order of the convolution matrix is from left to right (by width) and from top to bottom (by height). Based on the convolution scan order, the mapping order of the basic blocks in the first channel group is determined first by width and then by height. The stripe operation length determines the mapping end point in the first channel group. If the stripe operation length is 16, the 16th basic block is the mapping end point in the first channel group.

[0110] Step b2, determining a first mapping order of the basic blocks per channel group based on the channel grouping order, wherein the mapping order in the second and subsequent channel groups is consistent with the mapping order in the first channel group;

[0111] As an example, the order from the first channel group to the last channel group is used as the first mapping order of the basic block by channel group, wherein the mapping order in the second channel group and subsequent channel groups is consistent with the mapping order in the first channel group.

[0112] Step b3, grouping the convolution matrix into strips based on the strip operation length, and determining a second mapping order of the basic blocks strip by strip based on the order of the strip grouping;

[0113] As an example, based on a preset stripe operation length, the convolution matrix is strip-grouped, and the grouping order obtained by the stripe grouping is consistent with the order of performing the intermediate convolution operation. The order of determining the stripe grouping is the second mapping order of the basic block one by one.

[0114] Step b4: Determine the mapping order of the basic blocks based on the first mapping order and the second mapping order.

[0115] As an example, the mapping order of the basic blocks in the convolution matrix is determined based on the first mapping order and the second mapping order.

[0116] Step A5: reading out the data of the basic block according to the mapping order, and caching the data of the basic block into the cache space according to the mapping order;

[0117] As an example, the artificial intelligence chip reads the data of the basic block from the preset storage space according to the mapping order, and caches the read data into the cache space in the mapping order.

[0118] Step A6: releasing the data of the basic blocks that have completed the intermediate calculation and do not need to be reused from the cache space in the mapping order.

[0119] As an example, when determining the basic blocks in the convolution matrix that participate in the intermediate convolution operation and completing the intermediate convolution operation, it is determined whether the basic blocks need to be reused. If it is determined that reuse is not necessary, the data of the basic blocks in the convolution matrix that have completed the operation and do not need to be reused are released.

[0120] As an example, Figure 6 The convolution data has four channels, channels 0 through 3. Channels 1-16, 23-38, 45-60, and 67-82 in the figure represent the data of the 88 basic blocks cached in the first pass. Channels 17-110, 39-132, 61-154, and 83-176 in the figure represent the data of the 88 basic blocks cached in the second pass. The stripe operation length is 16, and the width of the convolution matrix is 22, which is smaller than the width of the convolution matrix. The basic blocks released during the first release are the data of all channels for 64 basic blocks: 1-16, 23-38, 45-60, and 67-82. The basic blocks released during the second release are the data of all channels for 64 basic blocks: 17-110, 39-132, 61-154, and 83-176.

[0121] In this embodiment, not all basic blocks in the convolution matrix participate in the intermediate convolution operation at the same time, but are operated in the order of convolution scanning. Therefore, the data in the basic blocks that participate in the intermediate convolution operation first are released first, and the data in the basic blocks that participate in the intermediate convolution operation later are released later. Some basic blocks need to participate in the second intermediate convolution operation or even more intermediate convolution operations after participating in the first intermediate convolution operation. That is, some basic blocks need to be reused.

[0122] In this embodiment, basic block data is read from storage and cached in cache space in a mapping order related to convolution operations. This mapping order takes into account the convolution scan order, channel grouping order, and the order of intermediate convolution operations. When centralized caching is performed based on this mapping order, cached data that participated in the same intermediate convolution operation and does not need to be reused can be released from the cache space in batches and in a timely manner, without waiting for the cached data to be reused.

[0123] As an example, the caching mode is the second caching mode. Step S30, based on the caching mode, caches the data of the basic block to a preset cache space, and releases the data in real time based on the caching mode, includes steps B1 and B2:

[0124] Step B1: if the stripe operation length is an integer multiple of the width, then read out data of multiple rows and all channel basic blocks in the convolution matrix in a row-by-row order, and cache the data in the cache space, wherein the integer multiple is a first integer and the number of rows is equal to the first integer;

[0125] Step B2: When it is determined that the data has completed intermediate operations and does not need to be reused, the data of the basic block is released from the cache space, wherein the data of all channel basic blocks of the first integer row is released.

[0126] As an example, if the stripe operation length is twice the width, that is, an integer multiple, and the first integer is 2, then Figure 4 The convolution matrix in the convolution matrix is read out from the preset storage space in a row-by-row order, and the data of multiple rows and all channel basic blocks in the convolution matrix are cached in the preset cache space. Since the strip operation is performed in batches during convolution splitting, when reading the basic block data from the storage space, 2 rows of basic block data are read out.

[0127] As an example, when the basic block data of the same batch cached in the cache space completes the intermediate calculation and does not need to be reused, this part of the data can be released from the cache space, so as not to occupy excess cache space and enhance timeliness. Among them, the basic block data of all channels of 2 rows are released.

[0128] As an example, Figure 7 , the convolution data has 4 channels, namely channel0 to channel3. 1-88 in the figure represents the data of 88 basic blocks cached for the first time, and 101-188 in the figure represents the data of 88 basic blocks cached for the second time. The stripe operation length is 22, and the width of the convolution matrix is 22. Then the stripe operation length is an integer multiple of the width, and the data of all channel basic blocks in the entire row are released at one time. For example, the data of 88 basic blocks 1-88 are released at one time, wherein the basic blocks 1-88 include 4 channels, that is, the data of all channels are released at one time. The next time, the data of 88 basic blocks 101-188 are directly released at one time, wherein the basic blocks 101-188 include 4 channels, and the data of all channels are also released at one time.

[0129] As an example, the cache mode is the third cache mode. Step S30, based on the cache mode, caches the data of the basic block to a preset cache space, and releases the data in real time based on the cache mode, includes steps C1 to C3:

[0130] As an example, the stripe operation length is 10 and the width is 8. The stripe operation length is not an integer multiple of the width, and the stripe operation length is longer than the width. Based on the preset third cache method, the data of the basic block is cached to the cache space.

[0131] Step C1: if the stripe operation length is greater than the width, and the stripe operation length includes a second integer multiple of the width and a remainder, then reading out data of multiple rows and all channel basic blocks in the convolution matrix in a row-by-row order, and buffering the data into the buffer space, wherein the number of rows is one greater than the second integer;

[0132] As an example, Figure 8 , the convolution matrix includes height, width and channels, and 1-10 in the figure represent 10 basic blocks. When the strip operation length is 10 and the width is 8, the strip operation length is 1 times the width plus 2, then the second integer is 1 and the remainder is 2. Since the data is read in units of the strip operation length, the number of rows read is 1 greater than the second integer, that is, during the current intermediate convolution operation, not only the current data is read, but also the data of the next intermediate convolution operation is read. In a row-by-row order, the data of multiple rows and all channel basic blocks in the convolution matrix are read out, and the data is cached in the cache space, wherein the number of multiple rows is 1 greater than the second integer.

[0133] Step C2: when it is determined that the data has completed the intermediate calculation and does not need to be reused, releasing the data of the basic block from the cache space, wherein the data of all channel basic blocks in the second integer row are released;

[0134] As an example, when the data involved in the next intermediate convolution operation completes the operation and does not need to be reused, it is released from the cache space in a timely manner. Since the release is in units of rows, and some of the data to be released is less than one row, this part of the data that is less than one row does not participate in the current release and will wait to be released together with the next intermediate convolution operation data.

[0135] As an example, when it is determined that the data has completed intermediate operations and does not need to be reused, the data of the basic block is released from the cache space, wherein the data of all channel basic blocks of the second integer row are released.

[0136] Step C3: When the basic block data is read out next time and cached in the cache space, the basic block data corresponding to the remainder is merged with the data that completes the intermediate operation next time and does not need to be reused, and released from the cache space together.

[0137] As an example, after the current intermediate convolution operation is completed, the next intermediate convolution operation is performed. During the next intermediate convolution operation, the basic block data continues to be read and cached in the cache space.

[0138] As an example, when the basic block data is read out next time and cached in the cache space, the basic block data corresponding to the remainder 2 is merged with the data that completes the intermediate operation next time and does not need to be reused, and released from the cache space at one time.

[0139] The present application provides a method, apparatus, device and medium for caching convolution data and its real-time release. Compared with the prior art, when a target convolution operation instruction is received, the width of the corresponding convolution matrix and the preset stripe operation length are determined, wherein the convolution matrix includes multiple basic blocks; based on the stripe operation length and the width, a caching method is determined; based on the caching method, the data of the basic block is cached to a preset cache space and released in real time based on the caching method. In the present application, the caching method is determined based on the size relationship between the stripe operation length of the convolution operation and the width of the convolution matrix, wherein the caching method is related to the convolution operation rules. The caching scheme selected according to the situation adapts to the corresponding situation, so that the cached data that participates in the same intermediate convolution operation and does not need to be reused can be released in batches from the cache space in a centralized and timely manner without waiting for the cached data to be reused. This speeds up the cache release speed without affecting the subsequent intermediate convolution operation, and improves the utilization rate of the cache space when performing the convolution operation.

[0140] Example 2

[0141] Furthermore, based on the first embodiment of the present application, another embodiment of the present application is provided. In this embodiment, in step C2, when it is determined that the data has completed the intermediate operation and does not need to be reused, the data of the basic block is released from the cache space. After the step of releasing the data of all channel basic blocks of the second integer row, steps D1 and D2 are included:

[0142] Step D1, establishing a linked list for the basic block data corresponding to the remainder;

[0143] Step D2: When it is determined that the basic block data corresponding to the remainder has completed the intermediate calculation and does not need to be reused, the basic block data corresponding to the remainder is released from the cache space based on the linked list.

[0144] As an example, after releasing all the channel basic block data in the second integer row, some data remains unreleased (basic block data corresponding to the remainder). This data must wait until the next intermediate convolution operation before it can be released from the cache space. After releasing all the channel basic block data in the second integer row, a linked list is created for the basic block data corresponding to the remainder. The linked list records the cache location information of the basic block data corresponding to the remainder. When it is determined that the basic block data corresponding to the remainder has completed the current intermediate operation, it is determined whether it needs to be reused. If reuse is not required, the corresponding block data is released from the cache space based on the linked list.

[0145] In this embodiment, by introducing a linked list, the basic block data corresponding to the remainder is released from the cache space in a timely manner. Since this part of the data does not need to be reused after participating in the current intermediate operation, it can theoretically be released from the cache space. The linked list can achieve timely release. This part of the data does not need to wait until the next intermediate operation is completed before being released, which improves the timeliness of cache release and the utilization rate of the cache space when performing convolution operations.

[0146] Example 3

[0147] Furthermore, based on all the above embodiments, another embodiment of the present application is provided. In this embodiment, as Figure 9 , provides a convolution data cache and real-time release device, the device comprising:

[0148] A first determining module is configured to determine, upon receiving a target convolution operation instruction, a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks;

[0149] a second determining module, configured to determine a cache mode based on the stripe operation length and the width;

[0150] The cache and release module is used to cache the data of the basic block to a preset cache space based on the cache method, and release the data in real time based on the cache method.

[0151] In a possible implementation manner of the present application, the caching mode is a first caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0152] a third determining module, configured to determine a cache area occupied by the to-be-built linked list if the length of the stripe operation is smaller than the width;

[0153] a fourth determining module, configured to determine a convolution scan order and a specification of a configured multiplication-addition matrix based on the target convolution operation instruction if it is determined based on the cache occupied area that a linked list does not need to be established;

[0154] A grouping module, configured to group the channels of the convolution matrix based on the specification to obtain a plurality of channel groups;

[0155] a fifth determining module, configured to determine a mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple channel groups;

[0156] A first cache module is configured to read out the data of the basic block according to the mapping order, and cache the data of the basic block into the cache space in the mapping order;

[0157] The first releasing module is configured to release the data of the basic blocks that have completed the intermediate calculation and do not need to be reused from the cache space in the mapping order.

[0158] In a possible implementation manner of the present application, after the step of determining the cache occupied area of the to-be-built linked list if the stripe operation length is smaller than the width, the apparatus includes:

[0159] A first linked list building module is configured to build a linked list for the basic blocks corresponding to the stripe operation length if it is determined that a linked list needs to be built based on the cache occupied area;

[0160] The second releasing module is configured to release the basic block data from the cache space in real time based on the linked list when it is determined that the basic block has completed intermediate operations and does not need to be reused.

[0161] In a possible implementation of the present application, the step of determining the mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple groups of channel groups, the apparatus includes:

[0162] a sixth determining module, configured to determine a mapping order of the basic blocks in a first channel group based on the convolution scan order, wherein a mapping end point in the first channel group is determined based on the stripe operation length;

[0163] a seventh determining module, configured to determine a first mapping order of the basic blocks per channel group based on the channel grouping order, wherein the mapping order in the second and subsequent channel groups is consistent with the mapping order in the first channel group;

[0164] an eighth determining module, configured to perform strip grouping on the convolution matrix based on the strip operation length, and determine a stripe-by-strip second mapping order of the basic blocks based on an order of the strip grouping;

[0165] A ninth determining module is configured to determine a mapping order of the basic blocks based on the first mapping order and the second mapping order.

[0166] In a possible implementation manner of the present application, the caching mode is a second caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0167] a second cache module, configured to read out data of multiple rows and all channel basic blocks in the convolution matrix in a row-by-row order and cache the data into the cache space if the stripe operation length is an integer multiple of the width, wherein the integer multiple is a first integer and the number of the multiple rows is equal to the first integer;

[0168] The third releasing module is configured to release the data of the basic block from the cache space when it is determined that the data has completed intermediate calculations and does not need to be reused, wherein the data of all channel basic blocks of the first integer row are released.

[0169] In a possible implementation manner of the present application, the caching mode is a third caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes:

[0170] a third cache module, configured to read out data of a plurality of rows and all channel basic blocks in the convolution matrix in a row-by-row order and cache the data into the cache space if the stripe operation length is greater than the width and the stripe operation length includes a second integer multiple of the width and a remainder, wherein the number of rows is one greater than the second integer;

[0171] a fourth releasing module, configured to release the data of the basic block from the cache space when it is determined that the data has completed intermediate calculations and does not need to be reused, wherein the data of all channel basic blocks of the second integer row are released;

[0172] The fifth releasing module is used to release the basic block data corresponding to the remainder and the data that completes the intermediate operation next time and does not need to be reused from the cache space together when the basic block data is read out next time and cached in the cache space.

[0173] In a possible implementation of the present application, when it is determined that the data has completed intermediate calculations and does not need to be reused, the data of the basic block is released from the cache space. After the step of releasing the data of all channel basic blocks of the second integer row, the apparatus includes:

[0174] A second linked list building module is used to build a linked list for the basic block data corresponding to the remainder;

[0175] A sixth releasing module is configured to release the basic block data corresponding to the remainder from the cache space based on the linked list when it is determined that the basic block data corresponding to the remainder has completed intermediate calculations and does not need to be reused.

[0176] The specific implementation of the convolution data caching and real-time release device of the present application is basically the same as the above-mentioned convolution data caching and real-time release method embodiments, and will not be repeated here.

[0177] Example 4

[0178] Furthermore, based on all the above embodiments, another embodiment of the present application is provided. In this embodiment, a caching device for convolution data and its real-time release device is provided. The caching device for convolution data and its real-time release device is a physical node device. The caching device for convolution data and its real-time release device includes: a memory, a processor, and a program stored on the memory for implementing the caching method for convolution data and its real-time release method. The memory is used to store the program for implementing the caching method for convolution data and its real-time release method; the processor is used to execute the program for implementing the caching method for convolution data and its real-time release method, so as to implement the steps of the caching method for convolution data and its real-time release method in the above embodiments.

[0179] Reference Figure 10 , Figure 10 It is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present application.

[0180] like Figure 10 As shown, the convolution data cache and its real-time release device may include: a processor 1001, such as a CPU, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to implement communication between the processor 1001 and the memory 1005. The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk storage. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0181] In a possible implementation of the present application, the cache of the convolution data and the real-time release device thereof may also include a network interface, an audio circuit, a display, a connecting line, a sensor, an input module, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface, a Bluetooth interface), and the input module may optionally include a keyboard, a system soft keyboard, voice input, wireless receiving input, etc.

[0182] Those skilled in the art will understand that the cache of convolution data and its real-time release device structure do not constitute a limitation on the cache of convolution data and its real-time release device, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0183] The memory, as a computer medium, may include an operating system, an information exchange module, and a convolution data cache and real-time release program. The operating system is a program that manages and controls the convolution data cache and its real-time release device hardware and software resources, supporting the convolution data cache and its real-time release program, as well as the operation of other software and / or programs. The information exchange module is used to enable communication between the various components within the memory, as well as communication with other hardware and software in the management system.

[0184] In the convolution data caching and real-time release device, the processor is used to execute the convolution data caching and real-time release program stored in the memory to implement the above-mentioned convolution data caching and real-time release steps.

[0185] The specific implementation of the convolution data caching and real-time release device of the present application is basically the same as the above-mentioned convolution data caching and real-time release method embodiments, and will not be repeated here.

[0186] Example 5

[0187] An embodiment of the present application provides a medium, and the medium stores one or more programs, and the one or more programs can also be executed by one or more processors to implement the steps of the caching of convolution data and its real-time release method in the above-mentioned embodiment.

[0188] The specific implementation of the medium of the present application is basically the same as the above-mentioned embodiments of the convolution data caching and real-time release method, and will not be repeated here.

[0189] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0190] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0191] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM or RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0192] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A convolution data cache and real-time release method, characterized in that: The convolution data cache and real-time release method include: Upon receiving a target convolution operation instruction, determining a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks; determining a cache mode based on the bar operation length and the width; Based on the cache mode, cache the data of the basic block to a preset cache space, and release it in real time based on the cache mode; The caching mode is a first caching mode, and the step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes: If the length of the operation bar is less than the width, determining the cache occupied area of the linked list to be built; If it is determined based on the cache occupied area that a linked list does not need to be established, then based on the target convolution operation instruction, a convolution scan order and specifications of a configured multiplication-addition matrix are determined; Based on the specification, the convolution matrix is channel grouped to obtain multiple channel groups; Determining a mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the plurality of channel groups; Reading the data of the basic block according to the mapping order, and caching the data of the basic block into the cache space according to the mapping order; In the mapping order, the data of the basic blocks that have completed the intermediate calculation and do not need to be reused are released from the cache space.

2. The method for caching convolution data and releasing it in real time according to claim 1, characterized in that: After the step of determining the cache occupied area of the linked list to be built if the stripe operation length is smaller than the width, the method further includes: If it is determined based on the cache occupied area that a linked list needs to be established, then a linked list is established for the basic blocks corresponding to the stripe operation length; When it is determined that the basic block has completed the intermediate operation and does not need to be reused, the basic block data is released from the cache space in real time based on the linked list.

3. The method for caching convolution data and releasing it in real time according to claim 1, characterized in that: The step of determining the mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the multiple groups of channel groups comprises: Determining a mapping order of the basic blocks in a first channel group based on the convolution scan order, wherein a mapping end point in the first channel group is determined based on the stripe operation length; Determining a first mapping order of the basic blocks per channel group based on the channel grouping order, wherein the mapping order in the second and subsequent channel groups is consistent with the mapping order in the first channel group; Grouping the convolution matrix into stripes based on the strip operation length, and determining a stripe-by-strip second mapping order of the basic blocks based on an order of the strip grouping; A mapping order of the basic blocks is determined based on the first mapping order and the second mapping order.

4. The method for caching convolution data and releasing it in real time according to claim 1, wherein: The caching mode is a second caching mode. The step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes: If the stripe operation length is an integer multiple of the width, reading data of multiple rows and all channel basic blocks in the convolution matrix in a row-by-row order, and buffering the data in the buffer space, wherein the integer multiple is a first integer and the number of rows is equal to the first integer; When it is determined that the data has completed intermediate operations and does not need to be reused, the data of the basic block is released from the cache space, wherein the data of all channel basic blocks of the first integer row are released.

5. The method for caching convolution data and releasing it in real time according to claim 1, characterized in that: The caching mode is a third caching mode. The step of caching the data of the basic block to a preset cache space based on the caching mode and releasing the data in real time based on the caching mode includes: If the stripe operation length is greater than the width, and the stripe operation length includes a second integer multiple of the width and a remainder, reading data of a plurality of rows and all channel basic blocks in the convolution matrix in a row-by-row order, and buffering the data in the buffer space, wherein the number of rows is one greater than the second integer; When it is determined that the data has completed the intermediate calculation and does not need to be reused, releasing the data of the basic block from the cache space, wherein the data of all channel basic blocks of the second integer row are released; When the basic block data is read out next time and cached in the cache space, the basic block data corresponding to the remainder is merged with the data that completes the intermediate operation next time and does not need to be reused, and released from the cache space together.

6. The method for caching convolution data and releasing it in real time according to claim 5, characterized in that: When it is determined that the data has completed the intermediate calculation and does not need to be reused, the data of the basic block is released from the cache space, wherein after the step of releasing the data of all channel basic blocks of the second integer row, the method includes: Create a linked list for the basic block data corresponding to the remainder; When it is determined that the basic block data corresponding to the remainder has completed the intermediate calculation and does not need to be reused, the basic block data corresponding to the remainder is released from the cache space based on the linked list.

7. A convolution data cache and real-time release device, characterized in that: Convolution data cache and real-time release device, including: A first determining module is configured to determine, upon receiving a target convolution operation instruction, a width of a corresponding convolution matrix and a preset stripe operation length, wherein the convolution matrix includes a plurality of basic blocks; a second determining module, configured to determine a cache mode based on the stripe operation length and the width; a cache and release module, configured to cache the data of the basic block to a preset cache space based on the cache method, and release the data in real time based on the cache method; The cache mode is the first cache mode, and the cache and release module is used to implement: If the length of the operation bar is less than the width, determining the cache occupied area of the linked list to be built; If it is determined based on the cache occupied area that a linked list does not need to be established, then based on the target convolution operation instruction, a convolution scan order and specifications of a configured multiplication-addition matrix are determined; Based on the specification, the convolution matrix is channel grouped to obtain multiple channel groups; Determining a mapping order of the basic blocks based on the convolution scan order, the stripe operation length, and the plurality of channel groups; Reading the data of the basic block according to the mapping order, and caching the data of the basic block into the cache space according to the mapping order; In the mapping order, the data of the basic blocks that have completed the intermediate calculation and do not need to be reused are released from the cache space.

8. A convolution data cache and real-time release device, characterized in that: It includes a memory, a processor, and a cache of convolution data and a real-time release program stored in the memory and runnable on the processor. The processor executes the cache of convolution data and the real-time release program to implement the steps of the method for caching convolution data and its real-time release as described in any one of claims 1 to 6.

9. A medium, characterized in that The medium stores a program for implementing a method for caching convolution data and releasing it in real time. The program for implementing a method for caching convolution data and releasing it in real time is executed by a processor to implement the steps of the method for caching convolution data and releasing it in real time as described in any one of claims 1 to 6.

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