SOC verification optimization method, device, computer equipment, and medium based on instruction stream analysis

Abstract

The present application relates to a SOC verification and optimization method, apparatus, computer equipment, and medium based on instruction stream analysis, which uniformly samples subroutines of a program and extracts Basic Block sequence information in the subroutines; extracts instruction information of each Basic Block; aggregates instruction information and Basic Block sequence information to obtain an instruction sequence, and constructs an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and using a comparative learning method; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the Basic Block program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performs program selection based on the subroutine similarity matrix.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a SOC verification optimization method, apparatus, computer equipment, storage medium, and computer program product based on instruction stream analysis. Background Art

[0002] SoC is an integrated circuit (IC) design technology that reduces system size and power consumption while improving performance and efficiency by integrating all or most functions of a computer or electronic system onto a single chip. SoC is the core technology of modern electronic devices (such as smartphones, tablets, and IoT devices) and a cornerstone of the modern information industry. SoC testing is a series of processes used to verify the correctness of SoC designs. The main goals of SoC testing are to ensure that the SoC design meets specifications and functional requirements and to detect and locate design defects.

[0003] However, in a continuous integration and continuous deployment (CI / CD) environment, test suites can become large and difficult to maintain. Test program reduction techniques can simplify test suites, reducing the number of test cases or the total amount of test execution while maintaining test coverage and test quality. On the one hand, test program reduction can reduce test execution time, making the testing process more efficient. Reducing test cases can reduce the manpower, material, and time costs associated with testing and accelerate the feedback cycle. On the other hand, by eliminating unnecessary tests, resources can be focused on tests that are more important or more likely to discover defects. Removing redundant or duplicate test cases can improve the overall quality of the test suite. Through reduction, it is possible to ensure that every test case is necessary and that testing is more targeted at key functions and risk areas on the SoC.

[0004] However, there is no effective solution for reducing SoC test programs in conventional technologies. Summary of the Invention

[0005] Based on this, it is necessary to provide an effective SOC verification optimization method, device, computer equipment, storage medium and computer program product based on instruction stream analysis to address the above technical problems, so as to support effective SoC test program deletion.

[0006] In a first aspect, the present application provides a SOC verification and optimization method based on instruction flow analysis. The method comprises:

[0007] uniformly sampling subroutines of the program and extracting Basic Block sequence information in the subroutines;

[0008] Extract the instruction information of each Basic Block;

[0009] Aggregating the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0010] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method;

[0011] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0012] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0013] In one embodiment, the uniform sampling program subroutine and extracting BasicBlock sequence information in the subroutine includes:

[0014] Divide the program's execution time into several fixed-length intervals;

[0015] a subroutine of a uniform sampling procedure based on the plurality of fixed-length intervals;

[0016] Use Qemu to extract the Basic Block sequence information in the subroutine.

[0017] In one embodiment, constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence includes:

[0018] Building a vocabulary based on the instruction sequence, and extracting a first training data set from the vocabulary;

[0019] Performing context prediction training on an initial instruction semantic sequence model based on the first training data set, wherein the initial instruction semantic sequence model is constructed based on an autoregressive language model;

[0020] Calculating the difference between the predicted instruction and the actual next instruction during the context prediction training process to construct a first objective function;

[0021] Backpropagate the first objective function and calculate the gradient of the loss value with respect to the model parameters;

[0022] Use the gradient descent method to iteratively update the model parameters, return to the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set, until the loss value converges or reaches a preset number of training rounds, and obtain the instruction semantic sequence model.

[0023] In one embodiment, the constructing of a Basic Block program behavior representation model based on the instruction semantic sequence model using a contrastive learning method includes:

[0024] A readout token is added to the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

[0025] In one embodiment, the constructing of a Basic Block program behavior representation model based on the instruction semantic sequence model using a contrastive learning method includes:

[0026] Performing random masking on the instruction sequence to generate a second training data set for contrastive learning, the second training data set including positive sample pairs and negative sample pairs;

[0027] Generating a semantic representation vector for each basic block in the positive sample pair and the negative sample pair using the instruction semantic sequence model;

[0028] Calculate the similarity between the semantic representation vector of each basic block and the positive sample pair and the negative sample pair to obtain the second objective function based on cosine similarity;

[0029] Backpropagate the second objective function to calculate the gradient of the loss value with respect to the model parameters;

[0030] The model parameters are iteratively updated using the gradient descent method, and the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair is returned to, until the loss value converges or reaches a preset number of training rounds, to obtain a Basic Block program behavior representation model.

[0031] In one embodiment, the reading of a plurality of slice subroutines to be run and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model includes:

[0032] Slice the test programs in different test suites according to a preset fixed length interval to obtain a number of sliced ​​subroutines to be run;

[0033] further slicing the slicing subroutine into sub-segments;

[0034] Obtaining a semantic vector of each of the sub-segments through the Basic Block program behavior representation model;

[0035] The semantic vectors of the sub-segments are clustered using the KMeans clustering method to obtain the semantic representation of the slicing subroutine.

[0036] In one embodiment, constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine and performing program selection based on the subroutine similarity matrix includes:

[0037] Based on the semantic representation of the slicing subroutine, the similarity between the slicing program behavior vectors is measured using the cosine method to construct a slicing program similarity matrix;

[0038] The KMeans clustering algorithm is used to cluster the similarity matrix of the slicing programs, and representative subroutines are selected from them.

[0039] In a second aspect, the present application also provides a SOC verification and optimization device based on instruction flow analysis. The device comprises:

[0040] A sampling module, used for uniformly sampling the subroutines of a program and extracting Basic Block sequence information in the subroutines;

[0041] Extraction module, used to extract instruction information of each Basic Block;

[0042] A first model building module is configured to collect the instruction information and the Basic Block sequence information to obtain an instruction sequence, and to build an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0043] A second model building module is used to build a Basic Block program behavior representation model based on the instruction semantic sequence model using a contrastive learning method;

[0044] A semantic processing module, configured to read a plurality of slice subroutines to be run and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model;

[0045] A selection module is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and perform program selection based on the subroutine similarity matrix.

[0046] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are performed:

[0047] uniformly sampling subroutines of the program and extracting Basic Block sequence information in the subroutines;

[0048] Extract the instruction information of each Basic Block;

[0049] Aggregating the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0050] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method;

[0051] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0052] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0053] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0054] uniformly sampling subroutines of the program and extracting Basic Block sequence information in the subroutines;

[0055] Extract the instruction information of each Basic Block;

[0056] Aggregating the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0057] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method;

[0058] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0059] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0060] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the following steps:

[0061] uniformly sampling subroutines of the program and extracting Basic Block sequence information in the subroutines;

[0062] Extract the instruction information of each Basic Block;

[0063] Aggregating the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0064] Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method;

[0065] Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model;

[0066] A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

[0067] The above-mentioned SOC verification optimization method, apparatus, computer equipment, storage medium and computer program product based on instruction stream analysis uniformly samples the subroutines of the program and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; aggregates the instruction information and Basic Block sequence information to obtain the instruction sequence, and constructs an instruction semantic sequence model based on the autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and using a comparative learning method; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the BasicBlock program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutines, and selects programs based on the subroutine similarity matrix. Throughout the entire process, by analyzing the instruction sequence of the test program during execution, a hierarchical language model is established to analyze the behavior of the test program. The program features extracted based on the instruction sequence are close to the hardware functions, which enables the dynamic analysis method to achieve more effective test program reduction in SoC testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 FIG. 1 is an application environment diagram of a SOC verification and optimization method based on instruction stream analysis in one embodiment;

[0069] Figure 2 1 is a flow chart of a SOC verification and optimization method based on instruction stream analysis in one embodiment;

[0070] Figure 3 Schematic diagram of a sub-process of S300 in one embodiment;

[0071] Figure 4 Schematic diagram of a sub-process of S400 in one embodiment;

[0072] Figure 5 Schematic diagram of a sub-process of S500 in one embodiment;

[0073] Figure 6 1 is a structural block diagram of the SOC verification and optimization device based on instruction stream analysis in one embodiment;

[0074] Figure 7 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0076] In order to explain in detail the technical principles, technical solutions and effects of the SOC verification and optimization method based on instruction stream analysis of this application, the effects will first be introduced with respect to the overall inventive concept based on the prior art.

[0077] Test program reduction techniques are categorized into white-box testing and black-box testing based on test transparency. White-box testing is a testing method that deeply examines the internal structure and logic of the device under test (DUT). This requires the tester to have a deep understanding of the DUT's internal implementation and to know the coverage relationships between test programs and functional points. In contrast, black-box testing ignores the DUT's internal structure or implementation details and focuses on analyzing the external test program itself. By analyzing similarities between test programs, they can build models to reduce test programs.

[0078] The analysis methods of test programs in black box testing mainly include three types: historical behavior analysis, static analysis and dynamic analysis of test programs:

[0079] Historical behavior analysis primarily analyzes the behavior of test programs in previous test cycles (e.g., historical data such as test case execution history and defect discovery records) to build models that predict potential misbehavior or defect patterns that the software may exhibit in a new test cycle. Leveraging historical misbehavior, similarities between test programs can be modeled. If two test cases exhibited similar failure patterns in the past, they are likely to reveal similar defects in future tests. Based on this similarity model, test case selection and execution sequence can be optimized. A limitation of historical behavior analysis lies in its data dependency, which relies on the collection of historical test data. Without sufficient historical data, the analysis results will be inaccurate, rendering the method ineffective. However, in a rapidly iterative development environment, there may not be enough time to execute all test programs and collect data, especially in agile development and continuous integration practices. Furthermore, when test program reduction is required, the number of test programs is often large. Executing a large number of test programs to collect historical data requires significant computing resources and time, making it impractical in resource-constrained or tight testing cycles. Therefore, historical behavior analysis is only applicable to regression testing, where testers already have a set of existing historical execution data.

[0080] Static analysis methods focus on identifying similarities between test programs by analyzing their static characteristics without executing them. Static analysis typically involves reviewing the test program's source code, evaluating its structure, including module calls, data flow, and control flow, and comparing its textual content, such as comments, variable names, and function names. While not executing the program, static analysis methods can predict the code paths likely to be covered by analyzing the logical structure of test cases, thereby streamlining the number of test programs. Furthermore, static analysis techniques can identify repetitive or similar code patterns within test programs, reducing redundant testing. A limitation of static analysis methods is that they are only suitable for analyzing test programs with relatively small code size. As code size grows and its structure becomes more complex, static analysis struggles to understand and track the program's logic. Furthermore, the quality of test program code is not always guaranteed, and poor code quality can compromise the accuracy and consistency of static analysis.

[0081] Dynamic analysis methods focus on the actual runtime behavior of the test program. Unlike historical behavior analysis methods, dynamic analysis methods do not require running on a real device under test (DUT). Instead, simulators, virtual machines, or test doubles can be used to simulate the DUT's runtime environment and collect dynamic behavior data. Dynamic analysis methods include function call graph analysis and log analysis. Function call graph analysis primarily tracks the sequence of function calls during program execution, constructing a function call graph that reveals the program's control flow and helps identify program behavior. Log analysis methods primarily analyze detailed program runtime information. Analyzing logs can indirectly reveal program execution characteristics and help understand program behavior. When streamlining SoC test programs, reusability is a key consideration. On the one hand, the streamlining method does not need to change with hardware variations; on the other hand, it does not need to change with changes in the test suite. While function call graph analysis can provide some insight into program behavior, functions can change with changes in the test program, requiring updates when the test suite is updated.

[0082] This application is mainly based on the program dynamic analysis method and proposes a hierarchical language model for instruction sequence modeling for SoC test program deletion. The core idea of ​​this model is to analyze the instruction sequence of the test program during execution and establish a hierarchical language model to analyze the behavior of the test program. The program features extracted based on the instruction sequence are closest to the hardware functions, which makes the dynamic analysis method achieve more effective test program deletion in SoC testing.

[0083] The main problem faced in modeling the similarity between programs through instruction sequence analysis is the long dependency problem of instruction sequences. A program with 1 billion instructions is very small and may only take a few seconds to run, but existing mathematical models such as artificial neural networks cannot effectively analyze such long sequences. To this end, this solution adopts a hierarchical analysis method to split the long instruction sequence into several Basic Block sequences, first analyzing the information in the Basic Block sequence, and then integrating the representations of these Basic Block sequence fragments to form a representation of the complete instruction sequence. Basic Block is the smallest behavioral unit of a program, and BasicBlock is the smallest behavioral unit in a program. Basic Block sequence analysis can capture a variety of behaviors in a program. Therefore, this method can not only solve the dependency modeling problem of long sequences, but also capture the key behaviors of the program.

[0084] Furthermore, instructions are discrete tokens, making them difficult to process using traditional analysis methods. Effective sequence analysis requires converting instruction sequences into continuous vector representations. To this end, this solution employs a language model for instruction sequence modeling, converting instruction sequences into continuous vector representations. Language models have achieved significant success in the field of natural language processing (NLP), capable of extracting rich feature information from token sequences. Instruction sequences, similar to natural languages, have a fixed vocabulary of tokens, and the sequences themselves exhibit certain patterns. Therefore, language models can be used to model and analyze instruction sequences. Because language models are self-supervised learning models that do not require labeled training data, the training process is highly scalable. Large, unlabeled instruction sequences can be used to train instruction language models with larger parameter sizes, fully extracting the features of instruction sequences.

[0085] The instruction language model can only generate representations of instructions and cannot be used directly to represent instruction sequences. Existing research on language models has also found that the vector information output by the language model cannot be used to measure similarity using some simple methods. Therefore, this solution proposes a method based on contrastive learning to fine-tune the instruction language model so that it can generate instruction sequence vectors that can be calculated similarly. Contrastive learning captures and understands the semantic information of the program by narrowing the similarity between positive pairs and widening the distance between negative pairs, thereby obtaining instruction sequence representations that can be calculated similarly. Contrastive learning is also a self-supervised learning method that can generate a large amount of training data to train the model without manual labeling.

[0086] When processing a slice of 1 billion instructions, even if it is cut into subsequences, each subsequence is of length S, there will still be a large number of subsequences (1 billion -S Of these slice subsequences, only a small fraction are representative; the majority are noise subsequences. Therefore, this approach designs a clustering representation mechanism that extracts representative subsequences through clustering and combines all cluster centers to form a holistic representation of the subroutine. The underlying mechanism behind clustering is data compression, compressing a large number of subsequences into cluster centers. These cluster centers, as representations of subroutines, more accurately reflect the program's key features and behavior. This process can remove a significant number of noise subsequences and yield an effective representation of the subroutine.

[0087] Based on the above invention concept, the SOC verification optimization method based on instruction flow analysis provided by the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The terminal 102 sends a SoC test program deletion request to the server 104. The server 104 responds to the request, uniformly samples the subroutines of the program, and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; aggregates the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructs an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and a comparative learning method; reads several slice subroutines to be run, and obtains the semantic representation of the slice subroutine through the BasicBlock program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the slice subroutine, and performs program selection based on the subroutine similarity matrix. Terminal 102 may include, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices may include smart speakers, smart TVs, smart air conditioners, and smart car devices. Portable wearable devices may include smart watches, smart bracelets, and head-mounted devices. Server 104 may be implemented as a standalone server or a server cluster consisting of multiple servers.

[0088] In one embodiment, Figure 2 As shown in FIG, a SOC verification optimization method based on instruction flow analysis is provided to reduce the number of instructions. Figure 1 Taking the server 104 in the example as an example, the following steps are included:

[0089] S100: uniformly sampling the subroutines of the program and extracting the Basic Block sequence information in the subroutines.

[0090] Uniformly sampling a program's subroutines can specifically divide the program's execution time into several fixed-length intervals. These intervals are divided by the number of instructions (for example, 1 billion instructions). Each interval "segment" is considered a subroutine. After sampling the subroutines, the Basic Block sequence information is extracted. A Basic Block is the smallest unit in the program's execution control flow. Instructions within a Basic Block are continuous and do not jump. A Basic Block can be viewed as a node in the control flow graph, and the complex control flow of a program can be simplified into several Basic Blocks and their connections.

[0091] S200: Extracting instruction information of each Basic Block.

[0092] A plugin can be used to extract the instruction information of a Basic Block. Specifically, when obtaining Basic Block sequence information, Qemu can be used to extract the Basic Block sequence information in the subroutine. To extract the instruction information in each Basic Block, the plugin can be used to register a plugin function during the TB execution phase of QEMU's simulation of the target program, recording all the instruction contents in the TB, which is the instruction information in the Basic Block.

[0093] S300: Collect instruction information and Basic Block sequence information to obtain an instruction sequence, and construct an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence.

[0094] The instruction semantic sequence model consists of a word embedding layer and an encoding layer. The encoding layer uses a 12-layer Transformer encoder. The word embedding layer not only encodes token content but also token position encoding to preserve sequence order and token category encoding to maintain sensitivity to different instruction content. Tokens within the same instruction use the same position encoding. Token category encodings include five token categories: opcode, condition code, register, operand, and operation address. An autoregressive language model is a self-supervised learning approach that trains the model to effectively predict the next instruction during program execution, guiding the model to understand and represent the meaning of program instructions. Through this self-supervised learning approach, the instruction semantic representation model captures and understands the relationships and semantic information between program instructions. Based on the previous processing steps, a large amount of instruction information and Basic Block sequence information is collected from the program execution process to obtain an instruction sequence. This instruction sequence serves as the data foundation for constructing an instruction semantic sequence model based on the autoregressive language model.

[0095] Specifically, a language model is used here to build an instruction sequence model. Instructions are discrete tokens, making them difficult to process with traditional analysis methods. Effective sequence analysis requires converting instruction sequences into continuous vector representations. Language models have achieved great success in the field of natural language processing (NLP), capable of extracting rich feature information from token sequences. Instruction sequences, similar to natural languages, have a fixed vocabulary of tokens and inherent patterns. Therefore, language models can be used to model and analyze instruction sequences, thus building an instruction sequence model.

[0096] S400: Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method.

[0097] A Basic Block program behavior representation model is constructed based on a contrastive learning approach. Specifically, the program behavior representation model is constructed based on the instruction semantic sequence model. This involves adding a readout token ([read-out]token) to the end of the instruction semantic sequence model's input to integrate the output of the instructions in the basic block. The output vector of the instruction semantic sequence model on the [read-out]token is input into a fully connected layer for feature transformation, and the transformed vector serves as the behavior representation of the basic block. The above model construction process is a self-supervised learning method. This method can compress and encode the input data by recovering the original data from noisy data.

[0098] Specifically, contrastive learning is used here to construct an instruction sequence representation model that can measure similarity. The vector information output by the language model cannot be used to measure similarity using simple methods. By fine-tuning the instruction representation model using contrastive learning, an instruction sequence representation model with measurable similarity can be constructed. Contrastive learning captures and understands program semantics by narrowing the similarity between positive pairs and distancing the similarity between negative pairs, resulting in an instruction sequence representation that can be used to calculate similarity.

[0099] S500: Read several slice subroutines to be run, and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model.

[0100] The test programs in different test suites are sliced ​​at fixed-length intervals to obtain several sliced ​​subroutine snapshots to be run. In the present invention, the length interval is set to 1 billion instructions. Select a test suite containing multiple test programs and collect the complete execution traces of the test programs in different test suites. Run each test program and record the instruction sequence it executes. Store the collected instruction execution traces in a log file for subsequent processing. Set the fixed-length interval of slicing to 1 billion instructions, count each instruction in the instruction execution trace, and slice it after reaching 1 billion instructions to generate several subroutine snapshots. Repeat the above process until all instruction sequences are processed. Each subroutine snapshot contains instructions of a fixed length.

[0101] The program behavior representation model constructed in S400 is used to obtain the semantic representation of the sliced ​​subroutine. To accurately represent the semantic features of the sliced ​​subroutine, the sliced ​​subroutine is further divided into smaller sub-segments. These sub-segments are semantically represented using the program behavior representation model to obtain the local behavioral features of the subroutine.

[0102] S600: Constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performing program selection based on the subroutine similarity matrix.

[0103] Based on the semantic representation of the sliced ​​subroutines obtained in S500, a subroutine similarity matrix is ​​constructed to characterize the similarity between the sliced ​​program behavior vectors. Then, based on the subroutine similarity matrix, program selection is performed to achieve program deletion, ultimately supporting effective SoC test program deletion.

[0104] The above-mentioned SOC verification optimization method based on instruction stream analysis uniformly samples the subroutines of the program and extracts the Basic Block sequence information in the subroutines; extracts the instruction information of each Basic Block; aggregates the instruction information and BasicBlock sequence information to obtain the instruction sequence, and constructs an instruction semantic sequence model based on the autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and using comparative learning; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the Basic Block program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutines, and selects programs based on the subroutine similarity matrix. Throughout the entire process, by analyzing the instruction sequence of the test program during execution, a hierarchical language model is established to analyze the test program's behavior. The program features extracted based on the instruction sequence are close to the hardware functions, which enables the dynamic analysis method to achieve more effective test program reduction in SoC testing.

[0105] In one embodiment, uniformly sampling subroutines of a program and extracting Basic Block sequence information from the subroutines includes: dividing the execution time of the program into a number of fixed-length intervals; uniformly sampling the subroutines of the program based on the number of fixed-length intervals; and extracting Basic Block sequence information from the subroutines using Qemu.

[0106] In this embodiment, Qemu is used to extract the Basic Block sequence information in the subroutine. Qemu is an open source emulator and virtual machine. Qemu uses the basic block of the program as the unit and establishes a TCG (tinycode generator) translation layer between the host machine and the target architecture to translate the instructions of the target architecture into host machine instructions for execution. The code block obtained by translation is called a translation block (TB), which is equivalent to the basic block of the program execution under the target architecture. Qemu provides a plug-in mechanism to observe and record the operation of the target program. It can load and run one or more plug-ins in the form of a dynamic link library at startup. The plug-in function is registered in the TB execution phase of the target program simulated by Qemu through the plug-in, and the instruction address of the TB is recorded as the mark of the Basic Block. The address information of these Basic Blocks will be retained and the execution sequence information of the Basic Block will be formed in chronological order.

[0107] like Figure 3 As shown, in one embodiment, S300 includes:

[0108] S310: Collect instruction information and Basic Block sequence information to obtain an instruction sequence.

[0109] The instruction information and Basic Block sequence information obtained in the previous processing steps are collected and sorted to obtain a large number of instruction sequences.

[0110] S320: Construct a vocabulary based on the instruction sequence, and extract a first training data set from the vocabulary.

[0111] In an instruction sequence, an instruction includes an opcode, an operand, and a register. Each instruction is split to obtain the opcode, operand, and register associated with the instruction. For example, an instruction MOV R1,100 can be split into MOV (opcode), R1 (register), and 100 (operand). The opcode, operand, and register are regarded as tokens. All independent tokens are collected to build a vocabulary. The vocabulary can be represented by a dictionary, where the key is the token and the value is the corresponding unique index. A training data set is constructed from the collected instruction sequence. A subsequence of 128 instructions is randomly sampled from the instruction sequence. The length of the subsequence can be adjusted as needed, but is fixed to 128 instructions in the present invention. Each subsequence is part of the training data, and each instruction in the subsequence is decomposed into a token index for input into the model.

[0112] S330: Performing context prediction training on an initial instruction semantic sequence model based on the first training data set, where the initial instruction semantic sequence model is constructed based on an autoregressive language model.

[0113] The initial instruction semantic model is used to predict the next instruction. The token indices of the input 128 instructions are converted into embedding vectors. The embedding vectors of the first 128 instructions are input into the Transformer encoder, and the model outputs the prediction for the next instruction, which is the 129th instruction after the 128th instruction.

[0114] S340: Calculate the difference between the predicted instruction and the actual next instruction during the context prediction training process, and construct a first objective function.

[0115] Calculate the difference between the predicted instruction and the actual next instruction. The actual next instruction contains multiple tokens (opcode, operand, register, etc.). For each predicted token, calculate the cross entropy loss. Specifically, calculate the cross entropy between the predicted distribution and the actual distribution at each position. Sum the losses of all tokens to get the overall loss value.

[0116] S350: Perform backpropagation on the first objective function and calculate the gradient of the loss value with respect to the model parameters.

[0117] Backpropagate the objective function in S340 to calculate the gradient of the loss value with respect to the model parameters.

[0118] S360: Use the gradient descent method to iteratively update the model parameters and return to step S330 until the loss value converges or reaches the preset number of training rounds to obtain the instruction semantic sequence model.

[0119] The model parameters are updated using a gradient descent algorithm. Steps S300 to S350 are repeated to iteratively update the model parameters until the loss converges or the preset number of training rounds is reached, ultimately obtaining an instruction semantic sequence model.

[0120] like Figure 4 As shown, in one embodiment, S400 includes:

[0121] S410: Perform random masking processing on the instruction sequence to generate a second training data set for contrastive learning, where the second training data set includes positive sample pairs and negative sample pairs.

[0122] Training data construction. A training dataset is constructed from the collected instruction sequences. Training data for comparative learning is generated through random masking, including positive sample pairs and negative sample pairs. Specifically, some instructions in each Basic Block are randomly masked, that is, some tokens of some instructions are randomly selected for masking. The positive sample of the original sample is the Basic Block after some tokens of some instructions in the basic block are randomly masked. The original basic block and the randomly masked basic block form a positive sample pair. In the construction of negative sample pairs, the negative samples are 63 other basic blocks randomly selected from the dataset. The original basic block and the 64 randomly selected basic blocks form negative sample pairs respectively.

[0123] S420: Generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair using an instruction semantic sequence model.

[0124] The instruction semantic sequence model is used to generate a semantic representation vector for each basic block. A special [read-out] token is added to the end of each basic block. This token is used to extract the overall semantic representation of the basic block. The basic block containing the [read-out] token is input into the instruction semantic sequence model, and the semantic representation vector of the entire basic block is extracted using the [read-out] token.

[0125] S430: Calculate the similarity between each basic block semantic representation vector and the positive sample pair and the negative sample pair to obtain a second objective function based on cosine similarity.

[0126] The model is trained by maximizing the similarity of positive pairs and minimizing the similarity of negative pairs. For each basic block, the similarity between its semantic representation vector and both the positive and negative pairs is calculated, using cosine similarity to measure similarity. The Softmax function is used to convert the similarity into a probability distribution. The goal is to maximize the similarity probability for positive pairs and minimize the similarity probability for negative pairs. The loss is calculated using the comparative InfoNCE function.

[0127] S440: Perform backpropagation on the second objective function to calculate the gradient of the loss value with respect to the model parameters.

[0128] Backpropagation is performed on the second objective function in S430 to calculate the gradient of the loss value with respect to the model parameters.

[0129] S450: Iteratively update the model parameters using the gradient descent method, and return to S420 until the loss value converges or reaches a preset number of training rounds, to obtain a Basic Block program behavior representation model.

[0130] The model parameters are updated using the gradient descent algorithm. S420 to S450 are repeated to iteratively update the model parameters until the loss value converges or the preset number of training rounds is reached.

[0131] like Figure 5 As shown, in one embodiment, S500 includes:

[0132] S510: Slice the test programs in different test suites according to intervals of preset fixed lengths to obtain a number of sliced ​​subroutines to be run.

[0133] The test programs in different test suites are sliced ​​at fixed-length intervals to obtain several sliced ​​subroutine snapshots to be run. In the present invention, the length interval is set to 1 billion instructions. Select a test suite containing multiple test programs and collect the complete execution traces of the test programs in different test suites. Run each test program and record the instruction sequence it executes. Store the collected instruction execution traces in a log file for subsequent processing. Set the fixed-length interval of slicing to 1 billion instructions, count each instruction in the instruction execution trace, and slice it after reaching 1 billion instructions to generate several subroutine snapshots. Repeat the above process until all instruction sequences are processed. Each subroutine snapshot contains instructions of a fixed length.

[0134] S520: Further divide the slicing subroutine into sub-segments.

[0135] The sliced ​​subroutine is further divided into sub-segments. The sliced ​​subroutine is further divided into smaller sub-segments to capture finer-grained program features and avoid failure of program feature capture due to overly long dependencies. Select an appropriate sub-segment length. In this invention, 128 Basic Blocks are used as the length of the sub-segment. The specific length can be adjusted according to actual needs and model capabilities. The selected length should ensure that it is sufficient to capture the local behavioral characteristics of the program. After segmentation, a subroutine of length S will contain S-128 sub-segments.

[0136] S530: Obtain the semantic vector of each sub-segment through the Basic Block program behavior representation model.

[0137] The semantic vector of each sub-segment is obtained through the Basic Block program behavior representation model obtained previously.

[0138] S540: clustering the semantic vectors of the sub-segments using a KMeans clustering method to obtain a semantic representation of the slice subroutine.

[0139] Program behavior representation based on feature clustering. To handle the semantic representation of large sub-fragments, direct averaging may result in feature loss or inaccuracy. To better capture and express the overall behavioral characteristics of a program, the semantic vectors of the sub-fragments are clustered using the KMeans clustering method. The distance metric used for clustering is Cosine similarity, and the number of clusters is set to 1024. The average of the 1024 cluster centers is then used to represent the overall behavioral characteristics of the program, resulting in a sub-program feature vector.

[0140] Overall, a clustering representation mechanism is employed here to obtain a global semantic representation of a sliced ​​subroutine. Clustering extracts distinctive subsequences, and all cluster centers are combined to form a holistic representation of the subroutine. The underlying mechanism of clustering is data compression, compressing a large number of subsequences into cluster centers. These cluster centers, as representations of subroutines, more accurately reflect the program's key features and behavior. This process can eliminate numerous noisy subsequences and yield an effective representation of the subroutine.

[0141] In one embodiment, constructing a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutines, and performing program selection based on the subroutine similarity matrix includes:

[0142] Step 1: Based on the semantic representation of slice subroutines, the cosine method is used to measure the similarity between slice program behavior vectors and construct a slice program similarity matrix.

[0143] Construct a subroutine similarity matrix. Based on the semantic representation vector of each slice subroutine obtained in the previous step, use the cosine method to measure the similarity between slice program behavior vectors and construct a slice program similarity matrix. By calculating the cosine similarity between slice program behavior vectors, a similarity matrix is ​​constructed to reflect the similarity between different slice subroutines.

[0144] Step 2: Use the KMeans clustering algorithm to cluster the slice program similarity matrix and select representative subroutines from it.

[0145] KMeans clustering selects subroutines. Use the KMeans clustering algorithm to cluster the similarity matrix and select representative subroutines. The KMeans algorithm clusters similar subroutines into the same group and finds the center of each group. The number of cluster centers, K, is determined based on the number of subroutines to be selected. This number is usually determined by the actual testing requirements. Run the KMeans algorithm to cluster the sliced ​​subroutines into K clusters. Select the subroutines closest to the center to obtain K representative subroutines. These K subroutines are then selected for actual testing.

[0146] In general, in the above embodiments, the SOC verification and optimization method based on instruction stream analysis of the present application has the following significant technical advantages:

[0147] One of the advantages of this application is its high reusability. Since the instruction set is fixed, the vocabulary of the instruction sequence representation model is also fixed. For the same instruction set, the changes in the instructions are very small and basically fixed. Therefore, the model does not need to update the vocabulary frequently, and the same vocabulary can be used for sequence representation for a long time. Due to the fixedness of the instruction set and the vocabulary, the sequence representation model trained based on the instruction set can be reused in different projects and tests. Whether it is a newly designed SoC or an improved version of an existing SoC, as long as the instruction set remains unchanged, the model can be directly applied without retraining.

[0148] A second advantage of this application is that by evenly slicing the test program at instruction intervals, the length of the test program can be reduced. The shorter the test program, the more concentrated and clear its behavioral characteristics are, which facilitates accurate matching of similar behaviors. Through refined similarity analysis, it is easier to find other program fragments with similar behavior, thereby effectively pruning the test program. This reduces redundant test cases and improves testing efficiency and quality.

[0149] The third advantage of this application is its cross-test suite analysis capability. In SoC testing, the test programs generated by different test suites will eventually run on the SoC system in the form of instruction sequences. Therefore, the analysis method based on instruction sequences can uniformly analyze and optimize the test programs across different test suites. This uniformity helps maintain consistency in analysis methods when managing and maintaining multiple test suites, reducing the complexity caused by differences between different suites.

[0150] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0151] Based on the same inventive concept, the present application also provides an instruction stream analysis-based SOC verification and optimization device for implementing the aforementioned instruction stream analysis-based SOC verification and optimization method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more of the following embodiments of the instruction stream analysis-based SOC verification and optimization device can be found in the above-mentioned limitations of the instruction stream analysis-based SOC verification and optimization method, and will not be repeated here.

[0152] In one embodiment, Figure 6 As shown, a SOC verification and optimization device based on instruction stream analysis is provided, comprising:

[0153] The sampling module 100 is used to uniformly sample the subroutines of the program and extract the Basic Block sequence information in the subroutines;

[0154] Extraction module 200, used to extract instruction information of each Basic Block;

[0155] The first model building module 300 is used to collect instruction information and Basic Block sequence information to obtain an instruction sequence, and to build an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence;

[0156] The second model building module 400 is used to build a Basic Block program behavior representation model based on the instruction semantic sequence model using a contrastive learning method;

[0157] The semantic processing module 500 is used to read a number of slice subroutines to be run and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model;

[0158] The selection module 600 is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutines, and perform program selection based on the subroutine similarity matrix.

[0159] In one embodiment, the sampling module 100 is further configured to divide the execution time of the program into a number of fixed-length intervals; uniformly sample the subroutines of the program based on the number of fixed-length intervals; and extract Basic Block sequence information in the subroutines using Qemu.

[0160] In one embodiment, the first model construction module 300 is also used to construct a vocabulary based on the instruction sequence and extract a first training data set from the vocabulary; perform context prediction training on the initial instruction semantic sequence model based on the first training data set, and the initial instruction semantic sequence model is constructed based on the autoregressive language model; calculate the difference between the predicted instruction and the actual next instruction during the context prediction training process, and construct a first objective function; perform backpropagation on the first objective function, and calculate the gradient of the loss value with respect to the model parameters; use the gradient descent method to iteratively update the model parameters, and return to the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set, until the loss value converges or reaches a preset number of training rounds, and obtain the instruction semantic sequence model.

[0161] In one embodiment, the second model building module 400 is further configured to add a readout token at the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

[0162] In one embodiment, the second model building module 400 is also used to perform random masking on the instruction sequence to generate a second training data set for comparative learning, the second training data set including positive sample pairs and negative sample pairs; use the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair; calculate the similarity between the semantic representation vector of each basic block and the positive sample pair and the negative sample pair to obtain a second objective function based on cosine similarity; perform backpropagation on the second objective function to calculate the gradient of the loss value relative to the model parameters; use the gradient descent method to iteratively update the model parameters, and return to the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair, until the loss value converges or reaches a preset number of training rounds, and obtain the Basic Block program behavior representation model.

[0163] In one embodiment, the semantic processing module 500 is also used to slice the test programs in different test suites according to preset fixed-length intervals to obtain a number of sliced ​​subroutines to be run; further divide the sliced ​​subroutines into sub-segments; obtain the semantic vector of each sub-segment through the Basic Block program behavior representation model; and cluster the semantic vectors of the sub-segments using the KMeans clustering method to obtain the semantic representation of the sliced ​​subroutine.

[0164] In one embodiment, the selection module 600 is also used to measure the similarity between slicer program behavior vectors based on the semantic representation of the slicer subroutines using the cosine method to construct a slicer program similarity matrix; and to cluster the slicer program similarity matrix using the KMeans clustering algorithm to select representative subroutines therefrom.

[0165] Each module in the above-mentioned SOC verification and optimization device based on instruction stream analysis can be implemented in whole or in part through software, hardware, or a combination thereof. Each of the above modules can be embedded in or independent of the processor of the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0166] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store preset data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a SOC verification and optimization method based on instruction stream analysis is implemented.

[0167] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0168] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the above-mentioned SOC verification and optimization method based on instruction stream analysis when executing the computer program.

[0169] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the SOC verification and optimization method based on instruction stream analysis is implemented.

[0170] In one embodiment, a computer program product is provided, including a computer program, which implements the above-mentioned SOC verification and optimization method based on instruction stream analysis when executed by a processor.

[0171] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0172] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program. The above-mentioned computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0173] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0174] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A SOC verification and optimization method based on instruction flow analysis, characterized in that: The method comprises: uniformly sampling subroutines of the program and extracting Basic Block sequence information in the subroutines; Extract the instruction information of each Basic Block; Aggregating the instruction information and the Basic Block sequence information to obtain an instruction sequence, and constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; Based on the instruction semantic sequence model, a Basic Block program behavior representation model is constructed using a contrastive learning method; Reading a number of slice subroutines to be run, and obtaining semantic representations of the slice subroutines through the Basic Block program behavior representation model; A subroutine similarity matrix is ​​constructed based on the semantic representation of the sliced ​​subroutines, and program selection is performed based on the subroutine similarity matrix.

2. The method according to claim 1, characterized in that The subroutine of the uniform sampling program and extracting the Basic Block sequence information in the subroutine include: Divide the program's execution time into several fixed-length intervals; a subroutine of a uniform sampling procedure based on the plurality of fixed-length intervals; Use Qemu to extract the Basic Block sequence information in the subroutine.

3. The method according to claim 1, characterized in that Constructing an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence includes: Building a vocabulary based on the instruction sequence, and extracting a first training data set from the vocabulary; Performing context prediction training on an initial instruction semantic sequence model based on the first training data set, wherein the initial instruction semantic sequence model is constructed based on an autoregressive language model; Calculating the difference between the predicted instruction and the actual next instruction during the context prediction training process to construct a first objective function; Backpropagate the first objective function and calculate the gradient of the loss value with respect to the model parameters; Use the gradient descent method to iteratively update the model parameters, return to the step of performing context prediction training on the initial instruction semantic sequence model based on the first training data set, until the loss value converges or reaches a preset number of training rounds, and obtain the instruction semantic sequence model.

4. The method according to claim 1, wherein The method of constructing a Basic Block program behavior representation model based on the instruction semantic sequence model and using a contrastive learning method includes: A readout token is added to the end of the input of the instruction semantic sequence model to obtain a Basic Block program behavior representation model.

5. The method according to claim 1, wherein The method of constructing a Basic Block program behavior representation model based on the instruction semantic sequence model and using a contrastive learning method includes: Performing random masking on the instruction sequence to generate a second training data set for contrastive learning, the second training data set including positive sample pairs and negative sample pairs; Generating a semantic representation vector for each basic block in the positive sample pair and the negative sample pair using the instruction semantic sequence model; Calculate the similarity between the semantic representation vector of each basic block and the positive sample pair and the negative sample pair to obtain the second objective function based on cosine similarity; Backpropagate the second objective function to calculate the gradient of the loss value with respect to the model parameters; The model parameters are iteratively updated using the gradient descent method, and the step of using the instruction semantic sequence model to generate a semantic representation vector for each basic block in the positive sample pair and the negative sample pair is returned to, until the loss value converges or reaches a preset number of training rounds, to obtain a Basic Block program behavior representation model.

6. The method according to claim 1, characterized in that The step of reading a plurality of slice subroutines to be run and obtaining the semantic representation of the slice subroutines through the Basic Block program behavior representation model includes: Slice the test programs in different test suites according to a preset fixed length interval to obtain a number of sliced ​​subroutines to be run; further slicing the slicing subroutine into sub-segments; Obtaining a semantic vector of each of the sub-segments through the Basic Block program behavior representation model; The semantic vectors of the sub-segments are clustered using the KMeans clustering method to obtain the semantic representation of the slicing subroutine.

7. The method according to claim 1, characterized in that The constructing of a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine and performing program selection based on the subroutine similarity matrix includes: Based on the semantic representation of the slicing subroutine, the similarity between the slicing program behavior vectors is measured using the cosine method to construct a slicing program similarity matrix; The KMeans clustering algorithm is used to cluster the similarity matrix of the slicing programs, and representative subroutines are selected from them.

8. A SOC verification and optimization device based on instruction flow analysis, characterized in that: The device comprises: A sampling module, used for uniformly sampling the subroutines of a program and extracting Basic Block sequence information in the subroutines; Extraction module, used to extract instruction information of each Basic Block; A first model building module is configured to collect the instruction information and the Basic Block sequence information to obtain an instruction sequence, and to build an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; A second model building module is used to build a BasicBlock program behavior representation model based on the instruction semantic sequence model using a contrastive learning method; A semantic processing module, configured to read a plurality of slice subroutines to be run and obtain the semantic representation of the slice subroutines through the Basic Block program behavior representation model; A selection module is used to construct a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and perform program selection based on the subroutine similarity matrix.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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