A memory failure handling method and apparatus

Abstract

A memory fault processing method and device are applied to a device including a first storage controller and a second storage controller. The first storage controller manages a first memory, and the second storage controller manages a second memory. The second memory managed by the second storage controller forms a backup space of a storage space of the first memory managed by the first storage controller. The method includes: when a fault of the first memory managed by the first storage controller is found, transferring a data read-write operation of the device from the storage space formed by the first memory managed by the first storage controller to the storage space formed by the second memory managed by the second storage controller. This mode is suitable for a scenario in which a DCPMM is used as the first memory, and can ensure the reliability of data in the DCPMM.

Description

[0001] This application is a divisional application, the original application number is 201910945454.9, the original application date is September 30, 2019, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, in particular to a memory fault processing method and device. BACKGROUND

[0003] Memory is an important component in a device, which can store data required for processor operation in the device, and can also exchange data with external storage such as a hard disk in the device.

[0004] When the device is running, the processor can first call the data required for operation to the memory, and the processor obtains the data required for operation from the memory to perform operation. If the data in the memory is incorrect, it will affect the overall operation of the device.

[0005] The traditional memory is volatile memory, that is, when the device is powered off, the data in the memory will be lost, resulting in the device cannot run normally. In order to ensure that the data in the memory can still exist after the device is powered off, persistent memory is derived, such as data center persistent memory (DCPMM). DCPMM is also known as direct current persistent memory in the industry. The capacity of persistent memory is larger, and the read-write speed is close to that of volatile memory.

[0006] Although the persistent memory can store data for a long time, it also faces the problem of data reliability. For example, when the persistent memory has a performance fault, the processor cannot obtain data from the persistent memory to perform operation, thereby causing the device to not run normally.

[0007] In summary, there is an urgent need for an effective method for ensuring data reliability suitable for persistent memory. SUMMARY

[0008] The present application provides a memory fault processing method and device to provide a method for ensuring data reliability in DCPMM.

[0009] In a first aspect, the present application provides a memory fault processing method, which is applied to a device including a first storage controller and a second storage controller, the first storage controller manages a first memory, and the second storage controller manages a second memory; here, the number of the first memory and the second memory is not limited, and can be one or multiple. The second memory managed by the second storage controller forms a backup space of the storage space of the first memory managed by the first storage controller, and the method includes: when a fault of the first memory managed by the first storage controller is found, transferring the data read-write operation of the device from the storage space formed by the first memory managed by the first storage controller to the storage space formed by the second memory managed by the second storage controller.

[0010] Through the above method, the storage space formed by the memory managed by the storage controller (the first storage controller and the second storage controller) is taken as the granularity for the primary and backup storage space, which is suitable for the scenario that the DCPMM is used as the memory (such as the first memory or the second memory); in addition, when a fault of the memory managed by one of the storage controllers occurs, the data read-write operation of the device is switched to the storage space managed by the other manager, which can ensure the reliability of the data.

[0011] In a possible implementation, in the device, the data in the second memory managed by the second storage controller can also be used to perform data write-back on the fault data in the first memory managed by the first storage controller, and the data of the fault first memory is recovered.

[0012] If the write-back is successful, after the device is powered on next time, the data read-write operation of the device can be switched to the storage space formed by the first memory managed by the first storage controller.

[0013] Through the above method, the data of the fault first memory can be effectively recovered, the storage space formed by the first memory managed by the first storage controller can be restored to normal, and the device can continue to perform the data read-write operation on the storage space formed by the first memory managed by the first storage controller.

[0014] In a possible implementation, if the write-back fails, the device can send an alarm information, and the alarm information is used to indicate that the first memory has a fault.

[0015] Through the above method, if the data of the fault first memory cannot be recovered, the user can be reminded in time, so that the user can find the fault of the first memory in the device in time, and replace the fault first memory.

[0016] In a possible implementation, the first storage controller manages the DCPMM, and the second storage controller manages the DCPMM. That is, the first storage and the second storage are both DCPMMs, and the first storage controller and the second storage controller are memory controllers, for example, the memory controllers can be IMCs.

[0017] By the above method, the storage space formed by the DCPMM managed by the memory controller is used as the granularity of the primary and backup storage spaces, which can better guarantee the reliability of the data in the DCPMM, is suitable for different insertion methods of the DCPMM, and because the DCPMM itself has a good read-write rate, the overall data reading efficiency of the device is high in this case, and the overall performance of the device can be guaranteed.

[0018] In a possible implementation, the first storage controller manages the DCPMM, and the second storage controller manages a plurality of disks, the first storage controller is a memory controller, and the second storage controller is a RAID card.

[0019] By the above method, the reliability of the data in the DCPMM managed by the memory controller can be guaranteed, and in this case, the storage space formed by the plurality of disks is used as the backup space, instead of using the storage space formed by part of the DCPMM managed by the memory controller as the backup space, which can effectively save costs.

[0020] In a possible implementation, in the device, the storage space of the plurality of first storages managed by the first storage controller can be mapped to the logical space of the first storage controller, and a mapping relationship of the address of the storage space of the first storage to the address of the logical space of the first storage controller is established. In this way, when the first storage controller stores data in the first storage, the first storage controller can allocate the address of the logical space to the data, so that the data can be more evenly distributed in each first storage, and the data balance of the plurality of first storages managed by the first storage is realized.

[0021] In a possible implementation, before the first storage managed by the first storage controller fails, the first storage managed by the first storage controller can be detected for failure. A default function can be set in the device, and the function can be started when the device is initially started. The function includes a failure detection function, and also indicates that when it is detected that the first storage fails, the data of the backup space is used to perform data write-back to the first storage.

[0022] By the above method, the failure detection function is started in advance, so that the first storage with failure can be found in time, and when the first storage fails, the data write-back can be performed in time, so as to ensure the reliability of the data and ensure that the device can normally operate.

[0023] In a possible implementation, before the first storage controlled by the first storage controller fails, when the device is started, the user can be prompted to select a mode of the primary and backup storage spaces, such as a first mode or a second mode, the first mode can be a performance mode capable of guaranteeing read-write efficiency (corresponding to the case that the first storage and the second storage are both DCPMM, and the first storage controller and the second storage controller are both memory controllers), and the second mode can be a cost mode capable of saving cost (corresponding to the case that the first storage is DCPMM, the first storage controller is a memory controller, the second storage is a disk, and the second storage controller is a RAID card). The user can select the required mode and trigger an instruction, which is used to instruct to configure the first mode or the second mode. When the device receives the instruction triggered by the user, the first mode or the second mode is configured in response to the instruction triggered by the user. When the first mode or the second mode is configured, address mapping can be performed on the storage space formed by the first storage controlled by the first storage controller and the storage space formed by the second storage controlled by the second storage controller, the storage space formed by the first storage controlled by the first storage controller is configured as the primary storage space, and the storage space formed by the second storage controlled by the second storage controller is configured as the backup storage space.

[0024] Through the above method, the primary and backup storage spaces in different modes can be flexibly configured according to the instruction triggered by the user, more choices are given to the user, the user experience is improved, and the storage space formed by the first storage controlled by the first storage controller and the storage space formed by the second storage controlled by the second storage controller are associated through address mapping.

[0025] In a possible implementation, when the storage space formed by the first storage controlled by the first storage controller and the storage space formed by the second storage controlled by the second storage controller are address mapped, the storage space formed by the first storage controlled by the first storage controller can be divided into a plurality of sub-blocks, and the storage space formed by the second storage controlled by the second storage controller can also be divided into a plurality of sub-blocks. A one-to-one mapping relationship between the addresses of the sub-blocks of the storage space formed by the first storage controlled by the first storage controller and the addresses of the sub-blocks of the storage space formed by the second storage controlled by the second storage controller is established.

[0026] Through the above method, the storage space formed by the first storage controlled by the first storage controller and the storage space formed by the second storage controlled by the second storage controller are address mapped through the division of the sub-blocks, and this method is simpler and more efficient.

[0027] In a second aspect, the embodiments of the present application further provide a fault processing apparatus, and beneficial effects can be referred to the description of the first aspect, which will not be repeated here. The apparatus has functions to implement the behaviors in the method examples of the first aspect. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. In one possible design, the structure of the fault processing apparatus includes a detection unit and a switching unit, and can further include a write-back unit and a configuration unit, which can perform the corresponding functions in the method examples of the first aspect, and specific details can be referred to the detailed description in the method examples, which will not be repeated here.

[0028] In a fourth aspect, the embodiments of the present application further provide an apparatus, and beneficial effects can be referred to the description of the first aspect, which will not be repeated here. The structure of the apparatus includes a processing unit, a first memory and a second memory, and the processing unit is configured to support the apparatus to perform the corresponding functions in the method of the first aspect. The first memory and the second memory are coupled with the processor, and the first memory or the second memory stores necessary program instructions and data of the apparatus. The structure of the apparatus further includes a communication interface for communication with other apparatuses.

[0029] In a fifth aspect, the present application further provides a computer readable storage medium, which stores instructions, and when the instructions are run on a computer, the computer executes the method of the above aspects.

[0030] In a sixth aspect, the present application further provides a computer program product containing instructions, and when the instructions are run on a computer, the computer executes the method of the above aspects.

[0031] In a seventh aspect, the present application further provides a computer chip, which is connected with a memory, and the chip is used to read and execute software programs stored in the memory, and executes the method of the above aspects. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A memory management system architecture schematic diagram is provided for the present application;

[0033] Figure 2 Another memory management system architecture schematic diagram is provided for the present application;

[0034] Figure 3 A memory management system configuration method schematic diagram is provided for the present application;

[0035] Figure 4 A memory fault processing method schematic diagram is provided for the present application;

[0036] Figure 5 Another memory fault processing method schematic diagram is provided for the present application;

[0037] Figure 6 A structural schematic diagram of a fault processing device provided in the present application is shown in the figure;

[0038] Figure 7 A structural schematic diagram of a device provided in the present application is shown in the figure. DETAILED DESCRIPTION

[0039] The embodiment of the present application provides a memory fault processing method. In the embodiment of the present application, a storage space managed by a storage controller is taken as a granularity for mirror configuration. A storage space formed by a first storage managed by a first storage controller is taken as a main storage space, and a storage space formed by a second storage managed by a second storage controller is taken as a backup storage space. When the first storage managed by the first storage controller fails, the device switches the main storage space and the backup storage space, switches data read-write operation of the device to the backup storage space, and performs data back-write on the failed first storage by using data stored in the backup storage space. The embodiment of the present application takes the storage space of the storage (the first storage and the second storage) managed by the storage controller (the first storage controller and the second storage controller) as a granularity for the main storage space and the backup storage space, is suitable for a scenario in which the DCPMM is used as the storage (such as the first storage or the second storage), can guarantee data reliability of the DCPMM, is suitable for different insertion methods of multiple DCPMMs in the device, and effectively expands an application range.

[0040] In the embodiment of the present application, the types of the storage (such as the first storage or the second storage) managed by the two storage controllers can be the same or different. For example, the two storage controllers can both manage multiple DCPMMs. For another example, one storage controller manages multiple DCPMMs, and the other storage controller manages a redundant array of independent disks (RAID) composed of multiple disks. The following introduces two management systems of the storage in the device to which the present application is applicable. In the embodiment of the present application, the first storage or the second storage can also be a storage of another type except for the DCPMM or the disk. The embodiment of the present application only takes the DCPMM or the disk as an example for description.

[0041] The first approach involves two memory controllers, each capable of managing multiple DCPMMs. These controllers can be memory controllers, capable of managing DCPMMs by reading, writing, and caching data within them. The memory controller can be a standalone module within the device or integrated into the processor, such as the central processing unit (CPU). For example, an integrated memory controller (IMC) can be integrated into the processor to manage DCOMMs, including initializing DCPMMs, performing data read / write operations, and caching.

[0042] This application only uses the memory controller as an example of an IMC. This application does not limit the specific form of other types of memory controllers, nor does it limit the memory controller to be integrated into the processor. Any controller that can manage the DCPMM can be used as the memory controller in this application.

[0043] like Figure 1 The diagram shown is a schematic of a memory management system architecture provided in an embodiment of this application. The memory management system is located in a device and includes a CPU 100. The various steps in the method embodiments provided in this application can be, but are not limited to, executed by the CPU 100.

[0044] CPU100 includes two IMCs, IMC110 and IMC120. Each IMC manages three channels; for example, IMC110 manages channels 111, 112, and 113, while IMC120 manages channels 121, 122, and 123. Each channel can support up to two memory slots, and each memory slot can accommodate one DCPMM or one dynamic random access memory (DRAM).

[0045] DCPMM is a special memory, which uses a general dual inline memory module (DIMM) package interface and can be used as non-volatile memory or volatile memory in different modes. For example, there are three different modes for DCPMM, including a memory mode (MM), an application mode (AD) and a mixed mode (MIX). In the memory mode, the DCPMM can be used as volatile memory; in the application mode, the DCPMM can be used as non-volatile memory and can realize no loss of power-off data; in the mixed mode, part of the storage space of the DCPMM can be used as non-volatile memory and part of the storage space can be used as volatile memory.

[0046] The memory slots in each channel of the IMC can be inserted with or without DCPMM. Due to the use constraints of the DCPMM, the DRAM is required to cooperate with the DCPMM application insertion method on the memory slot of the device. Currently, the DCPMM supports 15 specifications of insertion methods according to the capacity usage. For example, one DCPMM is inserted in each DIMM in the IMC, which is one insertion method; for another example, only one DCPMM is inserted in one DIMM in each channel of the IMC, which is also one insertion method.

[0047] Under this memory management system architecture, the storage space (referred to as the storage space managed by the IMC 110) formed by the plurality of DCPMMs managed by the IMC 110 and the storage space managed by the IMC 120 can be configured as a primary storage space and the storage space managed by the other IMC can be configured as a backup storage space. That is, one IMC is configured as the primary and the other IMC is configured as the backup, and the data read and write operation of the device occurs in the primary storage space, and the data backup in the primary storage space is saved in the backup storage space.

[0048] As a possible implementation, in order to ensure that the data in the primary storage space and the backup storage space can be evenly distributed in the DCPMMs under each channel, data balancing can be performed on the storage space managed by each IMC.

[0049] For example, for the storage space managed by an IMC, part or all of the storage space in the DCPMM under each channel of the IMC is taken out and mapped to the logical space managed by the IMC. When storing data to the storage space managed by the IMC, the IMC does not store the data in a certain DCPMM managed by the IMC, but allocates a storage address for the data from the logical space, so that the data can be evenly distributed in the DCPMMs under each channel.

[0050] The second type involves one storage controller managing multiple DCPMMs, which is an IMC; and another storage controller managing RAID, which is a RAID card.

[0051] like Figure 2 The diagram shown is a schematic of a memory management system architecture provided in an embodiment of this application. The memory management system is located in a device and includes a CPU 100. The CPU 100 may include two memory memory controllers (IMCs), namely IMC 110 and IMC 120. The structures of IMC 110 and IMC 120 are as follows... Figure 1 The system architecture shown is similar; please refer to the previous description for details, which will not be repeated here.

[0052] The memory management system architecture also includes a RAID card 200, which implements RAID functionality and configures a redundancy strategy for a RAID 210 consisting of multiple disks 211. In this embodiment, the RAID 210 can serve as a mirror unit for the storage space managed by IMC 110 and / or IMC 120. That is, the RAID 210 can be used to store data backups of the storage space managed by IMC 110 and / or IMC 120. Furthermore, the redundancy strategy configured by the RAID card 200 for the RAID 210 can be RAID 1, where RAID 1 allows simultaneous data read and write operations on two disks 211, ensuring data consistency between the two disks 211. The RAID card 200 can also configure other redundancy strategies for the RAID 210. This embodiment does not limit the redundancy strategy configured by the RAID card for RAID; RAID 1 is merely an example.

[0053] In this memory management system architecture, the storage space consisting of multiple DCPMMs managed by IMC110 and / or IMC120 (referred to as the storage space managed by IMC110 and / or IMC120) is configured as the primary storage space, and RAID210 is configured as the backup storage space. Data read and write operations of the device occur in the primary storage space, while data backups in the primary storage space are stored in the backup storage space.

[0054] Under this memory management system architecture, data balancing can also be performed on the storage space managed by each IMC. The method for achieving data balancing is the same as that for IMCs in the first memory management system architecture, as detailed above, and will not be repeated here.

[0055] The first memory management system uses half of the DCPMMs in the whole memory management system to form a backup storage space, and uses two IMCs, one as a main IMC and the other as a backup IMC. Since the device still reads or writes data from the DCPMM when performing data read / write, the data read / write efficiency of the whole memory management system is not affected, and the data read / write performance of the whole memory management system can be effectively ensured.

[0056] The second memory management system uses RAID as a mirror unit, and does not need to use part of the DCPMMs in the whole memory management system to form a backup storage space, thereby effectively saving costs.

[0057] The embodiments of the present application provide two memory management systems. When a device is initially started, the memory management system of the device can be configured to one of the two memory management systems based on the trigger of a user. The memory management system configuration method is described below.

[0058] As shown in Figure 3 FIG. 1, a memory management system configuration method provided by the embodiments of the present application includes the following steps.

[0059] Step 301: When a device is initially started, the mode of each DCPMM is configured by BIOS, such as AD, MIX or MM mode.

[0060] Step 302: After the IMC-DCPMM mirror patrol write-back function is started, the user is prompted to select a performance mode (corresponding to the first memory management system) or a cost mode (corresponding to the second memory management system).

[0061] The IMC-DCPMM mirror patrol write-back function refers to that after the device is started, the DCPMMs managed by the IMC 110 are detected for faults. In the case that a fault is detected in the DCPMMs managed by the IMC 110, the data in the backup storage space is used to perform data write-back to the DCPMMs that have faults.

[0062] It should be noted that the DCPMM detected in the IMC-DCPMM mirror patrol write-back function is the DCPMM managed by the master IMC, that is, the DCPMM forming the main storage space. In the embodiments of the present application, the storage space managed by the IMC 110 is taken as the main storage space as an example for description. When the storage space managed by the IMC 120 is taken as the main storage space, the DCPMM detected in the IMC-DCPMM mirror patrol write-back function is the DCPMM managed by the IMC 120; when the storage spaces managed by the IMC 110 and the IMC 120 are taken as the main storage space, the DCPMM detected in the IMC-DCPMM mirror patrol write-back function is the DCPMM managed by the IMC 110 and the IMC 120.

[0063] If the user selects the performance mode.

[0064] Step 303: For the IMC 110 and the IMC 120 in the CPU 100, the BIOS performs address mapping on the storage space managed by the IMC 110 and the storage space managed by the IMC 120.

[0065] When performing address mapping on the storage space formed by the DCPMM managed by the IMC 110 and the storage space formed by the DCPMM managed by the IMC 120, the storage space managed by the IMC 110 can be regarded as a block, then the block is sub-block divided, and an address is assigned to each sub-block.

[0066] Similarly, the storage space managed by the IMC 120 is regarded as a block, then the block is sub-block divided, and an address is assigned to each sub-block; a mapping relationship between the addresses of each sub-block under the IMC 110 and the addresses of each sub-block under the IMC 120 is established.

[0067] Step 304: The storage space managed by the IMC 110 is configured as the main storage space, and the storage space managed by the IMC 120 is configured as the standby storage space.

[0068] Step 305: If the storage space managed by the IMC 110 is successfully configured as the main storage space and the storage space managed by the IMC 120 is successfully configured as the standby storage space, the device is restarted.

[0069] If the storage space managed by the IMC 110 is not successfully configured as the main storage space and the storage space managed by the IMC 120 is not successfully configured as the standby storage space, the user is prompted that the configuration fails.

[0070] If the user selects the cost mode.

[0071] Step 306: The size of the non-volatile memory in the storage space managed by the IMC 110 is determined.

[0072] The BIOS can perform a capacity check on the storage media in each DCPMM by accessing the non-volatile memory (NVM) controller in each DCPMM, confirm the size of the non-volatile memory in each DCPMM, and then determine the size of the non-volatile memory in the storage space managed by the IMC 110.

[0073] Step 307: The RAID 200 card configures a redundancy strategy for the RAID 210, such as configuring RAID 1.

[0074] Step 308: Perform address mapping on the non-volatile memory in the storage space managed by the IMC 110 and the RAID 210 in the device.

[0075] In the embodiments of the present application, in order to ensure the reliability of the data in the non-volatile memory in the storage space managed by the IMC 110, the non-volatile memory in the storage space managed by the IMC 110 can be address mapped with the RAID 210. Of course, the storage space managed by the IMC 110 and the RAID 210 can also be address mapped, which can ensure the reliability of the data in the non-volatile memory in the storage space managed by the IMC 110 and the reliability of the data in the volatile memory in the storage space managed by the IMC 110. In the embodiments of the present application, only the case of address mapping the non-volatile memory in the storage space managed by the IMC 110 and the RAID 210 is taken as an example for description, and the case of address mapping the storage space managed by the IMC 110 and the RAID 210 is similar to the case of address mapping the non-volatile memory in the storage space managed by the IMC 110 and the RAID 210 in the device, which will not be described herein again.

[0076] It should be noted that the non-volatile memory in the storage space managed by the IMC 110 is taken as an example for description in the embodiments of the present application, and therefore the non-volatile memory in the storage space managed by the IMC 110 and the RAID 210 need to be address mapped in step 307.

[0077] If the non-volatile memory of the storage space managed by the IMC120 is configured as the primary storage space, address mapping is required between the non-volatile memory and RAID210 in the storage space managed by the IMC120. Similarly, if the non-volatile memory of the storage spaces managed by the IMC110 and IMC120 is configured as the primary storage space, address mapping is also required between the non-volatile memory and RAID210 in both IMC110 and IMC120. This can be configured according to the specific scenario. These two scenarios are similar to configuring the non-volatile memory of the storage space managed by the IMC110 as the primary storage space, and will not be elaborated upon here.

[0078] When mapping addresses between the non-volatile memory in the storage space managed by the IMC110 and RAID210, the non-volatile memory in the storage space managed by the IMC110 can be regarded as a block, and then this block can be divided into sub-blocks, and an address can be assigned to each sub-block.

[0079] Similarly, treat RAID210 as a block, then divide this block into sub-blocks and assign an address to each sub-block; establish a mapping relationship between the addresses of each sub-block under IMC110 and each sub-block of RAID210.

[0080] Step 309: Configure the non-volatile memory in the storage space managed by IMC110 as the primary storage space and the RAID210 as the secondary storage space.

[0081] Step 310: If successful, configure the non-volatile memory in the storage space managed by IMC110 as the primary storage space and the RAID210 as the secondary storage space. Otherwise, prompt the user that the configuration failed.

[0082] After configuring the memory management system, when a device performs a write operation in the primary memory space, the same write operation can be performed in the backup memory space, allowing the backup memory space to store a data backup of the primary memory space. Additionally, when the DCPMM managed by the IMC110 malfunctions, corresponding DCPMM fault handling methods can be used. The following sections describe the DCPMM fault handling methods under the two different memory management systems mentioned above:

[0083] The first type, based on Figure 1 The DCPMM fault handling method for the memory management system architecture shown.

[0084] like Figure 4 The above-described method, using IMC110 as the primary component and IMC120 as a backup, is an example of a DCPMM fault handling method provided in this application embodiment. The method includes:

[0085] Step 401: In the running of the device, detect each DCPMM managed by the IMC 110 in the device.

[0086] The DCPMM includes a non-volatile memory (NVM) controller and a storage medium. The storage medium in the DCPMM is used to store data. The NVM controller can actively monitor the storage medium in the DCPMM, determine the state of the storage medium in the DCPMM (such as the temperature of the storage medium, whether the storage medium has an uncorrectable error, etc.), and record in the failure monitoring information.

[0087] In the embodiments of the present application, whether each DCPMM fails can be determined by accessing the NVM controller in each DCPMM.

[0088] For any DCPMM managed by the IMC 110, if the NVM controller in the DCPMM is not successfully accessed, the NVM controller in the DCPMM fails, and it is determined that the DCPMM fails.

[0089] If the NVM controller is successfully accessed, the failure monitoring information recorded by the NVM controller can be accessed to determine the state of the storage medium in the DCPMM. For example, when the storage medium has an irreversible condition such as excessively high temperature, uncorrectable error, or electrical damage, it is determined that the storage medium fails, and it is further determined that the DCPMM fails.

[0090] Step 402: When it is detected that the DCPMM managed by the IMC 110 fails, switch the data read and write operation of the device to the storage space managed by the IMC 120. That is, downgrade the IMC 110 to a backup, and upgrade the IMC 120 to a master.

[0091] Step 403: Use the data in the storage space managed by the IMC 120 to perform data backwrite to the failed DCPMM.

[0092] Step 404: If the backwrite is successful, when the device is started next time, restore the master-backup relationship of the IMC 120 and the IMC 110, the IMC 110 is the master, and the IMC 120 is the backup.

[0093] Step 405: If the backwrite fails, send an alarm information to the user to prompt the DCPMM failure, and the user can also be notified to replace the failed DCPMM.

[0094] The user turns off the power of the device, replaces the failed DCPMM, and when the device is powered on again, each component (such as a processor, a memory, etc.) in the device is initialized, after the initialization is completed, the data in the storage space managed by the IMC 120 is used again to perform data write-back to the newly replaced DCPMM, and if the data write-back is successful, the master-slave relationship between the IMC 120 and the IMC 110 is restored.

[0095] It should be noted that even if the data write-back fails in step 405, the master-slave relationship between the IMC 120 and the IMC 110 is not unbundled, so that the address mapping between the storage space managed by the IMC 120 and the storage space managed by the IMC 110 is still maintained, and the backup data of the data stored in the DCPMM managed by the IMC 110, except for the failed DCPMM, can still be saved in the storage space managed by the IMC 120.

[0096] Secondly, a DCPMM failure processing method based on Figure 2 the memory management system architecture shown in the figure.

[0097] As Figure 5 described, a DCPMM failure processing method provided by an embodiment of the present application includes:

[0098] Step 501: During the operation of the device, each DCPMM in the device is detected. The same as step 401, for details, please refer to the related description of step 401, which will not be repeated here.

[0099] Step 502: When it is detected that the DCPMM managed by the IMC 110 fails, the data read-write operation of the device is switched to the RAID 210. That is, the RAID 210 is upgraded to the main storage space, and the storage space managed by the IMC 110 is used as the backup storage space.

[0100] Step 503: The data stored in the RAID is used to perform data write-back to the DCPMM managed by the IMC 110.

[0101] For example, the data stored in the RAID and the data in the storage space managed by the IMC 110 can be compared, and for the data inconsistent between the RAID and the storage space managed by the IMC 110, the inconsistent data in the storage space managed by the IMC 110 is erased, and the data stored in the RAID is used to perform data overwrite.

[0102] Step 504: If the write-back is successful, when the device is started next time, the master-slave relationship between the IMC 110 and the RAID 210 is restored, the IMC 110 is the master, and the RAID 210 is the backup.

[0103] Step 505: If the data write-back fails, an alarm information is sent to the user to prompt the DCPMM failure, and the user can also be informed to replace the failed DCPMM.

[0104] The user turns off the power of the device, replaces the failed DCPMM, and when the device is powered on again, initializes each component in the device. After the initialization is completed, the data in the RAID 210 is used again to perform data write-back on the newly replaced DCPMM. If the data write-back succeeds, the master-slave relationship between the IMC 110 and the RAID 210 is restored.

[0105] It should be noted that even if the data write-back fails in step 505, the master-slave relationship between the IMC 120 and the RAID 210 is not unbundled, so that the address mapping between the storage space managed by the RAID 210 and the storage space managed by the IMC 110 is still maintained. In the DCPMM managed by the IMC 110, the backup data of the data stored in the remaining DCPMMs except the failed DCPMM can still be saved in the RAID 210.

[0106] Based on the same inventive concept as the method embodiment, the embodiment of the present application also provides a fault processing apparatus for executing the method shown in Figure 3 、 4 and 5, and the related features can be referred to the above method embodiment, which will not be described here again. As shown in Figure 6 , the fault processing apparatus 600 includes a detection unit 601 and a switching unit 602.

[0107] The detection unit 601 is configured to detect that a first storage managed by a first storage controller fails.

[0108] The switching unit 602 is configured to, when the first storage managed by the first storage controller fails, transfer the data read-write operation of the device from a storage space formed by the first storage managed by the first storage controller to a storage space formed by a second storage managed by a second storage controller.

[0109] The fault processing apparatus 600 further includes a write-back unit 603, which can use the data in the second storage managed by the second storage controller to perform data write-back on the failed data in the first storage managed by the first storage controller. If the write-back succeeds, after the device is powered on next time, the read-write operation of the device is switched to the storage space formed by the first storage managed by the first storage controller. If the write-back fails, an alarm information is sent, which is used to indicate that the first storage fails.

[0110] The fault processing apparatus 600 further comprises a configuration unit 604, which can map the storage space of the first storage managed by the first storage controller as the logical space of the first storage controller, and can receive an instruction sent by a user before the detection unit detects that the first storage managed by the first storage controller fails, the instruction being used to indicate to configure a first mode or a second mode, the first mode indicating that the first storage and the second storage are DCPMMs, and the second mode indicating that the first storage is a DCPMM and the second storage is a disk; and the configuration unit 604 can configure the first mode or the second mode according to the instruction.

[0111] The above fault processing apparatus 600 can be used to execute the method shown in Figure 3 、 4 and 5, wherein the detection unit 601 can execute the method of detecting that the DCPMM managed by the IMC 110 fails in steps 401 and 402 in the method embodiment shown in Figure 4 , and can execute the method of detecting that the DCPMM managed by the IMC 110 fails in steps 501 and 502 in the method embodiment shown in Figure 5 . The switching unit 602 can execute the switching method of the data read operation in step 402 in the method embodiment shown in Figure 4 , and can execute the switching method of the data read operation in step 502 in the method embodiment shown in Figure 5 . The write-back unit 603 can execute steps 403-405 in the method embodiment shown in Figure 4 , and can execute steps 503-505 in the method embodiment shown in Figure 5 . The configuration unit 604 can execute steps 303-310 in the method embodiment shown in Figure 3 .

[0112] It should be noted that the division of the units in the embodiments of the present application is illustrative, and is only a logical function division, and another division mode can be used in actual implementation. The functional units in the embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0113] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0114] like Figure 7 The device 700 shown includes at least one processing unit 710, a first memory 720 and a second memory 730, and optionally, may also include a communication interface 740.

[0115] The processing unit 710 includes a first memory controller and a second memory controller, and may also include one or more general-purpose processors, such as CPU 100, or a combination of CPU 100 and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. This application does not limit the number or type of processors included in the processing unit 710; any processor capable of calling computer program instructions from memory (such as the first memory 720, the second memory 730, or other memories) can constitute the processing unit 710.

[0116] The specific connection medium between the processing unit 710 and the memory 720 is not limited in the embodiments of this application.

[0117] In such Figure 7The device further includes a communication interface 730, through which the processing unit 710 can perform data transmission when communicating with other devices.

[0118] When the device adopts the form shown in FIG. 7, Figure 7 When the device adopts the form shown in FIG. 7, Figure 7 The processing unit 710 in the device can invoke the computer program instructions stored in the memory (such as the first memory 720, the second memory 730, or other memories) to make the device 700 perform the methods shown in FIGS. 1-5. Figure 3 、 4 and 5.

[0119] Specifically, Figure 7 The functions / implementation processes of the detection unit, the switching unit, the write-back unit, and the configuration unit in the device can be implemented by the processing unit 710 invoking the computer program instructions stored in the memory. Figure 7 The functions / implementation processes of the detection unit, the switching unit, the write-back unit, and the configuration unit in the device can be implemented by the processing unit 710 invoking the computer program instructions stored in the memory.

[0120] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0121] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the computer or other programmable data processing devices produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams.

[0122] These computer program instructions can also be stored in a computer readable memory capable of guiding the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams.

[0123] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide a process for implementing the functions specified in the flowchart Figure 1 one flow or multiple flows and / or one block or multiple blocks. Figure 1 Figure 1 the steps of the functions specified in the flowchart or multiple flows and / or one block or multiple blocks.

[0124] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A server, characterized by The server comprises a BIOS, a first storage controller and a second storage controller, the BIOS is connected with the first storage controller and the second storage controller, the server configures the first storage controller and the second storage controller through the BIOS, the first storage controller manages a first storage, and the second storage controller manages a second storage. The first storage and the second storage are data center persistent memory (DCPMM), when the first storage managed by the first storage controller fails, the BIOS uses data in the second storage managed by the second storage controller to perform data write-back on the failed data in the first storage managed by the first storage controller. Alternatively, the first storage is DCPMM, and the second storage is a plurality of disks, when the first storage managed by the first storage controller fails, the BIOS sends failure information to the OS of the server, and the OS-side application uses data in the second storage managed by the second storage controller to perform data write-back on the failed data in the first storage managed by the first storage controller, and returns a message to the BIOS after the write-back is successful.

2. The server of claim 1, wherein, The storage space formed by the second storage managed by the second storage controller is a backup space of the storage space of the first storage managed by the first storage controller, and the storage space formed by the second storage managed by the second storage controller does not overlap with the storage space of the first storage managed by the first storage controller.

3. The server of claim 1 or 2, wherein, The first storage and the second storage are data center persistent memory (DCPMM), and the first storage controller and the second storage controller are memory controllers.

4. The server of claim 1 or 2, wherein, The first storage is data center persistent memory (DCPMM), the second storage is a plurality of disks, the first storage controller is a memory controller, and the second storage controller is a redundant array of independent disks (RAID) card.

5. The server of claim 1 or 2, wherein, The data in the storage space of the first storage managed by the first storage controller is distributed in the DCPMM under a plurality of channels of the first storage controller.

6. The server of claim 1 or 2, wherein, The server configures the first storage controller and the second storage controller in a first mode or a second mode through the BIOS, the first mode indicates that the first storage and the second storage are DCPMM, and the second mode indicates that the first storage is DCPMM and the second storage is a disk.

7. The server of claim 1 or 2, wherein, The first storage and the second storage are DCPMM, and the server performs address mapping on the storage space formed by the DCPMM managed by the first storage controller and the storage space formed by the DCPMM managed by the second storage controller through the BIOS.

8. The server of claim 1 or 2, wherein, The first memory is a DCPMM, the second memory is a plurality of disks, the second storage controller is a RAID card, the plurality of disks constitute a RAID, the RAID card configures a redundancy strategy for the RAID, and the server maps addresses of nonvolatile flash memory in the DCPMM managed by the first storage controller and the RAID managed by the second storage controller through the BIOS.

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