A loop current method-based power electronic system cluster simulation implementation method

Abstract

The application discloses a kind of based on loop current method's power electronic system cluster simulation implementation method, it is related to power electronic technical field.The application includes: based on loop current method's power electronic model cluster distribution initialization method and cluster computing scheduling method, wherein model distribution initialization method will large-scale power electronic model be distributed to each computing node according to the local circuit after decoupling of loop current method and complete the initialization of local circuit model simulation on each node, wherein cluster computing scheduling method realizes the multi-level parallel computing scheduling and synchronous process of main node to computing node in cluster.The application is suitable for large-scale power electronic simulation based on supercomputer or high-performance computer cluster, fully utilizes the advantage of large memory capacity of computer cluster to expand the scale of power electronic model simulation, fully utilizes the advantage of many processor core quantity of computer cluster to improve the efficiency of power electronic model simulation.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of power electronics, and particularly relates to a simulation implementation method for a power electronic system cluster based on a loop current method BACKGROUND

[0002] With the development and popularization of power electronic technology, the scale of a power electronic system is increasingly large. For a power system with a complex topology structure, great control difficulty and a large number of power electronic modules, it is of great significance to use a simulation tool to analyze a model, to ensure unit reliability and system stability, and is an effective means to ensure project continuous promotion. Compared with traditional power grid operation, the operation mechanism of a power electronic system is changed. The precision of traditional electromechanical transient simulation cannot meet the precision requirement of electromagnetic transient simulation in a large-scale power electronic system. Traditional simulation methods based on the overall state of a system or an overall admittance / impedance matrix have the disadvantages of slow simulation speed and large memory occupation, and cannot meet the simulation scale and simulation efficiency requirement in a large-scale power electronic system. SUMMARY

[0003] The application aims to provide a simulation implementation method for a power electronic system cluster based on a loop current method, which can make full use of the large memory capacity of a computer cluster to expand the simulation scale of a power electronic model, and make full use of the large number of processor cores of a computer cluster to improve the simulation efficiency of a power electronic model.

[0004] To achieve the above object, the application provides the following technical scheme: a simulation implementation method for a power electronic system cluster based on a loop current method, comprising the following steps:

[0005] Obtaining the total number n of unit circuits and calculating the memory capacity m required by the circuit part and the controller part in a model region i i The memory space occupied by the region i is calculated according to the following formula:

[0006]

[0007] Wherein m i is the total number of bytes required by the region i, r is the number of loop currents, b i is the number of unit circuits in the region, d i is the number of devices in the unit circuit, n i is the number of nodes in the unit circuit, s k is the number of states of the kth device in the unit circuit, e k is the number of electrical quantity attributes such as voltage and current of the kth device in the unit circuit (k=1, 2, …, d i ), c i defines the memory space occupied by the control system in the unit circuit, wherein The memory space occupied by the unit circuit admittance matrix and impedance matrix set is calculated, and since each unit circuit in a region shares a set of admittance matrix and impedance matrix, it is calculated only once in a region, 2b i n i The memory space occupied by the unit circuit voltage vector X j and current vector H j is described, b i The memory space occupied by the loop voltage vector E j is described, r p The memory space occupied by the node loop voltage vector and E i is described, b 2 The memory space occupied by the loop impedance Z j is described, r 2 The memory space occupied by the node loop voltage impedance and z p is described, b i n i The memory space occupied by the loop current selection matrix P j is described, b i Σe k The memory space occupied by each device to save its own voltage and current state is described, sizeof(double) describes the number of bytes occupied by a double type floating point number in different architectures of supercomputers, high-performance computer clusters;

[0008] A computer cluster is specified, in which one machine is the master node and the remaining N machines are the computing nodes, and the total memory capacity Σm i of all regions on each computing node is calculated, the memory capacity Σm i required by a single node is greater than the node capacity m p , and the part of the region of the node that needs to be adjusted to other nodes is adjusted to other nodes to meet the memory capacity Σm i required by a single node p constraint, and the adjusted Σ(n p -n / N) 2 is minimized;

[0009] According to the calculated memory space occupied by each region and the relationship between the master node and the computing nodes, the region unit circuit structure and device state in the entire simulation model are then evenly distributed to each computing node according to the number of region unit circuits on the computing nodes, while ensuring that all unit circuits in a region are distributed to the same computing node;

[0010] Each computing node calculates the admittance matrix of the unit circuit in region i under all device state combinations k j ​ and impedance matrix Among them, the same device state combination k j The lower admittance matrix and the impedance matrix satisfy the following relationship

[0011] Update the current simulation time record, allocate the current simulation time and the system-level control information obtained at the end of the previous simulation step to each computing node, and initiate a new parallel computing step for computing nodes.

[0012] By substituting the latest simulation time t into the voltage source, current source, and other components, the current vector H in each unit circuit at the current moment is calculated. j The value;

[0013] The latest control system switching signals from the master node are fed into the devices. Based on the current circuit state and control signals, the state, impedance, cutoff voltage, and other parameters of each device are changed. The unit circuit state index k is then calculated based on the state of each device. j ;

[0014] Each unit circuit is based on state index k j Read the admittance from the pre-computed admittance matrix set Read impedance from the pre-computed impedance matrix set Calculate the loop voltage and loop impedance of the unit circuit using the following formulas:

[0015]

[0016] In the compute node, a single thread is used to calculate the loop voltage and E on the compute node. p and loop impedance and Z p ;

[0017] The master node bases its data on the loop voltage and E on each compute node. p Calculate the sum of the loop voltages E at all nodes;

[0018] The master node is based on the loop impedance and Z on each compute node. p Calculate the sum of loop impedances Z at all nodes, and send the results from each node to the master node via the communication model. Further calculate the model loop admittance A, using the following formula:

[0019] A = Z -1 ;

[0020] The master node calculates the loop current R of the entire simulation model based on the obtained loop admittance A and the sum of the loop voltages E on all computational nodes, and synchronizes the loop current R to all computational nodes. The formula for calculating the loop current R is:

[0021] R = AE;

[0022] Based on the nodal voltage method and the node description equations of each unit circuit, the nodal voltages and device currents of multiple unit circuits within a node are calculated in parallel. This realizes the solution process of the entire circuit under the simulation step size. For each unit circuit, its nodal voltage X j The formula for vector calculation is as follows:

[0023]

[0024] Based on the device model and node voltage values, calculate the state of each device and detect whether a device state change has occurred in the unit circuit. If a unit circuit state change has occurred, set the device state to the latest state and record it in the unit state flag bit.

[0025] The node status flag S is obtained by statistically calculating the status flags of all circuits on the node. p If any unit circuit's status flag bit changes, then the node device status flag bit S of this node will be updated. p Record as a change;

[0026] The master node collects statistics from the device status flags S on the compute nodes. p If a device state change occurs at any node, it is considered that a device state change event has occurred within the current simulation step, and the device state change processing algorithm is called. Typical device state changes include diode cut-off / conduction and saturated inductor entering / exiting the nonlinear region.

[0027] If no change in device state is detected in the master node model state detection, the compute node collects the current electrical quantity values ​​in each unit circuit and feeds them back to the unit circuit control system for control. Based on the control results, the compute node modifies the device state in the unit circuit. Then, the compute node sends the feedback signal and control signal results to the master node through the communication model, and the master node performs a multi-node progress synchronization.

[0028] Based on the feedback and control signals from each computing node, the master node executes a system-level control system to achieve the interaction of control system signals between different unit circuits and the coordinated control between different control systems.

[0029] After this step-size simulation is completed, verify whether the simulation time t has reached the simulation set time T. If the simulation time has reached the set time, exit the model simulation calculation stage, export the simulation data and perform subsequent processing.

[0030] Furthermore, the memory capacity required for region i includes the admittance matrix of all devices in all state combinations within the region's unit circuits. Set, impedance matrix of all devices in all state combinations of a regional unit circuit. Set, the voltage vector X of all unit circuits within the region. j The current vector H of all unit circuits within the region j The loop voltage vector E of the unit circuit within the region j The loop impedance Z of each unit circuit within the region j Calculate the node loop voltage vector and E p Calculate the node loop impedance and Z p And the memory space occupied by each control system device.

[0031] The present invention has at least the following beneficial effects:

[0032] 1) This invention fully utilizes the advantage of the large memory capacity of computer cluster systems, and places different parts of the large-scale power electronics model on different computing nodes after decoupling, effectively expanding the simulation scale of power electronics systems.

[0033] 2) This invention fully utilizes the advantage of the large number of processors in a computer cluster system, decouples the large-scale power electronics model, and performs calculations on different parts of the model on different computing nodes, effectively improving the simulation calculation efficiency of power electronics systems.

[0034] 3) By applying the decoupling principle of the loop current method to the computer cluster architecture, different circuit regions in the simulation model will not be accessed across computing nodes, effectively improving the computing efficiency of computing nodes during parallel computing.

[0035] 4) Fully utilize the parallelizability of the loop current method and combine it with the scheduling principle of computer cluster system to design a computer cluster scheduling method suitable for decoupled parallel computing of the loop current method, so as to realize the parallelization of large-scale power electronics simulation computing.

[0036] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0037] Figure 1 This describes the star topology connection relationship between the master node and the computing nodes in this invention.

[0038] Figure 2 This invention relates to the principle of multi-core scheduling for parallel computing nodes;

[0039] Figure 3 This describes the basic principles and main processes of the loop circuit method in computer cluster systems.

[0040] Figure 4 This is the process of scheduling computing node clusters during the simulation calculation of this invention;

[0041] Figure 5 This is a schematic diagram of the processor and memory distribution within the cluster of this invention. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0043] Please see Figures 1-5 This invention relates to a method for simulating power electronic system clusters based on the loop current method. This method is applicable to supercomputer and high-performance computer cluster architectures. In this invention, the high-performance computer cluster is divided into two parts: one node acts as the master node to allocate models and invoke the system's parallel computing process, while the remaining nodes act as computing nodes to participate in the parallel phase calculation initiated by the master node. Each node can use either a non-uniform memory access (NUMA) architecture or a uniform memory access (UMA) architecture to achieve interconnection between multiple processors and multiple memory regions. The master node and computing nodes communicate with each other using underlying hardware communication technologies, including but not limited to Ethernet and unlimited bandwidth technologies. To reduce communication latency, supercomputers and high-performance computer clusters employ various working modes, including but not limited to communication via network protocol stacks and memory pass-through interconnection without network protocol stacks. The master node and computing nodes communicate with each other using communication models, including but not limited to MPI and sockets, to achieve data interaction and progress synchronization.

[0044] The loop current method decouples a group of unit circuits with the same circuit structure and connection method into a region. A power electronics simulation model consists of multiple regions, each containing multiple unit circuits with the same circuit structure. According to the basic principles of circuit analysis and node analysis, different unit circuits within the same region share the admittance matrix and impedance matrix under the same device state. Therefore, regions with the same circuit structure can be assigned to the same computation node, and the admittance matrix of the unit circuit under all device state combinations can be pre-calculated. and impedance matrix Because the admittance matrices and their inverse matrices within each unit circuit are pre-calculated and shared within the region, time-consuming matrix inversion calculations are not required during the calculation of loop currents and internal node voltages, greatly improving simulation speed. Before allocating the simulation model to the computing nodes, the memory capacity required for this region needs to be pre-calculated via S1, and allocated according to the actual capacity of each node in the cluster to avoid memory shortage failures during operation. The formula for calculating the memory space occupied by region i is shown below.

[0045]

[0046] Where m i This represents the total number of bytes required for region i, including memory occupied by the circuit and memory occupied by the control system. In conventional simulation models, the memory space occupied by circuit parameters such as the pre-calculated impedance matrix, admittance matrix, voltage vector, and current vector used to calculate the circuit is significantly larger than the memory space occupied by the control system. Here, r is the number of loop currents, and b... i It is the number of unit circuits in the region, d i n is the number of components within a unit circuit. i It is the number of nodes in the unit circuit, s k It is the number of states of the k-th device in the unit circuit, e k It is the quantity of electrical quantity attributes such as voltage and current of the k-th device in the unit circuit (k = 1, 2, ..., d). i ), c i The memory space occupied by the control system within the unit circuit is defined, where The memory space occupied by the set of admittance and impedance matrices for each unit circuit was calculated. Since all unit circuits within a region share the same set of admittance and impedance matrices, the calculation is performed only once within a region. (2b) i n i It describes the voltage vector X of the unit circuit. j and current vector H j Memory space occupied, b i r describes the loop voltage vector E j The memory space occupied, r describes the node loop voltage vector and E p The key is the amount of memory occupied, b i r 2 This describes the loop impedance Z. j Memory space occupied, r 2 This describes the node loop voltage impedance and z-axis. p Memory space occupied, b i n i r describes the loop current selection matrix P. j Memory space occupied, b i Σek This describes the memory space occupied by each device to store its own voltage and current states, while sizeof(double) describes the number of bytes occupied by a double-type floating-point number in supercomputers and high-performance computer clusters with different architectures.

[0047] In a computer cluster, one computer is selected as the master node, and the remaining N computers are designated as compute nodes. It is essential to ensure that the master node and all compute nodes are directly connected. Logically, the master node and compute nodes form a star topology centered on it. The actual hardware topology can utilize Ethernet, fiber optic networks, or similar devices. After calculating the memory space required for each region and the relationship between the master node and compute nodes using the above steps, the entire simulation model is distributed as evenly as possible across the compute nodes based on the number of unit circuits in each region. Simultaneously, it is crucial to ensure that all unit circuits within a region are allocated to the same compute node to avoid cross-node memory access. A feasible allocation method is as follows: the ratio of the number of unit circuits (n) in the computational model to the number of compute nodes (N) is n / N. Regions containing more than n / N unit circuits are allocated to a single compute node. Regions containing less than n / N unit circuits are allocated to the same compute node across multiple regions, ensuring that the total memory required on that compute node is Σm. i Less than the node content capacity m p Under the given conditions, the minimization constraint is satisfied:

[0048]

[0049] After completing the above optimization constraint S2, a one-way mapping relationship i→p between region number i and computing node p is formed, which serves as the basis for subsequent initialization allocation.

[0050] In the appendix Figure 3 In simulation S3, based on the communication model, the master node serializes the power electronics simulation model according to the mapping relationship i→p and distributes it to each computing node. The computing nodes then reconstruct the original model information and complete the model initialization. After obtaining the corresponding region configuration information, each computing node enumerates the state combinations k of all devices in the unit circuit within that region. j To form the admittance matrix And calculate its corresponding inverse matrix. After forming the impedance matrix and completing the initialization phase, the model simulation calculation phase begins. The memory distribution of the computer cluster, which is allocated and initialized based on the loop current method, is shown in the simplified diagram. Each computing node stores the admittance matrix and impedance matrix of a part of the circuit under all device state combinations. When performing circuit calculations, the voltage and current parameter calculation process of the circuit is allocated to the same node. Then, this computing node can use all the data stored in the node's memory to complete the unit circuit calculation without memory access between other nodes, thus improving the calculation efficiency.

[0051] Appendix Figure 4 This refers to the model simulation calculation phase workflow. Each simulation calculation step involves a top-down workflow scheduling of the computer cluster. During parallel computing in the simulation scheduling process, when the number of unit circuits to be calculated on each computing node exceeds the number of cores, to improve core utilization efficiency and avoid over-scheduling, one feasible node scheduling method is shown in the appendix. Figure 2 As shown, the unit circuits to be calculated are arranged into a matrix queue, and the processor cores to be calculated are arranged into a calculation queue. The idle cores in the calculation queue take the matrix parameters to be calculated from the matrix queue in turn, perform the calculation, and switch to the calculation state. After the core completes the calculation of a unit circuit, it switches back to the idle state and enters the calculation queue for sorting.

[0052] S4 is performed on the master node, updating the current simulation time record, distributing the current simulation time and the system-level control information obtained at the end of the previous simulation step to each computing node, and initiating a new parallel computing step for the computing nodes to calculate the sum of the loop voltages E on each node. p The sum of the loop impedances Z p .

[0053] S5-S8 are all performed at the computation node. In S5, the latest simulation time t is used to calculate the current vector H in each unit circuit at the current moment by substituting the voltage source, current source and other components. j The value of is used to input the latest control system switching signals from S6 into the device. Based on the current circuit state and control signals, the state, impedance, cutoff voltage, and other parameters of each device are changed. The unit circuit state index k is then calculated based on the state of each device. j In S7, each unit circuit is based on the state index k. j Read the admittance from the pre-computed admittance matrix set Read impedance from the pre-computed impedance matrix set Calculate the loop voltage and loop impedance of the unit circuit using the following formulas:

[0054]

[0055] S5-S7 employs additional nodes in the computing nodes. Figure 2 The queue computation method shown employs multi-core computation. After completing the computation process, S8 uses a single thread within the computation node to process the loop voltage and E on the computation node. p and loop impedance and Z p

[0056]

[0057] The master node performs a compute node synchronization phase after S8 ends and before S9 begins. Due to differences in the number of unit nodes in different regions and individual processor differences, the time taken for different compute nodes to complete S8 computations varies, ensuring that the sum of the loop voltages E in each compute node is equal when S9 begins. p The sum of the loop impedances Z p All calculations have been completed, and the results from each calculation node have been sent to the master node via the communication model. The model loop admittance A and loop current R are then calculated using the following formulas:

[0058]

[0059] As attached Figure 4 As shown, the two steps of calculating the loop voltage E and the loop impedance A in the master node are independent and can be performed in parallel in the master node. The progress of S9 and S10 is synchronized before S11 to ensure that the loop current R calculation, loop admittance A and loop voltage E are the latest calculated values ​​within the current simulation step.

[0060] At the end of S11, the global loop current R is synchronized to each computing node through the communication model, and a cluster parallel computing scheduling is initiated to calculate the node voltage, current, and device state of the unit circuit on all computing nodes. For the unit circuit, its node voltage X j The formula for vector calculation is as follows:

[0061]

[0062] The calculation of unit circuit S12 uses the attached... Figure 2 The multi-core scheduling method shown calculates the state of each device based on the device model and node voltage values, and detects whether a device state change has occurred in the unit circuit. If a unit circuit state change has occurred, the device state is set to the latest state and recorded in the unit state flag bit. Since there are several regions and several unit circuits on a computing node, after all unit circuits on the node have completed device state detection, the node performs S13 once, and counts the state flag bits of all circuits on the node to obtain the node state flag bit S. p If any unit circuit's status flag bit changes, then the node device status flag bit S of this node will be updated.p This is recorded as a change. At the end of S13, each compute node will change its node status flag S. p The process is synchronized to the master node, which then performs a progress synchronization of the compute nodes to ensure that the node status flags obtained on each node are the values ​​from the latest step size calculation.

[0063] In S14, the master node counts the device status flags S from the compute nodes. p If a device state change occurs at any node, it is considered a device state change event within the current simulation step, and the device state change handling algorithm is invoked. Typical device state changes include, but are not limited to, diode cutoff / conduction, and saturated inductor entering / leaving the nonlinear region. Several existing power electronic state change handling algorithms can be used for this purpose. One feasible method is to keep the latest calculated device state unchanged, and the master node keeps the simulation time t constant, jumping between S4 and S5 to re-perform the simulation calculation.

[0064] If no device state change is detected in the S14 master node model state detection, the process proceeds to the S16-S17 control system execution process. Since the computational load of the control system is significantly less than that of the power electronic circuit, the control system can be entirely calculated by the master node and synchronized to all computing nodes. Alternatively, the control systems of their respective circuits can be calculated on the computing nodes while the global control system is calculated on the master node. Figure 3 and attached Figure 4 The latter will be used as an example for explanation. S14 detects no change in device state and initiates a parallel computation of the computing node cluster, collecting the current electrical quantities in each unit circuit and feeding them back to the unit circuit control system for control. Based on the control results, the device states within the unit circuits are modified. The unit circuit control systems are not coupled to each other and can be used in conjunction with other systems. Figure 2 The multi-core circuit method shown is used. After the computing node completes the control result of the unit circuit in S16, it sends the feedback signal and control signal result to the master node through the communication model. The master node performs a multi-node progress synchronization and completes the calculation and transmission process of the control system on all computing nodes before the start of S17.

[0065] In S17, the master node executes a system-level control system based on data fed back from each computing node. This system-level control system enables the interaction of control system signals between different unit circuits, as well as coordinated control between different control systems. The addition of the system-level control system provides large-scale power electronic models with the capability for multi-system coordinated control interaction simulation and verification. It can verify the interaction coupling mechanism and operational stability between different power electronic systems and connect different power system architectures.

[0066] After the step-size simulation ends, S18 verifies whether the simulation time t has reached the simulation set time T. If the simulation time has reached the set time, it exits the model simulation calculation stage, exports the simulation data, and performs subsequent processing.

[0067] Traditional power electronics simulations based on the overall circuit method cannot utilize supercomputer architectures or high-performance computer clusters for parallel computation due to the coupling relationships between various nodes and devices. However, this invention employs the loop current method to decouple the power electronics model, equating the coupling relationships between different nodes and regions to loop currents. This decoupling of different regions allows for partial parallelization of unit circuits within different regions. Based on this principle, this invention implements a cluster-based large-scale power electronic circuit simulation method. The simulation implementation method in this invention consists of two parts: a cluster allocation and initialization method and a cluster computation scheduling method. The allocation and initialization algorithms solve the problems of simulation model segmentation and matrix initialization, fully utilizing the large memory capacity of the computer cluster. The pre-generated admittance and impedance matrices are distributed across various computing nodes. During cluster computation, computing nodes access the locally stored region matrix model to calculate the loop voltage, loop impedance, node voltage, and device current within the region. This achieves local integration of the processor core and memory, improving cluster computation efficiency.

[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0069] For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances. When an element is referred to as being "assembled on," "mounted on," "fixed to," or "set on" another element, it may be directly on the other element or there may be an intermediate element present. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible embodiments.

[0070] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0071] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

Claims

1. A method for simulating power electronic system clusters based on the loop current method, characterized in that, Includes the following steps: Obtain the total number of unit circuits n And calculate a single region of the simulation model. i Memory capacity required for internal circuitry and controller sections m i ,area i The formula for calculating the occupied memory space is as follows: in It is a region Total number of bytes required It is the number of loop currents, describing the vector sum of node loop voltages. Memory space occupied; It is the number of unit circuits in the area. It refers to the number of components within a single circuit unit. It refers to the number of nodes in a unit circuit. It is the first in the unit circuit Number of device states It is the first in the unit circuit The number of electrical quantity attributes such as voltage and current of each device. , The memory space occupied by the control system within the unit circuit is defined, where The memory space occupied by the set of admittance and impedance matrices for each unit circuit was calculated. Since all unit circuits within a region share the same set of admittance and impedance matrices, the calculation is performed only once within that region. It describes the voltage vector of the unit circuit. and current vector Memory space occupied, It describes the loop voltage vector. Memory space occupied, It describes the loop impedance. Memory space occupied, This describes the node loop voltage impedance and Memory space occupied This describes the loop current selection matrix. Memory space occupied This describes the memory space occupied by each device to store its own voltage and current states, sizeof( double This describes the number of bytes occupied by a double-type floating-point number in supercomputers and high-performance computer clusters with different architectures. Designate one machine in the computer cluster as the master node, and the remaining machines as master nodes. Each machine is a compute node; calculate the total memory capacity of all regions on each compute node. The memory capacity required on a single node Greater than node capacity Part of the node's memory area was moved to other nodes to meet the memory requirements of those nodes. Constraints, and after adjustment Minimum; Based on the calculated memory space occupied by each region and the relationship between the master node and the compute nodes, the regional unit circuit structure and device state in the entire simulation model are evenly distributed to each compute node according to the number of regional unit circuits on the compute nodes, while ensuring that all unit circuits in a region are assigned to the same compute node; Each computing node calculates the region based on the assigned region's unit circuit structure and device state. i The internal unit circuits combine all device states. Admittance matrix under and impedance matrix Among them, the same device state combination The lower admittance matrix and the impedance matrix satisfy the following relationship ; Update the current simulation time record, allocate the current simulation time and the system-level control information obtained at the end of the previous simulation step to each computing node, and initiate a new parallel computing step for the computing nodes; The latest simulation time t By substituting these values ​​into components such as voltage and current sources, the current vector in each unit circuit at the current moment can be calculated. The value; The latest control system switching signals from the master node are fed into the devices. Based on the current circuit state and control signals, the state, impedance, cutoff voltage, and other parameters of each device are changed. The unit circuit state index is then calculated based on the state of each device. ; Each unit circuit is indexed according to its state. Read the admittance from the pre-computed admittance matrix set Impedance is read from the pre-computed impedance matrix set. The loop voltage and loop impedance of the unit circuit are calculated according to the following formulas: ; In the compute node, a single thread is used to calculate the loop voltage on the compute node and and loop impedance and ; The master node calculates the loop voltage on each compute node and Calculate the sum of the loop voltages at all nodes. E ; The master node is based on the loop impedance on each compute node and Calculate the sum of the loop impedances at all nodes. Z The results from each computing node are then sent to the master node via a communication model to further calculate the model loop admittance. A The calculation formula is as follows: ； The master node based on the obtained loop admittance A The sum of loop voltages on all compute nodes E Calculate the loop current of the entire simulation model. R and the loop current R Synchronize to all computing nodes, loop current R The calculation formula is: ； Based on the nodal voltage method and the node description equations of each unit circuit, the nodal voltages and device currents of multiple unit circuits within a node are calculated in parallel. This realizes the solution process of the entire circuit under the simulation step size. For each unit circuit, its nodal voltage... X j The formula for vector calculation is as follows: Based on the device model and node voltage values, the state of each device is calculated, and it is detected whether a device state change has occurred in the unit circuit. If a unit circuit state change has occurred, the device state is set to the latest state, and a record is made in the unit state flag bit. The node status flags are obtained by statistically calculating the status flags of all circuits on the node. S p If any unit circuit's status flag bit changes, then the node device status flag bit of this node will be updated. S p Record as a change; The master node collects statistics on device status flags from the compute nodes. S p If a device state change occurs at any node, it is considered that a device state change event has occurred within the current simulation step, and the device state change handling algorithm is invoked. Typical device state changes include diode cutoff / conduction and saturated inductor entering / exiting the nonlinear region. If no change in device state is detected in the master node model state detection, the compute node collects the current electrical quantity values ​​in each unit circuit and feeds them back to the unit circuit control system for control. Based on the control results, the compute node modifies the device state in the unit circuit. Then, the compute node sends the feedback signal and control signal results to the master node through the communication model, and the master node performs a multi-node progress synchronization. Based on the feedback and control signals from each computing node, the master node executes a system-level control system to achieve the interaction of control system signals between different unit circuits and the coordinated control between different control systems. After this step-size simulation is completed, the simulation time is verified. t Has the simulation set time been reached? T If the simulation time reaches the set time, the simulation calculation stage will be exited, the simulation data will be exported, and subsequent processing will be performed.

2. The method for simulating power electronic system clusters based on the loop current method according to claim 1, characterized in that: area i The required memory capacity includes the admittance matrix of all devices in all state combinations within the unit circuitry of the region. Set, impedance matrix of all devices in all state combinations of a regional unit circuit. Set, the voltage vector of all unit circuits within the region Current vector of all unit circuits within the region The loop voltage vector of the unit circuit within the region The loop impedance of each unit circuit within the region Calculate the node loop voltage vector sum Calculate the node loop impedance and And the memory space occupied by each control system device.

3. The method for simulating power electronic system clusters based on the loop current method according to claim 1, characterized in that: The ideal method for allocating computing nodes is: the average number of unit circuits is n / N For areas with a greater than 1000 unit circuits n / N The region model assigns it to a single node, for regions with fewer than [number of unit circuits]. n / N The region model places two or more regions on the same node, reducing the total memory required on that compute node. Smaller than the node content capacity Under the given conditions, the minimization constraint is satisfied: 。 4. The method for implementing cluster simulation of power electronic systems based on the loop current method according to claim 1, characterized in that: The communication model used between the master node and the compute nodes includes MPI and sockets, which are used to pass the required information to the compute nodes. After the compute nodes complete the parallel computation of this stage, they send the data to the master node through the communication model. At the end of each parallel computation stage, the master node synchronizes all compute nodes and obtains the results from the compute nodes.

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