An implementation method of SM4 algorithm based on supercomputer

Abstract

The application discloses an implementation method of SM4 algorithm based on a supercomputer, and relates to the technical field of computer algorithms.The application comprises the following steps: step one, performing precalculation on a host end to perform SM4 symmetric encryption and decryption;step two, performing data encryption and decryption on a single node;step three, returning the calculation data of the single node to the host end;step four, receiving an SM4 symmetric encryption algorithm calculation request on the host end;step five, performing precalculation on the host end, grouping the encryption and decryption data, and performing SM4 symmetric encryption and decryption;step six, transmitting the result between nodes and returning the result to the host end;step seven, processing the calculation result on the host end to obtain an encryption and decryption result.The application optimizes each link of the SM4 symmetric encryption algorithm, realizes the SM4 symmetric encryption algorithm on an MT-3000, and improves the operation efficiency of the SM4 algorithm while ensuring the correctness and security of the algorithm.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of computer algorithms, and particularly relates to an implementation method of an SM4 algorithm based on a supercomputer. BACKGROUND

[0002] The SM4 algorithm, namely the original SMS4 algorithm, is a block cipher algorithm for wireless local area network products published by the State Cryptography Administration in 2006, and the SM4 cipher algorithm is the first domestic official published commercial cipher algorithm, and is approved as an industry standard by the State Cryptography Administration in March 2012, and at present, the cipher algorithm applied to security products (such as IPSec VPN, SSL, TLS, etc.) in China is gradually replaced by the SM4 algorithm to replace DES.

[0003] Optimization of the SM4 algorithm has been fully studied on the Intel platform, and with the continuous development of high-performance computing, it is of great significance to implement and optimize the SM4 cipher algorithm on a high-performance processor, which can greatly reduce the encryption and decryption time of the SM4 algorithm, however, there is no related research on the implementation and optimization of the SM4 algorithm based on a new generation of supercomputer, therefore, the application provides an implementation method of the SM4 algorithm based on a supercomputer to solve the above problems. SUMMARY

[0004] The application aims to overcome the above technical problems, and provides an implementation method of the SM4 algorithm based on a supercomputer, which optimizes each link of the SM4 symmetric encryption algorithm, and realizes the national commercial symmetric cipher algorithm on the MT-3000, thereby improving the operation efficiency of the SM4 algorithm while ensuring the correctness and security of the algorithm.

[0005] To solve the above technical problems, the technical scheme provided by the application is as follows: an implementation method of the SM4 algorithm based on a supercomputer, comprising the following steps:

[0006] Step one: pre-computing is performed on the host end, input encryption and decryption data are grouped according to available MT-3000 nodes, the filled encryption and decryption data is divided into N p same Block node data blocks according to nodes, N p is the number of available nodes, each node maps a Block node data block to perform SM4 symmetric cipher encryption and decryption, and then each node returns a same size ciphertext block;

[0007] Step two: single node performs corresponding data encryption and decryption;

[0008] Step 3: Return the computational data of a single node to the host.

[0009] Step 4: The host receives the SM4 symmetric encryption algorithm calculation request;

[0010] Step 5: The host performs pre-calculation, grouping the input encryption / decryption data according to the available MT-3000 nodes, and then dividing the padded encryption / decryption data into Np blocks of equal size based on the nodes. node Data block, N p This is the number of nodes that can be used, with each node mapping to one block. node The data block is encrypted and decrypted using SM4 symmetric cryptography, and then each node returns a ciphertext block of the same size;

[0011] Step 6: After each node completes the encryption and decryption of the corresponding data, the encrypted and decrypted results are transmitted between nodes through MPI communication. Multiple nodes complete the encryption and decryption of the grouped data in parallel. After all nodes have completed the process, the results are returned to the host, thereby improving the encryption and decryption performance of large-scale data.

[0012] Step 7: The host computer processes the calculation results returned by each node to obtain the final encryption and decryption results.

[0013] As an improvement, step two specifically involves: utilizing the numerous computing units in the acceleration domain, allowing one computing unit to handle one layer of the loop in the loop iteration structure, optimizing the loop iteration structure of the SM4 symmetric cryptography algorithm into a pipeline structure, improving the throughput of node encryption and decryption, and accelerating the encryption and decryption efficiency of a single node.

[0014] After adopting the above method, the present invention has the following advantages: The present invention implements the SM4 algorithm for the MT-3000 high-performance computing accelerator. Taking into account the architectural characteristics of the MT-3000, the SM4 algorithm is implemented quickly. The invention introduces a single-node pipeline structure optimization and a multi-node parallelization scheme, optimizes each link of the SM4 symmetric encryption algorithm, and implements the national standard commercial symmetric cryptographic algorithm on the MT-3000. While improving the computational efficiency of the SM4 algorithm, the correctness and security of the algorithm are guaranteed.

[0015] The host receives the computation request for the SM4 algorithm and stores the relevant parameters, such as the plaintext data to be encrypted and decrypted, the system parameters and fixed parameters used in the key expansion algorithm during the encryption and decryption process, etc. Then, the host is responsible for the preprocessing of the data for the SM4 symmetric encryption algorithm. In order to improve the encryption and decryption efficiency of the SM4 symmetric encryption algorithm, this invention designs a parallel optimization method for the round function loop iteration structure of SM4 based on the hardware characteristics of MT-3000. Since the SM4 symmetric encryption algorithm mainly includes an encryption and decryption module and a key expansion module, and these two modules have the same processing method, both based on a 32-round Feistel structure, these two modules account for most of the performance of the SM4 symmetric cryptographic algorithm. Therefore, optimizing the loop iteration structure can greatly improve the running efficiency of the SM4 symmetric cryptographic algorithm.

[0016] The host can receive data that needs to be encrypted using the SM4 symmetric cryptography algorithm. The host processes the plaintext data into blocks and then sends the blocks to the device for processing. Given the hardware architecture of the MT-3000, a node contains four acceleration domains, and each acceleration domain contains 24 computing units. Therefore, the data sent to a single node leverages its multiple computing units to optimize the iterative structure of the SM4 symmetric cryptography algorithm using a pipelined structure. This improves the throughput of the SM4 symmetric cryptography algorithm for encryption and decryption, accelerating the encryption and decryption efficiency within a single node. Then, across multiple nodes, the host sends the blocks to different nodes for parallel encryption and decryption via MPI communication, improving the encryption and decryption efficiency for large-scale data.

[0017] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0018] Fig. 1 This is a flowchart of the pipeline structure optimization of the SM4 symmetric cryptography algorithm within a single node based on the hardware structure characteristics of the MT-3000.

[0019] Fig. 2 This is a flowchart of the parallel optimization of the SM4 symmetric cryptography algorithm between nodes for the multi-node characteristics of the MT-3000 according to the present invention.

[0020] Fig. 3 This is the structure of the round function F in this invention.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Detailed Implementation

[0022] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] Combination Figs. 1-3 An implementation method of the SM4 algorithm based on a supercomputer includes the following steps:

[0025] Step 1: The host performs pre-calculation, grouping the input encryption / decryption data according to the available MT-3000 nodes, and then dividing the padded encryption / decryption data into N based on the nodes. p Blocks of the same size node Data block, N p This is the number of nodes that can be used, with each node mapping to one block. node The data block is encrypted and decrypted using SM4 symmetric cryptography, and then each node returns a ciphertext block of the same size;

[0026] Step 2: Single node performs encryption and decryption of corresponding data; specifically: by utilizing the numerous computing units in the acceleration domain, one computing unit undertakes one layer of the loop in the loop iteration structure, optimizing the loop iteration structure of the SM4 symmetric cryptography algorithm into a pipeline structure, improving the throughput of node encryption and decryption, and accelerating the encryption and decryption efficiency of a single node.

[0027] Step 3: Return the computational data of a single node to the host.

[0028] Step 4: The host receives the SM4 symmetric encryption algorithm calculation request;

[0029] Step 5: The host performs pre-calculation, grouping the input encryption / decryption data according to the available MT-3000 nodes, and then dividing the padded encryption / decryption data into Np blocks of equal size based on the nodes. node Data block, N p This is the number of nodes that can be used, with each node mapping to one block. nodeThe data block is encrypted and decrypted using SM4 symmetric cryptography, and then each node returns a ciphertext block of the same size;

[0030] Step 6: After each node completes the encryption and decryption of the corresponding data, the encrypted and decrypted results are transmitted between nodes through MPI communication. Multiple nodes complete the encryption and decryption of the grouped data in parallel. After all nodes have completed the process, the results are returned to the host, thereby improving the encryption and decryption performance of large-scale data.

[0031] Step 7: The host computer processes the calculation results returned by each node to obtain the final encryption and decryption results.

[0032] SM4 is a block cipher algorithm with a block size and master key length of 128 bits. The 128-bit master key is expanded into 32 32-bit round keys using a key arrangement algorithm. Both encryption and decryption transformations involve 32 iterations of the round function F. The structure of the round function F is as follows: Fig. 3 Let the plaintext input be (X0, X1, X2, X3). The ciphertext output is (Y0, Y1, Y2, Y3). The round key is RKi For i = 0, 1, ..., 31, the encryption transformation of the SM4 symmetric encryption algorithm is as follows: (1), i=0,1,...,31, Ciphertext (Y0,Y1,Y2,Y3)=(X35,X34,X33,X32), The decryption transformation of the SM4 symmetric encryption algorithm is the same as the encryption transformation structure, the only difference is the order of use of the round keys, that is, the decryption process is simply the reverse of the order of use of the round keys in the encryption process. In equation (1), the T transformation operation is a nonlinear transformation It is composed of linear transformation L, i.e., T( )=L( ( This transformation is Invertible transformation;

[0033] Nonlinear transformation : It is constructed by parallel operation of 8-bit S-boxes, The input is denoted as A = (a0, a1, a2, a3). The output is B = (b0, b1, b2, b3). Nonlinear transformation Can be defined as ;

[0034] Linear transformation L: The output is the input of the linear transformation, let the input be B. The output is C A linear change L can be defined as ;

[0035] The MT-3000 has one general domain and four acceleration domains. Each acceleration domain has 24 control cores and 384 acceleration cores (one control core + 16 acceleration cores can be regarded as a computing unit). The SM4 is optimized for parallelization based on the multi-core characteristics of this chip. Here, the operation of the general domain is the host-side operation, and the operation of the acceleration domain is the device-side operation.

[0036] This invention implements the SM4 algorithm on the MT-3000 high-performance computing accelerator. Taking into account the architectural characteristics of the MT-3000, the SM4 algorithm is implemented quickly by introducing a pipeline structure optimization within a single node and a parallelization scheme between multiple nodes. Each step of the SM4 symmetric encryption algorithm is optimized, and the national standard commercial symmetric cryptographic algorithm is implemented on the MT-3000. While improving the computational efficiency of the SM4 algorithm, the correctness and security of the algorithm are guaranteed.

[0037] The host receives the computation request for the SM4 algorithm and stores the relevant parameters, such as the plaintext data to be encrypted and decrypted, the system parameters and fixed parameters used in the key expansion algorithm during the encryption and decryption process, etc. Then, the host is responsible for the preprocessing of the data for the SM4 symmetric encryption algorithm. In order to improve the encryption and decryption efficiency of the SM4 symmetric encryption algorithm, this invention designs a parallel optimization method for the round function loop iteration structure of SM4 based on the hardware characteristics of MT-3000. Since the SM4 symmetric encryption algorithm mainly includes an encryption and decryption module and a key expansion module, and these two modules have the same processing method, both based on a 32-round Feistel structure, these two modules account for most of the performance of the SM4 symmetric cryptographic algorithm. Therefore, optimizing the loop iteration structure can greatly improve the running efficiency of the SM4 symmetric cryptographic algorithm.

[0038] The host can receive data that needs to be encrypted using the SM4 symmetric cryptography algorithm. The host processes the plaintext data into blocks and then sends the blocks to the device for processing. Given the hardware architecture of the MT-3000, a node contains four acceleration domains, and each acceleration domain contains 24 computing units. Therefore, the data sent to a single node leverages its multiple computing units to optimize the iterative structure of the SM4 symmetric cryptography algorithm using a pipelined structure. This improves the throughput of the SM4 symmetric cryptography algorithm for encryption and decryption, accelerating the encryption and decryption efficiency within a single node. Then, across multiple nodes, the host sends the blocks to different nodes for parallel encryption and decryption via MPI communication, improving the encryption and decryption efficiency for large-scale data.

[0039] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention. Actual embodiments are not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for implementing the SM4 algorithm based on a supercomputer, characterized in that: Includes the following steps: Step 1: The host performs pre-calculation, grouping the input encryption / decryption data according to the available MT-3000 nodes, and then dividing the padded encryption / decryption data into N based on the nodes. p Blocks of the same size node Data block, N p This is the number of nodes that can be used, with each node mapping to one block. node The data block is encrypted and decrypted using SM4 symmetric cryptography, and then each node returns a ciphertext block of the same size; Step 2: Encrypt and decrypt the corresponding data on a single node; Step 3: Return the computational data of a single node to the host; Step 4: The host receives the SM4 symmetric encryption algorithm calculation request; Step 5: The host performs pre-calculation, grouping the input encryption / decryption data according to the available MT-3000 nodes, and then dividing the padded encryption / decryption data into Np blocks of the same size based on the nodes. node Data block, N p This is the number of nodes that can be used, with each node mapping to one block. node The data block is encrypted and decrypted using SM4 symmetric cryptography, and then each node returns a ciphertext block of the same size; Step 6: After each node completes the encryption and decryption of the corresponding data, the encrypted and decrypted results are transmitted between nodes through MPI communication. Multiple nodes complete the encryption and decryption of the grouped data in parallel. After all nodes have completed the process, the results are returned to the host, thereby improving the encryption and decryption performance of large-scale data. Step 7: The host computer processes the calculation results returned by each node to obtain the final encryption and decryption results; Step two specifically involves: Considering the hardware structure characteristics of the MT-3000, each node contains four acceleration domains, and each acceleration domain contains 24 computing units. The MT-3000 has one general domain and four acceleration domains. Each acceleration domain has 24 control cores and 384 acceleration cores. One control core and 16 acceleration cores can be considered as one computing unit. By utilizing the numerous computing units in the acceleration domains, each computing unit can handle one layer of the loop in the iterative structure, optimizing the iterative structure of the SM4 symmetric cryptography algorithm into a pipelined structure, improving the throughput of node encryption and decryption, and accelerating the encryption and decryption efficiency of a single node.

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