Memory system and memory access interface device therefor

Abstract

A memory access interface device is provided. A clock generation circuit generates a reference clock signal. A pseudo data strobe signal generation circuit receives the reference clock signal, delays a read enable signal from a memory access controller to enable an output of the reference clock signal, and generates a pseudo data strobe signal. A true data strobe signal generation circuit receives a data strobe signal from a memory device, delays the read enable signal to enable an output of the data strobe signal, and generates a true data strobe signal. A data read circuit samples a data signal from the memory device based on a sampling signal to generate and transfer a read data signal to the memory access controller. A selection circuit selects the pseudo data strobe signal and the true data strobe signal as the sampling signal in single and double data rate transfer rate modes, respectively.

Description

Technical Field

[0001] This invention relates to memory technology, and more particularly to a memory system and its memory access interface device. Background Technology

[0002] Early common memory types were low-speed single data rate (SDR) memory. However, as product bandwidth requirements gradually increased, traditional SDR memory could no longer meet the speed demands. Therefore, double data rate (DDR) memory was proposed to overcome the speed limitations.

[0003] Within this architecture, increasingly faster double data transfer rate (DFR) memory technologies have emerged. However, commercially available controllers are required to support all speed modes. Designing a memory access interface that can be applied to both single-data-rate and double-data-rate memories is a pressing problem. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a memory system and a memory access interface device thereof to improve the prior art.

[0005] One object of the present invention is to provide a memory access interface apparatus, comprising: a clock generation circuit, a pseudo data strobe signal generation circuit, a true data strobe signal generation circuit, a data read circuit, and a selection circuit. The clock generation circuit is configured to generate a reference clock signal. The pseudo data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from a memory access controller to enable the output of the reference clock signal according to an enable segment of the read enable signal to generate a pseudo data strobe signal. The true data strobe signal generation circuit is configured to receive a data strobe signal from a memory device and delay the read enable signal to enable the output of the data strobe signal according to an enable segment of the read enable signal to generate a true data strobe signal. The data read circuit is configured to sample a data signal from the memory device according to a sampling signal, generate and transmit a read data signal to the memory access controller. The selection circuit is configured to select the pseudo data strobe signal as the sampling signal in single data transfer rate mode and to select the true data strobe signal as the sampling signal in double data transfer rate mode.

[0006] Another object of the present invention is to provide a memory system comprising: a memory access controller, a memory device, and a memory access interface device. The memory access interface device includes: a clock generation circuit, a pseudo-data strobe signal generation circuit, a true data strobe signal generation circuit, a data read circuit, and a selection circuit. The clock generation circuit is configured to generate a reference clock signal. The pseudo-data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from the memory access controller to enable the output of the reference clock signal according to an enable segment of the read enable signal, thereby generating a pseudo-data strobe signal. The true data strobe signal generation circuit is configured to receive a data strobe signal from the memory device and delay the read enable signal to enable the output of the data strobe signal according to an enable segment of the read enable signal, thereby generating a true data strobe signal. The data read circuit is configured to sample a data signal from the memory device according to a sampling signal, generate and transmit a read data signal to the memory access controller. The selection circuit is configured to select a pseudo-data strobe signal as the sampling signal in single data rate mode, and to select a true data strobe signal as the sampling signal in double data rate mode.

[0007] The features, implementation, and effects of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a block diagram of a memory system according to an embodiment of the present invention;

[0009] Figure 2 As shown in an embodiment of the present invention Figure 1 A more detailed block diagram of the memory access interface device;

[0010] Figure 3 The above is a waveform diagram of multiple signals related to the operation of the pseudo-data strobe signal generation circuit according to an embodiment of the present invention.

[0011] Figure 4 A waveform diagram of multiple signals related to the operation of a true data strobe signal generation circuit according to an embodiment of the present invention; and

[0012] Figure 5 This is a schematic diagram illustrating the timing relationship between the data signal and the sampling signal according to an embodiment of the present invention. Detailed Implementation

[0013] One object of the present invention is to provide a memory system and a memory access interface device thereof, which can achieve timing-accurate memory access in a low-cost manner, regardless of whether the memory device is a single data transfer rate memory or a double data transfer rate memory.

[0014] Please refer to Figure 1 . Figure 1 This is a block diagram illustrating a memory system 100 according to an embodiment of the present invention. The memory system 100 includes a memory access controller 110, a memory access interface device 120, and a memory device 130.

[0015] The memory system 100 can be electrically coupled to other modules via, for example, but not limited to, a system bus (not shown). For example, the memory system 100 can be electrically coupled to a processor (not shown) via a system bus so that the processor can access the memory system 100.

[0016] In one embodiment, the memory access interface device 120 may be, for example, but not limited to, a physical layer circuit.

[0017] The memory device 130 is a single data transfer rate memory or a higher-speed double data transfer rate memory.

[0018] External access signals, such as access signals from the processor, can be received by the memory access controller 110 and then transmitted to the memory access interface device 120. Furthermore, the access signal can be transmitted from the memory access interface device 120 to the memory device 130, or it can be used as a reference signal in the memory access interface device 120 to access the memory device 130.

[0019] In detail, in one embodiment, the memory access controller 110 may receive and transmit access signals, which may include, for example, but not limited to, a read enable signal REN, an instruction signal CMD, and an address signal access instruction ADD.

[0020] Based on the aforementioned signals, the memory access interface device 120 can activate the memory device 130, receive the data signal DQ from the activated memory device 130, sample the data signal DQ to generate a read data signal RDQ, and transmit it to the memory access controller 110.

[0021] When the memory device 130 is a single data transfer rate memory, the memory access interface device 120 receives the data signal DQ only from the driven memory device 130 and samples the data signal DQ according to the signal generated internally by the memory access interface device 120. When the memory device 130 is a double data transfer rate memory, the memory access interface device 120 can receive both the data signal DQ and the data strobe signal DQS from the driven memory device 130, and samples the data signal DQ according to the data strobe signal DQS.

[0022] Therefore, the internal data stored in the memory device 130 can be accessed according to the correct timing of the above signals.

[0023] The memory access interface device 120 actually includes a receiver RX and a transmitter TX. The transmitter TX receives the instruction signal CMD and the address signal ADD and transmits them to the memory device 130 to drive the memory device 130 to transmit the data signal DQ to the memory access interface device 120. The receiver RX receives the read enable signal REN and generates relevant sampling signals according to the different types of memory devices 130 (i.e., single data transfer rate memory or double data transfer rate memory), samples the data signal DQ, and completes the access operation to the memory device 130.

[0024] The following paragraphs will provide a detailed description of the structure and operation of the receiver RX.

[0025] Please refer to the following at the same time Figure 2 . Figure 2 As shown in an embodiment of the present invention Figure 1 A more detailed block diagram of the memory access interface device 120 is provided. It should be noted that... Figure 2 In this diagram, only the receiver RX of the memory access interface device 120 is shown, while the transmitter TX is not shown. Specifically, in one embodiment, Figure 2 All the circuit elements shown are located in the receiver RX.

[0026] The memory access interface device 120 includes a clock generation circuit 200, a pseudo data strobe signal generation circuit 210, a true data strobe signal generation circuit 220, a data reading circuit 230, and a selection circuit 240.

[0027] Clock generation circuit 200 is configured to generate a reference clock signal CMDCLK. In one embodiment, clock generation circuit 200 includes clock source circuit 205A and frequency divider circuit 205B. Clock source circuit 205A includes, for example, but not limited to, a phase-locked loop, and is configured to generate a source clock signal SCLK. The source clock signal SCLK can be selectively compared with... Figure 1 The transmitter TX shares the same frequency. A frequency divider circuit 205B is configured to divide the source clock signal SCLK to generate a reference clock signal CMDCLK. In one embodiment, the circuitry within the receiver RX is adapted to receive and operate according to the frequency of the reference clock signal CMDCLK.

[0028] The pseudo data strobe signal generation circuit 210 is configured to receive the reference clock signal CMDCLK and delay the read enable signal REN from the memory access controller 110 to enable the output of the reference clock signal CMDCLK according to the enable segment of the read enable signal REN, thereby generating the pseudo data strobe signal FDQS.

[0029] The true data strobe signal generation circuit 220 is configured to receive the data strobe signal DQS from the driven memory device 130 and delay the read enable signal REN to enable the output data strobe signal DQS according to the enable segment of the read enable signal REN, thereby generating the true data strobe signal TDQS.

[0030] The data read circuit 230 is configured to sample the data signal DQ from the driven memory device 130 according to the sampling signal SS, generate and transmit the read data signal RDQ to the memory access controller 110.

[0031] The selection circuit 240 is configured to select the pseudo data strobe signal FDQS as the sampling signal SS in single data rate mode, and to select the true data strobe signal TDQS as the sampling signal SS in double data rate mode.

[0032] In one embodiment, when the memory device 130 is a single data transfer rate memory, the selection circuit 240 operates in a single data transfer rate mode, and when the memory device 130 is a double data transfer rate memory, the selection circuit 240 operates in a double data transfer rate mode.

[0033] Please refer to Figure 3 . Figure 3 The above is a waveform diagram of multiple signals related to the operation of the pseudo-data strobe signal generation circuit 210 according to an embodiment of the present invention.

[0034] When the memory device 130 is a single data transfer rate (SDR) memory, the driven memory device 130 only transmits the data signal DQ to the data read circuit 230 and does not transmit the data strobe signal DQS. In this case, the pseudo data strobe signal generation circuit 210 is configured to generate a pseudo data strobe signal FDQS, thereby enabling the selection circuit 240, which operates in single data transfer rate mode, to select the pseudo data strobe signal FDQS as the sampling signal SS.

[0035] like Figure 3As shown, the pseudo-data strobe signal generation circuit 210 delays the read enable signal REN, thereby generating a delayed read enable signal REND. The enable segment SEN in the read enable signal REN is also delayed accordingly and used to enable the output reference clock signal CMDCLK. Specifically, the pseudo-data strobe signal generation circuit 210 only allows the reference clock signal CMDCLK to be output in the portion corresponding to the enable segment SEN, as the pseudo-data strobe signal FDQS.

[0036] In one embodiment, the start timing TF1 of the pseudo data strobe signal FDQS corresponds to the arrival timing TF2 of the data signal DQ transmitted from the memory device 130 to the data read circuit 230.

[0037] Specifically, the time required for the memory access interface device 120 to perform a read operation on the memory device 130 includes... Figure 1 The time when the instruction signal CMD and address signal ADD are transmitted to the memory device 130 via the transmitter TX of the memory access interface device 120, the time when the memory device 130 processes the data to retrieve the corresponding data from the corresponding address, and the time when the memory device 130 transmits the data signal DQ to the data read circuit 230 via the line.

[0038] Therefore, the pseudo-data strobe signal generation circuit 210 ensures that the timing corresponding to the sum of the delay time of the read enable signal REN and the time of generating the pseudo-data strobe signal FDQS must correspond to the timing corresponding to the total time of the above operations.

[0039] It should be noted that the term "corresponding" above means that, without causing errors in access operations, there can be an acceptable difference in timing between the two, and they do not have to be exactly the same.

[0040] In one embodiment, the duration TL of the enable segment SEN corresponding to the read enable signal REN of the pseudo-data strobe signal generation circuit 210 corresponds to the data length DL of the data signal DQ. Specifically, the duration of the enable segment SEN must be sufficient for the generated pseudo-data strobe signal FDQS to sample all data content included in the data signal DQ. Figure 3 In this example, the data signal DQ includes two data points, DA and DB. The duration of the enable segment SEN must allow the pseudo-data strobe signal FDQS to have two sampling periods. After selecting the pseudo-data strobe signal FDQS as the sampling signal SS, the selection circuit 240 causes the data reading circuit 230 to sample the data DA and DB respectively according to the sampling signal SS.

[0041] Similarly, the term "correspondence" mentioned above means that, without causing access operation errors, the time length TL and data length DL can have an allowable gap and do not have to be exactly equal.

[0042] Please refer to Figure 4 . Figure 4 The above is a waveform diagram of multiple signals related to the operation of the true data strobe signal generation circuit 220 according to an embodiment of the present invention.

[0043] When the memory device 130 is a double data rate memory, the driven memory device 130 transmits a data signal DQ and a data strobe signal DQS to the data read circuit 230. In this case, the true data strobe signal generation circuit 220 is configured to generate a true data strobe signal TDQS, thereby enabling the selection circuit 240, which operates in double data rate mode, to select the true data strobe signal TDQS as the sampling signal SS.

[0044] like Figure 4 As shown, the true data strobe signal generation circuit 220 delays the read enable signal REN, thereby generating a delayed read enable signal REND. The enable segment SEN in the read enable signal REN is also delayed accordingly and used to enable the output data strobe signal DQS. In detail, the true data strobe signal generation circuit 220 outputs a portion of the data strobe signal DQS corresponding to the enable segment SEN, as the true data strobe signal TDQS.

[0045] In one embodiment, the start timing TT1 of the true data strobe signal TDQS corresponds to the arrival timing TT2 of the memory device 130 transmitting the data strobe signal DQS to the true data strobe signal generation circuit 220.

[0046] Specifically, the time required for the memory access interface device 120 to perform a read operation on the memory device 130 includes... Figure 1 The time when the instruction signal CMD and address signal ADD are transmitted to the memory device 130 via the transmitter TX of the memory access interface device 120, the time when the memory device 130 generates the data strobe signal DQS through processing, and the time when the memory device 130 transmits the data strobe signal DQS to the true data strobe signal generation circuit 220 via the line.

[0047] Therefore, the time for delaying the read enable signal REN by the true data strobe signal generation circuit 220 needs to correspond to the total time of the above operations.

[0048] It should be noted that the term "corresponding" above means that, without causing errors in access operations, the timing of the two can have a gap within an acceptable range, and they do not have to be exactly the same.

[0049] like Figure 4 As shown, the data strobe signal DQS may include a tri-state segment TS1 before the preamble segment PRA and a tri-state segment TS2 after the postamble segment POA. Since the preamble segment PRA and the postamble segment POA are quite short (e.g., but not limited to one or two cycles in length), the read enable signal REN provides a gating mechanism to precisely eliminate the tri-state segments TS1 and TS2, resulting in a clean, true data strobe signal TDQS. This design avoids unstable signal drift caused by variations in process technology, voltage, and temperature.

[0050] In one embodiment, the time length TL of the enable segment SEN of the read enable signal REN corresponding to the true data strobe signal generation circuit 220 corresponds to the total time length TTL of the leading segment PRA, the strobe segment STS, and the trailing segment POA of the data strobe signal DQS.

[0051] In one embodiment, since the data strobe signal DQS is configured to sample the data signal DQ, the timing of the data strobe signal DQS corresponds to that of the data signal DQ, and the time length of the strobe segment STS of the data strobe signal DQS also corresponds to the data length DL of the data signal DQ. Therefore, the true data strobe signal TDQS generated according to the above method will also have corresponding timing and a strobe segment STS of the same time length. Figure 4 In the example, the data signal DQ includes eight data points DA to DH, and the gating segment STS has four sampling periods. After selecting the true data gating signal TDQS as the sampling signal SS, the selection circuit 240 causes the data reading circuit 230 to sample the data DA to DH respectively according to the sampling signal SS.

[0052] Similarly, the term "corresponding" mentioned above means that, without causing errors in access operations, the time length TL and data length DL can have a permissible difference and do not have to be exactly equal.

[0053] In one embodiment, the data readout circuit 230 may include, for example, but not limited to, a readout data receiving circuit 232, a readout data first-in-first-out circuit 234, a readout correction circuit 236, and a readout data selection circuit 238, which operate according to, for example, but not limited to, a reference clock signal CMDCLK.

[0054] The read data receiving circuit 232 is configured to sample the data signal DQ according to the sampling signal SS. The read data first-in-first-out circuit 234 is configured to perform clock domain conversion on the data sampled by the read data receiving circuit 232, thereby generating the read data signal RDQ.

[0055] In one embodiment, clock domain conversion is used to convert the clock domain of data between the data receiving circuit 232 and the memory access controller 110.

[0056] The read correction circuit 236 is configured to perform calculations on the data stored in the read data first-in-first-out circuit 234 according to a preset correction algorithm, and generate a feedback correction signal (not shown) to the read data receiving circuit 222.

[0057] In single data transfer rate mode, the data readout circuit 230 is configured to sample the data signal DQ according to the two edges of each sampling period of the sampling signal SS, thereby generating two sampling results. The readout data selection circuit 238 selects one of the two sampling results for output according to the timing relationship between the sampling signal SS and the data signal DQ, generating the readout data signal RDQ.

[0058] Please refer to Figure 5 . Figure 5 This is a schematic diagram illustrating the timing relationship between the data signal DQ and the sampling signal SS according to an embodiment of the present invention.

[0059] like Figure 5 As shown, the timing relationship between the data signal DQ and the sampling signal SS includes conditions 500, 510, and 520.

[0060] In condition 500, the negative terminal 530 of the sampling signal SS is located between the transition states of the two data points DA and DB, which can easily cause sampling errors. Therefore, the read data selection circuit 238 will select the sampling result of the positive terminal 540 of the sampling signal SS in condition 500 for output to generate the read data signal RDQ.

[0061] In condition 510, the positive terminal 540 of the sampling signal SS is located between the transition states of the two data points DA and DB, which can easily cause sampling errors. Therefore, the read data selection circuit 238 will select the sampling result of the negative terminal 530 of the sampling signal SS in condition 500 for output to generate the read data signal RDQ.

[0062] In condition 520, data can be sampled at both the negative terminal 530 and the positive terminal 540 of the sampling signal SS. Therefore, the read data selection circuit 238 can arbitrarily select the sampling result of one of the negative terminal 530 and the positive terminal 540 for output to generate the read data signal RDQ.

[0063] It should be noted that the timing relationship between the data signal DQ and the sampling signal SS can be determined by first performing a test program to sample the test data signal DQ with the sampling signal SS and observing the sampling results. This allows the data selection circuit 238 to be set, and the data selection circuit 238 to select one of the sampling results of the negative terminal 530 and the positive terminal 540 of the sampling signal SS for output in actual operation.

[0064] On the other hand, in double data transfer rate mode, the data readout circuit 230 is configured to sample the data signal DQ according to the two edges of each sampling period of the sampled signal SS, generating two sampling results. The readout data selection circuit 238 then bypasses, outputting the two sampling results to generate the readout data signal RDQ.

[0065] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art should be able to make modifications and variations without departing from the spirit of the invention.

[0066] In summary, regardless of whether the memory device is a single data transfer rate memory or a double data transfer rate memory, the memory system and its memory access interface device in this invention can achieve time-precise memory device access in a low-cost manner.

[0067] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and these changes may all fall within the scope of patent protection claimed by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of the present invention.

[0068] Explanation of reference numerals in the attached figures:

[0069] 100: Memory System

[0070] 110: Memory Access Controller

[0071] 120: Memory access interface device

[0072] 130: Memory device

[0073] 200: Clock generation circuit

[0074] 205A: Clock Source Circuit

[0075] 205B: Frequency divider circuit

[0076] 210: Pseudo-data strobe signal generation circuit

[0077] 220: True data strobe signal generation circuit

[0078] 230: Data Reading Circuit

[0079] 232: Data receiving circuit

[0080] 234: First-In-First-Out (FIFO) Circuit for Reading Data

[0081] 236: Reading the calibration circuit

[0082] 238: Data selection circuit

[0083] 240: Selection Circuit

[0084] 500, 510, 520: Status

[0085] 530: Negative end

[0086] 540: Positive End

[0087] ADD: Address signal access instruction

[0088] CMDCLK: Reference clock signal

[0089] CMD: Command signal

[0090] DA~DH: Data

[0091] DL: Data Length

[0092] DQ: Data signal

[0093] DQS: Data strobe signal

[0094] FDQS: Pseudo-data strobe signal

[0095] POA: Follow-up section

[0096] PRA: Leading Segment

[0097] RDQ: Read data signal

[0098] REN: Read enable signal

[0099] REND: Delayed read enable signal

[0100] RX: Receiver

[0101] SCLK: Source clock signal

[0102] SEN: Enable Section

[0103] STS: Gating Section

[0104] SS: Sampled signal

[0105] TDQS: True Data Strobe Signal

[0106] TF1, TT1: Start timing

[0107] TF2, TT2: Arrival Timing

[0108] TS1, TS2: Tri-state sections

[0109] TL: Duration

[0110] TTL: Total Time Length

[0111] TX: Teleporter

Claims

1. A memory access interface device, comprising: A clock generation circuit configured to generate a reference clock signal; A pseudo-data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from a memory access controller to enable the output of the reference clock signal according to an enable segment of the read enable signal, thereby generating a pseudo-data strobe signal. A true data strobe signal generation circuit is configured to receive a data strobe signal from a memory device and delay the read enable signal to enable the output of the data strobe signal according to the enable segment of the read enable signal, thereby generating a true data strobe signal. A data read circuit is configured to sample a data signal from the memory device according to a sampling signal, generate and transmit a read data signal to the memory access controller; as well as A selection circuit is configured to select the pseudo data strobe signal as the sampling signal in a single data transfer rate mode, and to select the real data strobe signal as the sampling signal in a double data transfer rate mode.

2. The memory access interface device according to claim 1, characterized in that, It also includes a receiver and a transmitter. The clock generation circuit, the pseudo data strobe signal generation circuit, the true data strobe signal generation circuit, the data reading circuit, and the selection circuit are disposed in the receiver. The transmitter is configured to receive an instruction signal and an address signal from the memory access controller and transmit them to the memory device to drive the memory device.

3. The memory access interface device according to claim 1, characterized in that, A start timing of the pseudo-data strobe signal corresponds to an arrival timing of the data signal transmitted by the memory device to the data read circuit. The start timing of the true data strobe signal corresponds to the arrival timing of the memory device transmitting the data strobe signal to the true data strobe signal generation circuit; The time length of the enable segment of the read enable signal corresponding to the pseudo data strobe signal generation circuit corresponds to a data length of the data signal; The time length of the enable segment of the read enable signal corresponding to the true data strobe signal generation circuit corresponds to the total time length of a preamble segment, a strobe segment, and a postamble segment of the data strobe signal.

4. The memory access interface device according to claim 1, characterized in that, In the single data transmission rate mode, the data readout circuit is configured to sample the data signal according to the two edges of each sampling period of the sampled signal to generate two sampling results, and select one of the two sampling results for output according to a timing relationship between the sampled signal and the data signal, thereby generating the readout data signal; as well as In the double data transfer rate mode, the data readout circuit is configured to sample the data signal according to the two edges of each sampling period of the sampled signal to generate the two sampling results and output them, thereby generating the readout data signal.

5. The memory access interface device according to claim 1, characterized in that, The memory device is a single data transfer rate memory or a double data transfer rate memory.

6. A memory system, comprising: A memory access controller; A memory device; as well as A memory access interface device, comprising: A clock generation circuit configured to generate a reference clock signal; A pseudo-data strobe signal generation circuit is configured to receive the reference clock signal and delay a read enable signal from the memory access controller to enable the output of the reference clock signal according to an enable segment of the read enable signal, thereby generating a pseudo-data strobe signal. A true data strobe signal generation circuit is configured to receive a data strobe signal from the memory device and delay the read enable signal to enable the output of the data strobe signal according to the enable segment of the read enable signal, thereby generating a true data strobe signal. A data read circuit configured to sample a data signal from the memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller; and A selection circuit is configured to select the pseudo data strobe signal as the sampling signal in a single data transfer rate mode, and to select the real data strobe signal as the sampling signal in a double data transfer rate mode.

7. The memory system according to claim 6, characterized in that, The memory access interface device further includes a receiver and a transmitter. The clock generation circuit, the pseudo data strobe signal generation circuit, the true data strobe signal generation circuit, the data reading circuit, and the selection circuit are disposed in the receiver. The transmitter is configured to receive an instruction signal and an address signal from the memory access controller and transmit them to the memory device to drive the memory device.

8. The memory system according to claim 6, characterized in that, A start timing of the pseudo-data strobe signal corresponds to an arrival timing of the data signal transmitted by the memory device to the data read circuit. The true data strobe signal and the memory device transmitting the data strobe signal to the true data strobe signal generation circuit have the same timing correspondence. The start timing of the true data strobe signal corresponds to the arrival timing of the data strobe signal transmitted by the memory device to the true data strobe signal generation circuit; The time length of the enable segment of the read enable signal corresponding to the true data strobe signal generation circuit corresponds to the total time length of a preamble segment, a strobe segment, and a postamble segment of the data strobe signal.

9. The memory system according to claim 6, characterized in that, In the single data transfer rate mode, the data readout circuit is configured to sample the data signal according to the two edges of each sampling period of the sampled signal to generate two sampling results, and select one of the two sampling results to generate the readout data signal according to a timing relationship between the sampled signal and the data signal. as well as In the double data transfer rate mode, the data readout circuit is configured to sample the data signal according to the two edges of each sampling period of the sampled signal to generate the two sampling results, thereby generating the readout data signal.

10. The memory system according to claim 6, characterized in that, The memory device is a single data transfer rate memory or a double data transfer rate memory.

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