An impedance calibration circuit and calibration method applied to HBM memory

Abstract

This invention discloses an impedance calibration circuit and calibration method for HBM memory, relating to the field of double data rate memory chip technology. The calibration method, on the one hand, eliminates the offset voltage of the comparator circuit and improves calibration accuracy by performing two calibrations with opposite polarities on the PU and PD resistors; on the other hand, it eliminates the influence of signal noise and power supply fluctuations on the calibration results by performing a voting operation on the output of the comparator circuit, determining the final output result of the comparator circuit within the voting period by counting the number of times the comparator circuit outputs 0 and 1 within the voting period, further improving calibration accuracy. This ensures that the calibration accuracy meets the requirements for fast and high-precision calibration of HBM PHYs.

Description

Technical Field

[0001] This invention belongs to the field of double data rate memory chip technology, specifically relating to an impedance calibration circuit and calibration method for HBM memory. Background Technology

[0002] In Double Data Rate (DDR) memory chips, on the one hand, with the development of DDR technology, the requirements for impedance continuity of signal transmission lines are gradually increasing. Impedance mismatch can lead to signal reflection and ringing, and in severe cases, data errors or timing deviations. On the other hand, differences in the manufacturing process, voltage, and temperature of the devices themselves can also cause inconsistent impedance in the drivers, thus affecting signal integrity. To ensure impedance consistency and improve the integrity of input and output signals and the output signal strength of DDR memory chips, an impedance (ZQ) calibration system is usually added inside the DDR memory chip and the DDR physical interface (PHY) module.

[0003] Traditional impedance calibration systems typically consist of an output driver, a comparator circuit, a reference voltage generation circuit, a finite state machine, and control logic. Their working principle is to dynamically adjust the pull-up (PU) and pull-down (PD) impedances of the output driver to achieve precise matching with an external reference resistor, thereby achieving impedance consistency.

[0004] The general process of impedance calibration is as follows: The impedance calibration system first calibrates the pull-up driver. The PU voltage and the reference voltage are input to the comparator circuit for comparison. The comparator circuit outputs the comparison result to the finite state machine. After logic processing, the output signal PUCODE is adjusted to adjust the pull-up (PU) voltage to the reference voltage level, thus completing the pull-up (PU) impedance calibration. The signal PUCODE is then stored in the register.

[0005] After calibrating the pull-up (PU) impedance, the impedance calibration system calibrates the pull-down driver: First, the obtained signal PUCODE is applied to the pull-up driver of PUPD. Then, the PUPD voltage and the reference voltage are input to the comparator circuit. After comparison, the comparator circuit outputs the result to the finite state machine. After processing by the finite state machine, the output signal PDCODE is adjusted to adjust the PUPD voltage to the reference voltage level, thus completing the PD impedance calibration. The signal PDCODE is then stored in the register.

[0006] In the calibration process of current impedance calibration systems:

[0007] On the one hand, comparator circuits generate offset voltages, which affect calibration accuracy and lead to decreased signal integrity and system stability. Current technical solutions mainly fall into two categories: one is to add a resistor string DAC to the external reference resistor, adjusting the reference voltage to offset the comparator circuit's offset voltage; the other is to modify the comparator circuit's input transistors to be adjustable, adjusting the size ratio of the input transistors to offset the comparator circuit's offset voltage. Both of these solutions require a large number of switching transistors, increasing the area of ​​the impedance calibration system and the number of input pins, resulting in significant drawbacks.

[0008] On the other hand, current impedance calibration systems are susceptible to signal noise and power supply noise. In particular, when the input terminals of the comparator circuit are close together, the output terminal of the comparator circuit may be in a dynamic flipping state under the influence of signal noise and power supply noise, which will interfere with the state machine's control of the PU / PDCODE process and further affect the accuracy of impedance calibration.

[0009] In the field of double data rate memory chips, compared with the DDR physical interface, the high bandwidth memory physical interface has higher requirements for the accuracy of the impedance calibration system. The traditional impedance calibration system mentioned above is difficult to meet the needs of high bandwidth memory. Summary of the Invention

[0010] To address the aforementioned problems in the prior art, this invention provides an impedance calibration circuit and calibration method for HBM memory. On one hand, this invention optimizes the comparator circuit and introduces a new multiplexer, voting logic circuit, and control logic to perform two calibrations with opposite polarities for the PU and PD, thereby eliminating the offset voltage of the comparator circuit. On the other hand, by using a voter in the impedance calibration circuit provided by this invention to perform a voting operation on the comparator circuit output, the influence of signal noise and power supply fluctuations on the impedance calibration results is eliminated.

[0011] The objective of this invention can be achieved through the following technical solutions:

[0012] The first aspect of this disclosure provides an impedance calibration circuit for HBM memory. The impedance calibration circuit for HBM memory comprises an output driver, a multiplexer, a reference voltage generation circuit, a comparator circuit, a voting logic circuit, a finite state machine, and control logic.

[0013] The output driver, which is the starting signal output terminal of the circuit, includes a first pull-up driver, a second pull-up driver, and a first pull-down driver. Its function is to dynamically adjust the pull-up (PU) and pull-down (PD) impedances to match the characteristic impedance of the transmission line, thereby reducing signal reflection and distortion.

[0014] The multiplexer is located at the rear end of the output driver, serving as the output terminal of the output driver and the input terminal of the comparator circuit. Its function is to select and regulate the PU and PD signals output by the output driver.

[0015] The reference voltage generation circuit is located at the front end of the comparator circuit and serves as one of the input ports of the comparator circuit. Its function is to provide a precise reference voltage for the comparator circuit.

[0016] The comparator circuit is located after the reference voltage generation circuit and the multiplexer, and is connected to the voting logic circuit. Its function is to compare the input PU signal or PD signal with the reference voltage, drive the calibration logic to adjust the impedance of the output driver, and ensure precise matching with the external reference resistor.

[0017] The comparator circuit also has a resistor-capacitor filter at the input terminal for noise reduction of the input reference voltage and PU and PD signals.

[0018] The comparator circuit also includes a comparator circuit input switch, located after the resistor-capacitor filter. Its function is to input a control signal SW to control the polarity switching of the comparator circuit.

[0019] The comparator circuit is also equipped with a comparator circuit output switch, which is used to output the result COMP_O to the voting logic circuit, so that the voter can vote.

[0020] The voting logic circuit is located at the rear end of the comparator circuit and connected to a finite state machine. Its function is to use a voter to perform a voting operation on the output of the comparator circuit. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is determined, thereby eliminating the influence of signal noise and power fluctuations on the calibration result.

[0021] The finite state machine and control logic are located at the back end of the voting logic circuit. They perform logical judgments on the output results of the voting logic circuit and output adjustment signals to adjust the impedance based on the judgment results. They are the control brain of the entire calibration process, coordinating the collaborative work of each module to ensure that the impedance adjustment process is efficient, accurate and stable.

[0022] The impedance calibration method applied to HBM memory described herein has the following process and principle:

[0023] Step 1 (PU_CAL1): Enable the first pull-up driver, output the PU voltage, and the comparator circuit input / output control signal SW=0. Use the comparator circuit to compare the PU voltage with the reference voltage. The comparator circuit outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting cycle, the final result of the comparator circuit output within the cycle is judged. The output result is fed back to the finite state machine. According to the control logic, the signal PUCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PUCODE is calibrated, the PU voltage is closest to the reference voltage. The signal PUCODE at this time is saved into the register and set as signal PUCODE1.

[0024] Step 2 (PU_CAL2): Enable the first pull-up driver to output the PU voltage. The comparator circuit input-output control signal SW=1, flipping the polarity of the comparator circuit input. The comparator circuit compares the PU voltage with the reference voltage, and outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting cycle, the final result of the comparator circuit output within the cycle is determined, and the output result is fed back to the finite state machine. According to the control logic, the signal PUCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PUCODE is calibrated, the PU voltage is closest to the reference voltage. The signal PUCODE at this time is saved into the register and set as signal data PUCODE2. The signals PUCODE1 and PUCODE2 are added and shifted to obtain the new signal data PUCODEA, completing the calibration of the PU impedance. The offset voltage of the comparator circuit is eliminated in the result of the signal PUCODEA at this time.

[0025] Step 3 (PD_CAL1): Input signal PD_EN=1, enable the second pull-up driver and the first pull-down driver, output PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver uses the output signal PUCODEA of the first pull-up driver calibrated in step 2. The comparator circuit input-output control signal SW=0. The comparator circuit compares the PD voltage with the reference voltage. The comparator circuit outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the output of the comparator circuit. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is judged. The output result is fed back to the finite state machine. According to the control logic, the signal PDCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PDCODE is calibrated, the PD voltage is closest to the reference voltage. The signal PDCODE at this time is saved into the register and set as signal PDCODE3.

[0026] Step 4 (PD_CAL2): Input signal PD_EN=1, enabling the second pull-up driver and the first pull-down driver, outputting PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver uses the output signal PUCODEA of the first pull-up driver calibrated in Step 2. The comparator circuit input-output control signal SW=1, flipping the polarity of the comparator circuit input. The comparator circuit compares the PD voltage with the reference voltage, and outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the output of the comparator circuit. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is determined, and the output result is fed back to the finite state machine. According to the control logic, the signal PDCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PDCODE is calibrated, the PD voltage is closest to the reference voltage. The signal PDCODE at this time is saved into the register and set as signal PDCODE4. After adding and shifting signals PDCODE3 and PDCODE4, a new signal PDCODEC is obtained, completing the PD impedance calibration. At this point, signal PDCODEC eliminates the offset voltage of the comparator circuit in the result, achieving accurate calibration of the entire impedance.

[0027] A second aspect of this disclosure provides a voting operation applied to an impedance calibration circuit for HBM memory as described above.

[0028] The voting operation is implemented by a voting logic circuit, and its working principle and process are as follows:

[0029] Each calibration step (PU_CAL1, PU_CAL2, PD_CAL1, PD_CAL2) contains several STEPs (test and evaluation procedure stages). The number of STEPs is equal to the number of bits in the PU / PDCODE signal. Each STEP includes latency, pipeline delay, and voting time (voting time is an odd number of clock cycles). After comparison, the comparator circuit outputs the comparison result COMP_O to the voting logic circuit. The voting logic circuit uses a clock signal to sample the comparator circuit output COMP_O and votes through the STEPs, determining the number of times the comparator circuit output COMP_O is 0 or 1 within the voting cycle. This determines the final result of the comparator circuit output within the cycle, thus eliminating the influence of signal noise and power supply fluctuations on the impedance calibration result.

[0030] The beneficial effects of this invention are as follows:

[0031] This invention introduces a high-precision impedance calibration technique that meets the fast and high-precision calibration requirements of High Memory Physical Layer Interface (HBMPHY) by adding a multiplexer and improving the comparator circuit design to a traditional impedance calibration circuit. By performing two calibrations on the pull-up impedance PU and pull-down impedance PD with opposite input polarities, and averaging the outputs of the two calibrations, the comparator circuit offset voltage is eliminated, resulting in more accurate impedance calibration results. Compared with traditional methods for eliminating comparator circuit offset voltage, this method not only reduces the area of ​​the impedance calibration system but also reduces the number of external pins required.

[0032] This invention adds a voting logic circuit to the traditional impedance calibration circuit. By using a voter to vote on the output of the comparator circuit, the final result of the comparator circuit output within the voting period is determined based on the number of times the comparator circuit output is 0 and 1. This eliminates the influence of signal noise and power supply fluctuations on the impedance calibration result, and further improves the accuracy of the calibration result.

[0033] For the High Memory Physical Layer Interface (HBMPHY), this invention completes impedance calibration in just 15~20us with an accuracy of ±5%, which can meet the fast and high-precision calibration requirements of HBM PHY. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of an impedance calibration circuit structure provided in an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the input switch structure of a multiplexer and comparator circuit provided in an embodiment of the present invention;

[0038] Figure 2-1 This is a first partial enlarged view of a schematic diagram of the input switch structure of a multiplexer and comparator circuit provided in an embodiment of the present invention;

[0039] Figure 2-2 This is a second partial enlarged view of a schematic diagram of the input switch structure of a multiplexer and comparator circuit provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the comparator circuit output switch structure provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the impedance calibration circuit operation provided in an embodiment of the present invention;

[0042] Figure 4-1 This is a flowchart of Part A of the impedance calibration circuit provided in an embodiment of the present invention;

[0043] Figure 4-2 This is a flowchart of part B of the impedance calibration circuit provided in an embodiment of the present invention.

[0044] Figure 4-3 This is a flowchart of the C part of the impedance calibration circuit provided in an embodiment of the present invention;

[0045] Figure 4-4 This is a flowchart of the D-section of the impedance calibration circuit provided in an embodiment of the present invention.

[0046] Figure 5 A schematic diagram of the STEP time composition provided for an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0048] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0049] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0050] Example 1

[0051] This embodiment provides an impedance calibration circuit for HBM memory, such as... Figure 1 The impedance calibration circuit for HBM memory described herein specifically includes an output driver (DRV), a multiplexer, a reference voltage generation circuit (VREF), a comparator circuit, a voting logic circuit, a finite state machine (FSM), and control logic.

[0052] The output driver (DRV) is the starting signal output terminal of the circuit, including a first pull-up driver (PUDRV), a second pull-up driver (PU DRV), and a first pull-down driver (PD DRV). Its function is to dynamically adjust the pull-up (PU) and pull-down (PD) impedances to match the characteristic impedance of the transmission line, thereby reducing signal reflection and distortion.

[0053] The aforementioned multiplexer has the following specific structure: Figure 2 , Figure 2-1 and Figure 2-2 As shown, it is located at the rear end of the output driver (DRV) and serves as the output terminal of the output driver and the input terminal of the comparator circuit. Its function is to select and regulate the PU and PD signals output by the output driver.

[0054] The reference voltage generation circuit (VREF) is located at the front end of the comparator circuit and serves as one of the input ports of the comparator circuit. Its function is to provide a precise reference voltage for the comparator circuit.

[0055] The comparator circuit is located after the reference voltage generation circuit and the multiplexer, and is connected to the voting logic circuit. Its function is to compare the input PU signal or PD signal with the reference voltage, drive the calibration logic to adjust the impedance of the output driver, and ensure precise matching with the external reference resistor.

[0056] The comparator circuit also has a resistor-capacitor filter (RCFILT) at the input terminal to perform signal denoising on the input reference voltage and PU and PD signals.

[0057] The comparator circuit also includes a comparator circuit input switch, the specific structure of which is as follows: Figure 2 , Figure 2-1 and Figure 2-2 As shown, it is located at the end of the resistor-capacitor filter and its function is to input the control signal SW to control the comparator circuit to switch polarity.

[0058] The comparator circuit also includes a comparator circuit output switch, the specific structure of which is as follows: Figure 3 As shown, the output result COMP_O is sent to the voting logic circuit to facilitate voting by the voter.

[0059] The voting logic circuit is located at the back end of the comparator circuit and connected to a finite state machine. It also requires a clock signal (CLK) to operate. Its function is to use the voter to vote on the output of the comparator circuit. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is judged, thus eliminating the influence of signal noise and power fluctuations on the calibration result.

[0060] The finite state machine (FSM) and control logic are located at the back end of the voting logic circuit. They perform logical judgments on the output results of the voting logic circuit and output adjustment signals to adjust the impedance based on the judgment results. They are the control brain of the entire calibration process, coordinating the collaborative work of each module to ensure that the impedance adjustment process is efficient, accurate and stable.

[0061] Based on the aforementioned impedance calibration circuit for HBM memory, on the one hand, it can perform two calibrations with different polarities for the pull-up (PU) impedance and pull-down (PD) impedance, and by averaging, eliminate the comparator circuit offset voltage to obtain a more accurate calibration result. On the other hand, the voter in the voting logic circuit can perform a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period can be determined, thus eliminating the influence of signal noise and power supply fluctuations on the impedance calibration result.

[0062] Example 2:

[0063] This embodiment provides an impedance calibration method for HBM memory, which is applied to the impedance calibration circuit for HBM memory described above.

[0064] like Figure 4 , Figure 4-1 , Figure 4-2 , Figure 4-3 , Figure 4-4 As shown, the flow steps of the impedance calibration method applied to HBM memory are as follows:

[0065] Step 1 (PU_CAL1): Enable the first pull-up driver (PU_DRV) to output the PU voltage. The comparator circuit input and output control signal SW=0. The comparator circuit compares the PU voltage with the reference voltage (VREF). The comparator circuit outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is judged. The output result is fed back to the finite state machine. According to the control logic, the signal PUCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PUCODE is calibrated, the PU voltage is closest to the reference voltage. The signal PUCODE at this time is saved into the register and set as signal PUCODE1.

[0066] Step 2 (PU_CAL2): Enable the first pull-up driver (PU_DRV) to output the PU voltage. The comparator circuit input-output control signal SW=1, flipping the polarity of the comparator circuit input. The comparator circuit compares the PU voltage with the reference voltage (VREF). The comparator circuit outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is determined. The output result is fed back to the finite state machine (FSM). According to the control logic, the signal PUCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PUCODE is calibrated, the PU voltage is closest to the reference voltage. The signal PUCODE at this time is saved into the register and set as signal data PUCODE2. After adding signals PUCODE1 and PUCODE2 and shifting them, a new signal data PUCODEA is obtained, which completes the calibration of the PU impedance. At this time, the offset voltage of the comparator circuit is eliminated in the result of the signal PUCODEA.

[0067] Step 3 (PD_CAL1): Input signal PD_EN=1, enabling the second pull-up driver (PU_DRV) and the first pull-down driver (PD_DRV), outputting PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver (PU_DRV) uses the output signal PUCODEA of the first pull-up driver calibrated in Step 2. The comparator circuit input-output control signal SW=0, using the comparator circuit to compare the PD voltage with the reference voltage (VREF). The comparator circuit outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output. By judging the number of times the comparator circuit output is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is judged, and the output result is fed back to the finite state machine. According to the control logic, the signal PDCODE is adjusted using the bit-by-bit binary search method or SAR logic. When the last bit of the signal PDCODE is calibrated, the PD voltage is closest to the reference voltage (VREF). The signal PDCODE at this time is saved into the register and set as signal PDCODE3.

[0068] Step 4 (PD_CAL2): Input signal PD_EN=1, enabling the second pull-up driver (PU_DRV) and the first pull-down driver (PD_DRV), outputting PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver (PU_DRV) uses the output signal PUCODEA of the first pull-up driver calibrated in Step 2. The comparator circuit input / output control signal SW=1, flipping the input polarity of the comparator circuit. The comparator circuit compares the PD voltage with the reference voltage (VREF), and outputs the comparison result to the voting logic circuit. The voting logic circuit performs a voting operation on the comparator circuit output, determining the final result of the comparator circuit output within the voting cycle by counting the number of times the comparator circuit output is 0 or 1. The output result is then fed back to the finite state machine (FSM) according to the control logic. The PD impedance is calibrated using a bit-by-bit binary search or SAR logic. Once the last bit of the PD code is calibrated, the PD voltage is closest to the reference voltage (VREF). This PD code is then saved to a register and designated as PDCODE4. PDCODE3 and PDCODE4 are added together and shifted to obtain a new signal PDCODEC, completing the PD impedance calibration. PDCODEC eliminates the offset voltage from the comparator circuit in the result, achieving precise calibration of the entire impedance.

[0069] Example 3

[0070] This embodiment provides a STEP (Test and Evaluation Procedure) stage, which is applied to the voting logic circuit of the impedance calibration circuit described above. Based on the STEP, the output result of the comparator circuit is voted on. By judging the number of times the output result of the comparator circuit is 0 and 1 within the voting period, the final result of the comparator circuit output within the period is determined, thus eliminating the influence of signal noise and power supply fluctuations on the impedance calibration result.

[0071] The time composition of each STEP is as follows: Figure 5 As shown. STEP includes latency, pipeline delay, and voting time, where the voting time is an odd number of clock cycles.

[0072] Each calibration step (PU_CAL1, PU_CAL2, PD_CAL1, PD_CAL2) contains several STEPs (test and evaluation procedure stages), the number of which is equal to the number of bits in the PU / PDCODE signal.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An impedance calibration circuit for HBM memory, characterized in that: It includes an output driver, a multiplexer, a reference voltage generation circuit, a comparator circuit, a voting logic circuit, a finite state machine, and a control logic module; The multiplexer is located at the rear end of the output driver, serving as the output terminal of the output driver and the input terminal of the comparator circuit, and is used to select and control the PU signal and PD signal output by the output driver. The comparator circuit is located after the reference voltage generation circuit and the multiplexer, and is used to compare the input PU signal or PD signal with the input reference voltage to drive the calibration logic to adjust the impedance of the output driver. The voting logic circuit is located at the back end of the comparator circuit and connected to a finite state machine. It is used to perform voting operations on the output result of the comparator circuit. By judging the number of times the comparator circuit outputs 0 and 1 within the voting period, the final result of the comparator circuit output within the period is judged. The finite state machine and control logic module are located at the back end of the voting logic circuit. They are used to make logical judgments on the output results of the voting logic circuit and output a feedback signal PUCODE to the output driver.

2. The impedance calibration circuit for HBM memory according to claim 1, characterized in that, The output driver is used to output an initial calibration voltage signal, and the output driver includes a first pull-up driver, a second pull-up driver, and a first pull-down driver.

3. The impedance calibration circuit for HBM memory according to claim 1, characterized in that, The comparator circuit is equipped with a comparator circuit input switch, which is used to transmit control signals to the comparator to control the comparator circuit to flip its polarity.

4. The impedance calibration circuit for HBM memory according to claim 1, characterized in that, The comparator circuit is equipped with a comparator output switch, which is used to output the result to the voting logic circuit for voting operations.

5. The impedance calibration circuit for HBM memory according to claim 1, characterized in that, The comparator circuit also has a resistor-capacitor filter at the input terminal for noise reduction of the input reference voltage, PU signal and PD signal.

6. The impedance calibration circuit for HBM memory according to claim 1, characterized in that, The comparator circuit further includes at least one of a resistor-capacitor filter, a comparator input switch, and a comparator output switch.

7. An impedance calibration method for HBM memory, applied to an impedance calibration circuit for HBM memory as described in any one of claims 1 to 6, characterized in that, Includes the following steps: PU_CAL1: Enables the first pull-up driver, outputs the PU voltage, the comparator circuit input and output control signal SW=0, the comparator circuit compares the PU voltage with the reference voltage, the comparator circuit outputs the comparison result to the voting logic circuit, the voting logic circuit performs a voting operation on the comparator circuit output to obtain the final output result, the final output result is fed back to the finite state machine, and PUCODE is adjusted according to the bit-by-bit binary search method or SAR logic. After the last bit of PUCODE is calibrated, PUCODE is stored in the register and recorded as signal PUCODE1; PU_CAL2: Enables the first pull-up driver, outputs the PU voltage, the comparator circuit input-output control signal SW=1, the comparator circuit input polarity is reversed, the comparator circuit compares the PU voltage with the reference voltage, the signal PUCODE adjustment process is the same as PU_CAL1, resulting in signal PUCODE2; after adding signal PUCODE1 and signal PUCODE2 and shifting, a new signal PUCODEA is obtained; PD_CAL1: Input signal PD_EN=1, enables the second pull-up driver and the first pull-down driver, outputs PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver uses the calibrated signal PUCODEA. The comparator circuit input-output control signal SW=0. The comparator circuit compares the PUPD voltage with the reference voltage. The signal PDCODE adjustment process is the same as PU_CAL1, resulting in signal PDCODE3. PD_CAL2: Input signal PD_EN=1, enabling the second pull-up driver and the first pull-down driver, outputting PU voltage and PD voltage. The input signal PUCODEB of the second pull-up driver uses the output signal PUCODEA of the first pull-up driver calibrated in step PU_CAL2. The comparator circuit input-output control signal SW=1, the input polarity of the comparator circuit is reversed, and the comparator circuit compares the PUPD voltage with the reference voltage. The signal PDCODE adjustment process is the same as PU_CAL1, resulting in signal PDCODE4. Signals PDCODE3 and PDCODE4 are added and shifted to obtain a new signal PDCODEC.

8. The impedance calibration method for HBM memory according to claim 7, characterized in that, The voting operation is as follows: the output result of the comparator circuit is voted on through STEP, and the final result of the comparator circuit output within the voting period is determined based on the number of times the comparator circuit output result is 0 and 1 within the voting period.

9. The impedance calibration method for HBM memory according to claim 7, characterized in that, Each of the steps PU_CAL1, PU_CAL2, PD_CAL1, and PD_CAL2 includes several steps, the number of which is equal to the number of bits in the signal PUCODE / PDCODE.

10. The impedance calibration method for HBM memory according to claim 7, characterized in that, The time components of each STEP include waiting time, pipeline delay, and voting time, with the voting time being an odd number of clock cycles.

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