Memory packages and storage devices including memory packages

Abstract

A memory package and a storage device including the memory package are provided. The memory package includes: a package substrate; memory chips disposed on the package substrate and divided into a first group and a second group, the first group and the second group being spaced apart from each other in a first horizontal direction; a first buffer chip disposed on the package substrate and outputting control command signals received from an external memory controller to the first group; and a second buffer chip disposed on the package substrate and outputting control command signals to the second group. The package substrate includes: a main path for transmitting control command signals from an external memory controller, and branch path paths connecting the main path to each of the first and second buffer chips. The branch path paths branch the control command signals to the first and second buffer chips. The branch path paths are disposed in the space between the first and second buffer chips.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0167122, filed on November 21, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments relate to memory packages and storage devices including memory packages. Background Technology

[0003] A memory package may include multiple memory chips mounted on a package substrate, and a storage device may include one or more memory packages. The storage device may include a device controller for controlling the memory package, and the device controller may control the multiple memory chips via a buffer chip included in the memory package. With the continued growth in demand for data storage in various electronic devices, the need for memory packages and storage devices in which buffer chips and memory chips are efficiently arranged is constantly increasing. Summary of the Invention

[0004] One of the problems addressed by the example embodiments is providing a memory package and storage device in which multiple memory chips are effectively connected using a connection layer of a package substrate and / or a system substrate.

[0005] According to one aspect of this disclosure, a memory package includes: a package substrate; a plurality of memory chips disposed on an upper surface of the package substrate and grouped into a first group of memory chips stacked in a vertical direction perpendicular to the upper surface of the package substrate and a second group of memory chips stacked in the same vertical direction, wherein the first group of memory chips is spaced apart from the second group of memory chips in a first horizontal direction parallel to the upper surface of the package substrate; a first buffer chip disposed on the upper surface of the package substrate and configured to output a control command signal received from an external memory controller to the first group of memory chips; and a second buffer chip disposed on the upper surface of the package substrate and configured to output a control command signal to the second group of memory chips, wherein the first buffer chip and the second buffer chip are disposed in a space between the first group of memory chips and the second group of memory chips and are arranged in the first horizontal direction. The package substrate includes: a main path through which the control command signal is transmitted from the external memory controller; and a branch path connecting the main path to each of the first buffer chip and the second buffer chip. The branch path is configured to branch the control command signal received from the main path to the first buffer chip and the second buffer chip. When viewed in a plan view, the branch line path is set in the space between the first buffer chip and the second buffer chip.

[0006] According to one aspect of this disclosure, a storage device includes: a system substrate including a plurality of interconnects; a memory controller mounted on the system substrate; and at least one memory package mounted on the system substrate and configured to operate in response to control command signals received from the memory controller via the plurality of interconnects, wherein the at least one memory package includes: a plurality of memory chips; a pair of buffer chips adjacent to each other in a first horizontal direction parallel to an upper surface of the system substrate, connected to the memory controller and the plurality of memory chips, and configured to output control command signals received from the memory controller to the plurality of memory chips; a package substrate including a plurality of connectors and a plurality of upper bonding pads, the plurality of connectors being electrically connected to the plurality of interconnects, the plurality of upper bonding pads being between and electrically connected to the pair of buffer chips, wherein the plurality of memory chips and the pair of buffer chips are mounted on the package substrate; and a protective layer encapsulating the plurality of memory chips and the pair of buffer chips. The pair of buffer chips is connected to the memory controller via a single channel provided by the plurality of interconnects and the plurality of connectors. A single channel includes: a main path connected to the memory controller; and a branch path extending from one end of the main path located between the pair of buffer chips and connected to each of the pair of buffer chips. The branch path includes a horizontal portion extending from the said end of the main path in a first horizontal direction and having opposing ends respectively connected to corresponding upper bonding pads among the plurality of upper bonding pads. The said end of the main path is connected to the middle of the opposing ends of the horizontal portion of the branch path in the first horizontal direction. The opposing ends of the horizontal portions of the branch path are at the same vertical level in a vertical direction perpendicular to the upper surface of the system substrate.

[0007] According to one aspect of this disclosure, a storage device includes: a system substrate; a memory controller mounted on the system substrate; and at least one memory package mounted on the system substrate and configured to operate in response to a control command signal received from the memory controller. The at least one memory package includes: a plurality of memory chips; a pair of buffer chips disposed adjacent to each other, connected to the memory controller and the plurality of memory chips, and configured to output the control command signal received from the memory controller to the plurality of memory chips; and a package substrate including a pair of upper bonding pads electrically connected to the pair of buffer chips. The plurality of memory chips and the pair of buffer chips are mounted on the package substrate. The pair of buffer chips are connected to the memory controller via a main path extending from the memory controller and a branch path extending from the main path. The branch path contacts the pair of upper bonding pads between the pair of buffer chips.

[0008] According to one aspect of an example embodiment, a storage device is provided, the storage device comprising: a system substrate including interconnects; a device controller mounted on the system substrate; and at least one memory package mounted on the system substrate and configured to operate in response to a control command received from the device controller via the interconnects, wherein the at least one memory package includes: a plurality of memory chips; at least one pair of buffer chips arranged adjacent to each other, connected to the device controller and the plurality of memory chips, and configured to output control commands input from the device controller to the plurality of memory chips; and a package substrate including connectors electrically connected to the interconnects, wherein the plurality of memory chips and the pair of buffer chips are mounted on the package substrate, wherein the at least one pair of buffer chips is connected to the device controller via a branch path provided by the connector, and the branch path is located between opposite sides of the pair of buffer chips. The package substrate further includes an upper bonding pad disposed between the at least one pair of buffer chips, and the connector includes a horizontally extending connection pattern and a connection via extending from the connection pattern to the upper bonding pad, and the connection pattern and the connection via provide the branch path. The branch line path includes: a horizontal portion provided by a connecting pattern; and a vertical portion provided by a connecting via, extending from the opposite end of the horizontal portion to the upper mating pad. Attached Figure Description

[0009] The above and other aspects, features and advantages of the exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 and Figure 2 This is a schematic diagram of a storage device according to an example embodiment of an example embodiment.

[0011] Figure 3 This is a schematic circuit diagram of a memory cell array according to an example embodiment.

[0012] Figure 4 This is a schematic diagram of the appearance of a storage device according to an example embodiment.

[0013] Figure 5 This is a cross-sectional side view of a storage device according to an example embodiment.

[0014] Figure 6 This is a schematic diagram of the appearance of a storage device according to an example embodiment.

[0015] Figure 7A and Figure 7B This is a cross-sectional side view of a storage device according to an example embodiment.

[0016] Figure 8 This is a schematic diagram of a buffer chip according to an example embodiment.

[0017] Figure 9 This is a cross-sectional side view of a memory package according to an example embodiment.

[0018] Figure 10 This is a cross-sectional side view of a memory package according to an example embodiment.

[0019] Figure 11 This is a cross-sectional side view of a memory package according to an example embodiment.

[0020] Figure 12 This is a cross-sectional side view of a memory package according to an example embodiment.

[0021] Figure 13 This is a cross-sectional side view of a memory package according to an example embodiment.

[0022] Figure 14 This is a cross-sectional side view of a memory package according to an example embodiment.

[0023] Figure 15 This is a cross-sectional side view of a memory package according to an example embodiment. Detailed Implementation

[0024] In the following description, examples of embodiments will be described with reference to the accompanying drawings. Unless otherwise specifically stated, in this specification, terms such as “upper,” “upper surface,” “lower,” “lower surface,” “side surface,” etc., are based on the drawings and may actually vary depending on the orientation of the component arrangement.

[0025] Furthermore, ordinal numbers (such as "first," "second," "third," etc.) can be used as markers for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or other claims).

[0026] Figure 1 and Figure 2 This is a schematic diagram of storage devices 1 and 100 according to an example embodiment of the example embodiments.

[0027] First, refer to Figure 1The storage device 1 may include a device controller 10 and a memory region 20. The device controller 10 may be a memory controller for controlling the operation of the memory region 20. The storage device 1 may support multiple channels CH1 to CHm, and the memory region 20 and the device controller 10 may be connected via multiple channels CH1 to CHm. For example, the storage device 1 may include a solid-state drive (SSD) device, etc.

[0028] Memory region 20 may include multiple memory packages 201 to 20 m Multiple memory packages 201 to 20 m Multiple channels CH1 to CHm can be connected to the device controller 10, and multiple memory packages 201 to 2020 are also available. m Each of the multiple memory devices NVM11 to NVMmn may include a plurality of memory devices NVM11 to NVMmn. Each of the multiple memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, memory devices NVM11 to NVM1n included in the first memory package 201 may be connected to the first channel CH1 via paths W11 to W1n, and memory devices NVM21 to NVM2n included in the second memory package 202 may be connected to the second channel CH2 via paths W21 to W2n.

[0029] In the example embodiment, each of the plurality of memory devices NVM11 to NVMmn can be implemented as an arbitrary memory cell operable according to individual commands from the device controller 10. For example, each of the plurality of memory devices NVM11 to NVMmn can be implemented as a chip or a die. However, the example embodiment is not limited thereto. When each of the plurality of memory devices NVM11 to NVMmn is implemented as a chip or a die, the plurality of memory devices NVM11 to NVMmn can be respectively housed in a plurality of memory packages 201 to 20 m They are stacked on top of each other.

[0030] The device controller 10 can send signals to or receive signals from the memory region 20 via multiple channels CH1 to CHm. For example, the device controller 10 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory region 20 via multiple channels CH1 to CHm, or receive data DATAa to DATAm from the memory region 20.

[0031] In the embodiment, multiple memory packages 201 to 20 mThe device may include a buffer chip, which can transmit signals between multiple memory devices NVM11 to NVMmn and the device controller 10. For example, during a programming operation, the device controller 10 can send an address signal and data to be stored in memory region 20 to the buffer chip. The buffer chip can send data to one of the multiple memory devices NVM11 to NVMmn based on the address signal.

[0032] When multiple memory packages 201 to 20 m When a buffer chip is included, the buffer chip can output data and address signals to at least one of the plurality of memory devices NVM11 to NVMmn based on the data and address signals sent to the buffer chip by the device controller 10. In other words, the buffer chip can branch and provide signal transmission paths between the device controller 10 and the plurality of memory devices NVM11 to NVMmn.

[0033] Device controller 10 can select one of the non-volatile memory devices connected to each channel via each channel, and send signals to or receive signals from the selected non-volatile memory device. For example, device controller 10 can select non-volatile memory device NVM11 among non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. Device controller 10 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0034] Device controller 10 can send signals in parallel to memory region 20 or receive signals in parallel from memory region 20 via different channels. For example, device controller 10 can send command CMDa to first memory package 201 via first channel CH1, and simultaneously send command CMDb to second memory package 202 via second channel CH2. For this purpose, each of first memory package 201 and second memory package 202 may include a buffer chip. Optionally, device controller 10 can receive data DATAa from first memory package 201 via first channel CH1, and simultaneously receive data DATAb from second memory package 202 via second channel CH2.

[0035] Device controller 10 controls the overall operation of memory region 20. Device controller 10 can control each of the multiple memory devices NVM11 to NVM1n connected to multiple channels CH1 to CHm by sending signals to multiple channels CH1 to CHm. For example, device controller 10 can control the selection of one of the multiple memory devices NVM11 to NVM1n by sending command CMDa and address ADDRa to the first channel CH1.

[0036] Each of the plurality of memory devices NVM11 to NVMmn can operate under the control of device controller 10. For example, memory device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided through the first channel CH1. For example, memory device NVM21 can read data DATAb based on the command CMDb and address ADDRb provided through the second channel CH2, and send the read data DATAb to device controller 10.

[0037] Figure 1 The diagram shows that memory region 20 communicates with device controller 10 via m channels, and memory region 20 includes n non-volatile memory devices corresponding to each channel. However, the number of channels and the number of memory devices connected to a channel can vary.

[0038] Reference Figure 2 The storage device 100 in the example embodiment may include a device controller (or external device controller) 110 and a memory package 120. The memory package 120 may include a pair of buffer chips BF and a plurality of memory chips MC, and the plurality of memory chips MC may be divided into a plurality of groups G1 and G2. Figure 2 In the embodiments shown, the number of memory chips MC included in each of groups G1 and G2 is described as the same, but the number of memory chips MC included in at least some of groups G1 and G2 may be different from each other.

[0039] The memory chips MC included in each of the multiple groups G1 and G2 can be connected to a pair of buffer chips BF via different paths. For example, the multiple memory chips included in the first group G1 can be connected to each other via a first lead W1, and can also be connected to a first buffer chip 121. The multiple memory chips included in the second group G2 can be connected to each other via a second lead W2, and can also be connected to a second buffer chip 122. Although in Figure 2The diagram briefly illustrates this, but multiple first leads W1 and multiple second leads W2 can be configured to connect the first group G1 and the second group G2 to the buffer chip BF, respectively. Furthermore, according to embodiments, memory chips can be connected to each other via connection methods different from those of leads W1 and W2, or memory chips MC can be connected to the buffer chip BF. As an example, the memory chips in the first group G1 can be connected to each other via through-silicon vias (TSVs) and can be connected to the first buffer chip 121 via first leads W1. Figure 14 (Example).

[0040] The buffer chip BF can be a chip that facilitates signal exchange between the device controller 110 and the memory package 120. The buffer chip BF can be connected to leads W1 and W2 via multiple chip pads PAD1 and PAD2. The multiple chip pads PAD1 and PAD2 are connected to a selection circuit SC, and the selection circuit SC can select at least one of the multiple chip pads PAD1 and PAD2 according to a command from the device controller 110. Figure 2 In the diagram, the buffer chip BF is shown as including a controller connection pad PAD1 and a memory connection pad (or memory access pad) PAD2, but multiple controller connection pads PAD1 and memory connection pads PAD2 can be provided respectively.

[0041] As an example, the device controller 110 may send an address signal to the controller connection pad PAD1 of the buffer chip BF for selecting at least one memory chip MC from the first group G1 and the second group G2. The buffer chip BF may select the memory connection pad PAD2 based on the address signal and send data to or receive data output from the memory chip. If the storage device 100 supports multi-channel operation to reduce latency, the address signal generated by the device controller 110 and its corresponding control command may be sent simultaneously to the first group G1 and the second group G2.

[0042] For example, if the device controller 110 generates a control command to perform a control operation (such as a programming operation, a reading operation, etc.), the control command may include address information specifying the memory chip used to perform the control operation. The selection circuit SC of the buffer chip BF may select at least one of the plurality of memory access pads PAD2 based on the address information included in the control command, and may not select the remaining plurality of memory access pads PAD2.

[0043] According to an embodiment, at least one of a transmitter for sending data and / or signals to a memory chip and a receiver for receiving data from the memory chip can be connected to each of a plurality of chip pads PAD1 and PAD2. A selection circuit SC can select at least one of the plurality of chip pads PAD1 and PAD2 based on address information received from the device controller 110, and can activate the transmitter and / or receiver connected to the selected at least one chip pad. Furthermore, the selection circuit SC can deactivate the transmitter and receiver connected to the unselected chip pads among the plurality of chip pads PAD1 and PAD2.

[0044] As an example, the selection circuit SC may include a multiplexer or a demultiplexer. Thus, the selection circuit SC can selectively send data and signals received from the device controller 110 to multiple memory chips divided into N groups (N being a natural number greater than or equal to 2).

[0045] Each memory chip MC may include a semiconductor substrate 211 and a first structure 212 and a second structure 213 stacked on the semiconductor substrate 211. As an example, the first structure 212 may include a peripheral circuit region in which peripheral circuitry (e.g., row decoder, page buffer, voltage generator, etc.) required for the operation of each memory chip MC is arranged. The second structure 213 may include a cell region in which a common source line 214, a gate stack structure 215 with a gate electrode layer stacked on the common source line 214, a channel structure 216 penetrating the gate stack structure 215, or a bit line 217 electrically connected to the channel structure 216 are arranged.

[0046] Each of the memory chips MC may include a through interconnection 218 connected to peripheral circuitry in the first structure 212 and extending in the second structure 213. The through interconnection 218 may be connected to an input / output pad 219 disposed above each of the memory chips MC. The input / output pad 219 of each memory chip MC included in the first group G1 may be connected to a first lead W1, and the input / output pad 219 of each memory chip MC included in the second group G2 may be connected to a second lead W2. Therefore, the memory chips MC included in each of the first group G1 and the second group G2 are electrically connected to each other.

[0047] The reference shows the sectional view. Figure 2 The through-interconnect 218 of the memory chip MC is shown as one, but each of the memory chips MC may include multiple through-interconnects. Multiple through-interconnects can be connected to multiple first leads via multiple input / output pads.

[0048] In one of the exemplary embodiments, the memory package 120 may include buffer chips BF corresponding to groups G1 and G2 of the memory chip MC, respectively, and the buffer chips BF may be connected to the device controller 110 via the same channel. Therefore, the stub path between the device controller 110 and the buffer chips BF can be minimized, and signal reflection and RC delay can be minimized.

[0049] Figure 3 This is a schematic circuit diagram of a memory cell array according to an example embodiment.

[0050] Figure 3 This is a diagram illustrating a 3D Vertical NAND (V-NAND) structure applicable to a memory package according to an example embodiment. When a memory device included in a memory package is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the memory device can be configured as follows: Figure 3 The equivalent circuit shown is illustrated.

[0051] Figure 3 The memory block BLK shown represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, multiple memory NAND strings included in the memory block BLK may be formed in a direction perpendicular to the substrate.

[0052] Reference Figure 3 The memory block BLK may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., and MC8, and a ground select transistor GST. Although Figure 3 Each of the multiple memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, ..., and MC8, but the example embodiment is not necessarily limited thereto.

[0053] The string select transistor SST can be connected to the corresponding string select line SSL1, SSL2, or SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The string select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0054] Word lines of the same height (e.g., one of GTL1 through GTL8) can be connected together, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 can be separated separately. Figure 3 In the diagram, the memory block BLK is shown as connected to eight gate lines GTL1, GTL2, ..., and GTL8 and three bit lines BL1, BL2 and BL3, but the inventive concept is not limited thereto.

[0055] Figure 4 This is a schematic diagram of the appearance of the storage device 100A according to an example embodiment. In the following, in the detailed description and claims, "storage device" may refer to a "memory package" that also includes the system substrate 101 and / or the device controller 110.

[0056] Reference Figure 4 In the example embodiment, storage device 100A may be a solid-state drive (SSD). Storage device 100A may have a form factor according to the M.2 standard and may communicate with an external central processing unit, system-on-a-chip, or application processor according to the PCIe (Peripheral Component Interconnect Fast) protocol. However, the form factor of storage device 100A and the protocol used for communication with other external devices may vary depending on the embodiment. For example, storage device 100A may have a form factor such as a 2.5-inch disk drive and may communicate with other external devices according to the SATA (Serial Advanced Technology Attachment) protocol.

[0057] Storage device 100A may include a system substrate 101, connector pins 102 and component elements 103 formed on the system substrate 101, a device controller 110 mounted on the system substrate 101, a memory package (e.g., NAND flash memory) 120, or dynamic random access memory (DRAM) 130, and a power management integrated circuit (PMIC) 140. Connector pins 102 may contact pins of a computer device and / or server device on which storage device 100A is mounted. Component elements 103 may include passive components (such as resistors and capacitors) required for the operation of storage device 100A.

[0058] Device controller 110 can control storage device 100A according to control commands from computer device and / or server device. Device controller 110 can store data received through connector pin 102 in memory package 120 and / or DRAM 130, or can read data stored in memory package 120 and / or DRAM 130 and output the data to computer device and / or server device. PMIC 140 can distribute power supplied through connector pin 102 to device controller 110, memory package 120 or DRAM 130.

[0059] The memory package 120 may be implemented as a memory package according to the embodiments described below. For example, each of the memory packages 120 may include at least one pair of buffer chips and a plurality of memory chips. The pair of buffer chips may be arranged such that the controller connection pads face each other (0 degrees and 180 degrees). Furthermore, one of the buffer chips may include a data mirroring function. This will be referred to... Figure 5 A more detailed description follows.

[0060] Figure 5 This is a cross-sectional side view of the storage device 100A according to an example embodiment.

[0061] Reference Figure 5 The storage device 100A of the example embodiment may include at least one memory package 120, a device controller 110, and a system substrate 101.

[0062] System substrate 101 may include interconnect pads 101P and interconnects INC. Interconnects INC can be connected to device controller 110 and memory package 120 via interconnect pads 101P. Device controller 110 is mounted on interconnect pad 101P via chip bumps 118, and memory package 120 is mounted on interconnect pad 101P via package bumps 128. Device controller 110 and memory package 120 are electrically connected to each other via interconnects INC formed within system substrate 101 and can exchange signals with each other. Interconnects INC may include interconnect pattern portions and interconnect via portions made of conductive material.

[0063] In an example embodiment, signals generated by the device controller 110 to control the memory package 120 and data to be stored in the memory chip MC within the memory package 120 can be sent to the memory package 120 via channels CH1 and CH2 provided by interconnect INC. For example, the device controller 110 can communicate with the memory package 120 mounted on the system substrate 101 via a first channel CH1 provided by a first interconnect INC1 and a second channel CH2 provided by a second interconnect INC2, respectively. According to an example embodiment, the device controller 110 can communicate with memory packages 120, each comprising multiple buffer chips BF, via a single channel. For example, multiple buffer chips BF can share a single channel. Therefore, the branch path length of the channel can be reduced, and the SI (signal integrity) characteristics of the memory device can be improved.

[0064] The memory package 120 can be configured to operate in response to a control command received from the device controller 110 via the interconnect INC of the system substrate 101. The memory package 120 may include a plurality of memory chips MC, at least one pair of buffer chips BF, and a package substrate 125. The buffer chips BF and the plurality of memory chips MC may be covered over the package substrate 125 by a protective layer 123. The protective layer 123 may encapsulate the plurality of memory chips MC and the buffer chips BF and may include an insulating material (such as epoxy molding compound EMC).

[0065] Multiple memory chips MC are divided into multiple groups G1 and G2 and connected to a buffer chip BF. The buffer chip BF can allocate channels to the multiple groups G1 and G2 to facilitate signal transmission and reception between the device controller 110 and the multiple memory chips MC. As an example, the memory chips MC in the first group G1 and the second group G2 can be connected to the first buffer chip 121 and the second buffer chip 122, respectively. The memory chips MC in each of the multiple groups G1 and G2 can be stacked on top of each other and connected to each other via leads W1 and W2. The semiconductor chip in the first group G1 can be connected to the first buffer chip 121 via the first lead W1, and the semiconductor chip in the second group G2 can be connected to the second buffer chip 122 via the second lead W2. However, according to an embodiment, the memory chips MC included in each of the multiple groups G1 and G2 can be connected to each other via through interconnects (such as through-silicon vias) instead of leads.

[0066] The buffer chip BF can be a chip that facilitates signal exchange between the device controller 110 and the memory chip MC. For example, the buffer chip BF can be used as an intermediary for signal exchange between the device controller 110 and the memory chip MC. The buffer chip BF can be connected to the device controller 110 and multiple memory chips MC, and is configured to output control commands received from the device controller 110 to multiple memory chips MC. The buffer chip BF can be connected to the device controller 110 and the memory chip MC via controller connection pad PAD1 and memory connection pad PAD2. The controller connection pad PAD1 and memory connection pad PAD2 can be connected to the first upper bonding pad BP1a and the second upper bonding pad BP1b via a third lead W3. In some embodiments, the buffer chip BF can be flip-chip bonded to the package substrate 125. The buffer chip BF can select at least one of the multiple memory connection pads PAD2 according to commands from the device controller 110. For example, the device controller 110 may send address signals to the controller connection pad PAD1 of the buffer chip BF for selecting at least some of the memory chips MC included in the first group G1 and / or at least some of the memory chips MC included in the second group G2. Based on the address signals, the buffer chip BF may select the memory connection pad PAD2 and send data to or receive data output by the memory chips.

[0067] Package substrate 125 may include bonding pads BP1 and BP2 and connectors RDL. Connectors RDL are electrically connected to buffer chip BF, memory chip MC, and device controller 110 via upper bonding pad BP1 and lower bonding pad BP2. Connectors RDL provide signal paths between the external device controller 110 and buffer chip BF, and / or between buffer chip BF and memory chip MC. Some of the connectors RDL (e.g., first connector RDL1) connect a first upper bonding pad BP1a to lower bonding pad BP2 and provide signal paths for exchanging signals between the external device controller 110 and buffer chip BF via package bumps 128. First connector RDL1 provides a signal path between device controller 110 and buffer chip BF. Some of the connectors RDL (e.g., second connector RDL2) connect a second upper bonding pad BP1b to memory chip MC and provide signal paths for exchanging signals between memory chip MC and buffer chip BF. Second connector RDL2 provides a signal path between buffer chip BF and memory chip MC.

[0068] Encapsulation bump 128 may be formed on lower bonding pad BP2. Encapsulation bump 128 can be connected to chip pad 110P and chip bump 118 of device controller 110 via interconnect pad 101P and interconnect INC of system substrate 101. Second connector RDL2 may be electrically decoupled from encapsulation bump 128. Second connector RDL2 may connect memory chip MC in memory package 120 to corresponding buffer chip BF. Therefore, second connector RDL2 may not be electrically connected to encapsulation bump 128, which connects memory package 120 to system substrate 101 and other components mounted on system substrate 101 (such as device controller 110).

[0069] According to an example embodiment, the memory package 120 may include buffer chips BF corresponding to groups G1 and G2 of the memory chip MC, respectively. Buffer chips BF mounted in one memory package 120 can communicate with the device controller 110 via the same (same) channel and can be arranged adjacently such that the controller connection pads PAD1 of the buffer chips BF face each other. For example, two memory packages 120 mounted on the system substrate 101 can communicate with the device controller 110 via a first channel CH1 and a second channel CH2, respectively. For example, a pair of buffer chips BF embedded in one of the two memory packages 120 can communicate with the device controller 110 via the first channel CH1, and a pair of buffer chips BF embedded in the other of the two memory packages 120 can communicate with the device controller 110 via the second channel CH2. Therefore, the branch line length of the signal transmission path (single channel) between the device controller 110 and the buffer chips BF can be reduced, and signal reflection and RC delay can be minimized.

[0070] For example, the memory package 120 may include a first buffer chip 121 and a second buffer chip 122. The first buffer chip 121 facilitates signal exchange between the memory chips of the first group G1 and the device controller 110, and the second buffer chip 122 facilitates signal exchange between the memory chips of the second group G2 and the device controller 110. The first buffer chip 121 and the second buffer chip 122 may be connected to a first connector RDL1 via a first upper bonding pad BP1a disposed between the first buffer chip 121 and the second buffer chip 122 in an upper bonding pad BP1. The first buffer chip 121 may send a first control signal, branching from the control command signal at the branch point DP, to the first group G1, and the second buffer chip 122 may send a second control signal, branching from the control command signal at the branch point DP, to the second group G2, the control command signal being received from the device controller 110.

[0071] The first connector RDL1 may include a main path MP (i.e., a main signal line) and a branch path STP (i.e., a branch signal line). The main path MP may be provided by the interconnect INC of the system substrate 101 and the connector RDL of the package substrate 125. The main path MP may extend from the device controller 110 into the interior of the package substrate 125. The main path MP may have one end (“branch point”) DP, at which control commands generated from the device controller 110 are branched into a pair of buffer chips BF. The branch point DP may be located on the connector RDL of the package substrate 125. The branch path STP may be connected to a first upper bonding pad BP1a between the pair of buffer chips BF. The branch path STP connects the pair of buffer chips BF to the device controller 110. The branch path STP may be located between two sides S1 of the pair of buffer chips BF facing each other, or between two sides S2 of the pair of buffer chips BF opposite to said side S1. In an embodiment, the branch line path STP connected to each of the first buffer chip 121 and the second buffer chip 122 may be formed only between a pair of buffer chips BF.

[0072] In an embodiment, the branch path STP may include a horizontal portion HS and a vertical portion VS. The horizontal portion HS may extend horizontally from the branch point DP and may have opposite ends respectively connected to the corresponding first upper engagement pad BP1a. The vertical portion VS may extend vertically from the opposite end of the horizontal portion HS to the corresponding first upper engagement pad BP1a. In some embodiments, the branch path STP may include only the horizontal portion HS ( Figure 10 (Example). The opposite ends of the horizontal section HS may be located at the same vertical level. The main path MP may include a lower horizontal section LHS located below the horizontal section HS of the branch path STP, and a lower vertical section LVS connecting the lower horizontal section LHS of the main path MP to the horizontal section HS of the branch path STP. The branch point DP of the main path MP may be defined as the contact area between the lower vertical section LVS and the horizontal section HS (i.e., the contact area where the lower vertical section LVS connects to or contacts the horizontal section HS). The branch point DP may be located in the middle of the opposite ends of the horizontal section HS. For example, the length of the branch path STP from the branch point DP to the corresponding first upper mating pad BP1a may be constant. For example, when viewed in a plan view, the length of the branch path between the branch point DP and one of the corresponding first upper mating pads BP1a may be the same as the length of the branch path between the branch point DP and the other of the corresponding first upper mating pads BP1a.

[0073] Figure 6 This is a schematic diagram of the appearance of the storage device 100B according to an example embodiment.

[0074] Reference Figure 6Except that memory packages (e.g., NAND flash memory) 120A and 120B are mounted on both sides of the system substrate 101, the storage device 100B of the example embodiment may have the same characteristics as the referenced one. Figure 4 The described features are the same or similar. Storage device 100B may be a solid-state drive (SSD), as described in the reference. Figure 4 The described embodiments are similar. The storage device 100B can communicate with an external central processing unit, system-on-a-chip, or application processor, and the form factor of the storage device 100B and the protocol used for communicating with external devices can be modified differently.

[0075] Storage device 100B may include system substrate 101, connector pins 102 and component elements 103 formed on system substrate 101, device controller 110 mounted on system substrate 101, memory packages 120A and 120B, or DRAM 130 and PMIC 140.

[0076] The capacity of storage device 100B can be increased by mounting memory packages 120A and 120B on both sides of system substrate 101. According to an example embodiment, each of memory packages 120A and 120B may also include at least one pair of buffer chips. Hereinafter, this will be referred to... Figure 7A and Figure 7B It is described in more detail.

[0077] Figure 7A and Figure 7B These are cross-sectional side views of storage devices 100B and 100B' according to the example embodiment.

[0078] Reference Figure 7A Except that memory packages 120A and 120B are mounted on opposite sides (e.g., upper and lower surfaces) of system substrate 101, the storage device 100B of the example embodiment may have the same characteristics as the referenced one. Figure 5 The described features are the same or similar. The storage device 100B of the example embodiment may include at least one first memory package 120A and at least one second memory package 120B respectively mounted on opposite sides of the system substrate 101. The storage device 100B may also include a device controller 110 and the system substrate 101.

[0079] System substrate 101 may include a first interconnect pad 101P1, a second interconnect pad 101P2, and an interconnect INC. The interconnect INC can be connected to device controller 110 and memory packages 120A and 120B via interconnect pads 101P1 and 101P2. Device controller 110 can be mounted on the first interconnect pad 101P1 via chip bumps 118, and the first memory package 120A and the second memory package 120B can be mounted on the first interconnect pad 101P1 and the second interconnect pad 101P2 via package bumps 128, respectively. Device controller 110 and memory packages 120A and 120B can be electrically connected to each other via the interconnect INC formed within system substrate 101 to exchange signals. The interconnect INC may include interconnect pattern portions and interconnect via portions made of conductive material.

[0080] Device controller 110 and memory packages 120A and 120B can be electrically connected to each other via interconnects INC of system substrate 101 to exchange signals. According to an example embodiment, device controller 110 can communicate with memory packages 120A and 120B, each including multiple buffer chips BF, via a single channel. For example, device controller 110 can communicate with first memory package 120A via a first channel CH1 provided by first interconnect INC1, and with second memory package 120B via a second channel CH2 provided by second interconnect INC2. Therefore, the branch path length of the channel can be reduced, and the SI (signal integrity) characteristics of the memory device can be improved.

[0081] Memory packages 120A and 120B may have the same construction. Memory packages 120A and 120B may include a plurality of memory chips MC, at least a pair of buffer chips BF, and a package substrate 125. The buffer chips BF and the plurality of memory chips MC may be covered over the package substrate 125 by a protective layer 123.

[0082] Multiple memory chips MC can be divided into multiple groups G1 and G2 and connected to a buffer chip BF including a first buffer chip 121 and a second buffer chip 122. The buffer chip BF can allocate channels to the multiple groups G1 and G2 to facilitate signal transmission and reception between the device controller 110 and the multiple memory chips MC. As an example, the memory chips MC of the first group G1 and the second group G2 can be connected to the first buffer chip 121 and the second buffer chip 122, respectively. In each of the multiple groups G1 and G2, the memory chips MC can be stacked vertically on top of each other and connected to each other via leads W1 and W2. The semiconductor chip of the first group G1 can be connected to the first buffer chip 121 via the first lead W1, and the semiconductor chip of the second group G2 can be connected to the second buffer chip 122 via the second lead W2. However, according to an embodiment, the memory chips MC included in each of the multiple groups G1 and G2 can be connected to each other via through interconnects (such as through-silicon vias) instead of leads.

[0083] The buffer chip BF can be a chip that facilitates signal exchange between the device controller 110 and the memory chip MC. The buffer chip BF can be connected to the upper bonding pad BP1 via a third lead W3. In some embodiments, the buffer chip BF can be flip-chip bonded to the package substrate 125. The buffer chip BF can be electrically connected to the external device controller 110 via a first connector RDL1 to exchange signals. The first connector RDL1 provides a signal path between the device controller 110 and the buffer chip BF. A second connector RDL2 provides a signal path between the buffer chip BF and the memory chip MC.

[0084] According to an example embodiment, memory packages 120A and 120B may include a pair of buffer chips BF corresponding to respective groups G1 and G2 of the memory chip MC. The buffer chip BF mounted in the first memory package 120A can communicate with the device controller 110 via a first channel CH1. The buffer chip BF mounted in the second memory package 120B can communicate with the device controller 110 via a second channel CH2. Therefore, the branch line length in the signal transmission path (single channel) between the device controller 110 and the buffer chip BF can be reduced, and signal reflection and RC delay can be minimized.

[0085] Each of the memory packages 120A and 120B may include a first buffer chip 121 facilitating signal exchange between the memory chips of the first group G1 and the device controller 110, and a second buffer chip 122 facilitating signal exchange between the memory chips of the second group G2 and the device controller 110. The first buffer chip 121 and the second buffer chip 122 may be connected to a first connector RDL1 via some of the components disposed between the first buffer chip 121 and the second buffer chip 122 in the upper bonding pad BP1. The branch path of the first connector RDL1 may be formed only between a pair of buffer chips BF.

[0086] Reference Figure 7B Except that the memory packages 120A and 120B mounted on opposite sides (e.g., upper and lower surfaces) of the system substrate 101 are connected to the same channel, the storage device 100B' of the example embodiment may have the same characteristics as the referenced one. Figure 7A The described features are the same or similar. The interconnect INC of system substrate 101 can be connected to device controller 110 and memory packages 120A and 120B via interconnect pads 101P1 and 101P2. Device controller 110 and memory packages 120A and 120B can be electrically connected to each other via interconnect INC formed within system substrate 101 to exchange signals. According to an example embodiment, device controller 110 can communicate with first memory package 120A and second memory package 120B via a single channel. For example, device controller 110 can communicate with first memory package 120A and second memory package 120B via a first channel CH1 provided by interconnect INC. First memory package 120A and second memory package 120B can communicate with device controller 110 using the same single channel (e.g., first channel CH1). Therefore, the branch line path length of the channel can be reduced, and the SI (signal integrity) characteristics of the memory device can be improved. Therefore, when the branch points of the channel paths connecting the device controller 110 and the multiple buffer chips BF are formed inside the package substrate 125, and the gaps between the multiple buffer chips BF are minimized (i.e., the length of the branch path is minimized), the input / output speed between the device controller 110 and the memory packages 120A and 120B can be increased by approximately 10% or more compared to the case where the branch points of the channel paths are formed inside the system substrate 101.

[0087] Figure 8 This is a schematic diagram of the buffer chip BF according to an example embodiment.

[0088] Reference Figure 8In the example embodiment, the buffer chips BF can be arranged in at least one pair. For example, the buffer chips BF may include a first buffer chip 121 and a second buffer chip 122 arranged adjacent to each other in a first horizontal direction D1, which is parallel to the upper surface of the system substrate 101 or the upper surface of the package substrate 125. The first buffer chip 121 and the second buffer chip 122 can be connected to the connector RDL of the package substrate 125 via a first upper bonding pad BP1a arranged between the buffer chips BF.

[0089] The connector RDL provides a channel path CH between the buffer chip BF and the external device controller. The channel path CH may include a main path MP extending from the external device controller to a branch point DP between the buffer chips BF, and branch paths STP branching from the main path MP and connecting to the first buffer chip 121 and the second buffer chip 122. The main path MP and the branch paths STP may be provided by a connection pattern 125L and / or a connection via 125V on the package substrate 125. The channel path CH may include multiple main paths MP and multiple branch paths STP, and the multiple branch paths STP may be spaced apart from each other in a second horizontal direction D2, which is parallel to the upper surface of the system substrate 101 or the upper surface of the package substrate 125. The second horizontal direction D2 may be perpendicular to the first horizontal direction D1.

[0090] In an embodiment, the branch path STP may include a horizontal portion HS provided by a connection pattern 125L and a vertical portion VS provided by a connection via 125V. The horizontal portion HS may extend horizontally from the branch point DP and may have opposite ends respectively connected to the corresponding first upper engagement pad BP1a. The vertical portion VS may extend vertically from the opposite ends of the horizontal portion HS to the corresponding first upper engagement pad BP1a. The opposite ends of the connection pattern 125L providing the horizontal portion HS may be located at the same vertical level. The main path MP may include a lower horizontal portion LHS provided by the connection pattern 125L and a lower vertical portion LVS provided by the connection via 125V. The branch point DP may be defined such that the lower vertical portion LVS connects to (or contacts) the contact area of ​​the horizontal portion HS. The branch point DP may be located at the middle of the connection pattern 125L providing the horizontal portion HS in the first horizontal direction D1. The length of the connecting pattern 125L for the horizontal portion HS can be constant or can be the same as each other, and the height of the connecting via 125V for the vertical portion VS extending from the opposite end of the horizontal portion HS to the first upper engagement pad BP1a can be constant or can be the same as each other.

[0091] A connection pattern 125L providing the horizontal portion HS may be located between the first buffer chip 121 and the second buffer chip 122. The first buffer chip 121 and the second buffer chip 122 may include a side facing each other in the first horizontal direction D1 (hereinafter referred to as the "inner surface") and another side facing away from said side (hereinafter referred to as the "outer surface"). The length L of the horizontal portion HS in the first horizontal direction D1 may be less than the distance d1 between the inner surfaces of the pair of buffer chips BF in the first horizontal direction D1, or the distance d2 between the outer surfaces of the pair of buffer chips BF in the first horizontal direction D1. The connection pattern 125L providing the horizontal portion HS may not overlap with the first buffer chip 121 and the second buffer chip 122 in the vertical direction D3, which is perpendicular to the upper surface of the package substrate 125. According to the example embodiment, the branch line length (length of the horizontal portion HS) in the signal transmission path (single channel) of the device controller 110 and the buffer chip BF can be reduced, and signal reflection and RC delay can be minimized.

[0092] In an example embodiment, one of a pair of buffer chips BF may be configured to mirror data signals from an external device controller transmitted via channel path CH. The pair of buffer chips BF may be adjacent, such that corresponding sides of their arranged controller connection pads PAD1 face each other. When a pair of buffer chips BF have the same arrangement of controller connection pads PAD1, the arrangement order of the controller connection pads PAD1 facing each other can be reversed. For example, the first buffer chip 121 has a pad configuration of controller connection pads PAD1 in the order of data pads DQ1, DQ2, DQS, DQ3, and DQ4, while the second buffer chip 122 has a pad configuration of controller connection pads PAD1 in the reverse order of data pads DQ4, DQ3, DQS, DQ2, and DQ1. In this case, the routing length can be increased to match the order of the data pads. However, according to one embodiment, one of the buffer chips BF can be configured to mirror the data signal path (i.e., the pad configuration of the controller connection pad PAD1 and the signal path connected thereto), such that each of the first buffer chip 121 and the second buffer chip 122 has data pads DQ1, DQ2, DQS, DQ3, and DQ4 in the same order. This mirrored signal path simplifies the routing design between the first upper bonding pads BP1a arranged in two rows, and thus shortens the branch path STP of the channel path CH. In other words, the arrangement of the controller connection pads PAD1 of the first buffer chip 121 and the second buffer chip 122 can be mirror-symmetric with respect to the space between the first buffer chip 121 and the second buffer chip 122.

[0093] A pair of buffer chips (BF) can be designed such that the controller connection pad (PAD1) is symmetrical with respect to the data strobe signal pins (e.g., data pad DQS) and data pins (e.g., data pads DQ1, DQ2, DQ3, and DQ4) that require high-speed operation. For example, power pins, ground pins, chip enable pins, command latch enable pins, address latch enable pins, write enable pins, read enable pins, ready busy pins, or select pins can be arranged symmetrically with respect to the data strobe signal pins (e.g., data pad DQS) and data pins (e.g., data pads DQ1, DQ2, DQ3, and DQ4).

[0094] For example, when the first buffer chip 121 is positioned at 0 degrees and the second buffer chip 122 is positioned at 180 degrees, the order of the data pins (e.g., data pads DQ1, DQ2, DQ3, and DQ4) of the first buffer chip 121 and the second buffer chip 122 (e.g., data pads DQ1, DQ2, DQ3, and DQ4) can be reversed. The second buffer chip 122 may have a DQ mirroring function that swaps bit 0 with 7, bit 1 with 6, bit 2 with 5, and bit 3 with 4. The second buffer chip 122 may form a mirror signal of the data signal input from an external device controller. This disclosure is not limited thereto. In embodiments, for signal integrity, the second buffer chip 122 may have a physical layout and signal routing that mirrors the first buffer chip 121. The second buffer chip 122 does not have a DQ mirroring function.

[0095] Figure 9 This is a cross-sectional side view of the memory package 120a according to an example embodiment.

[0096] Reference Figure 9 The memory package 120a of the example embodiment may include a plurality of memory chips MC, a plurality of buffer chips BF, and a package substrate 125. The plurality of buffer chips BF and the plurality of memory chips MC may be covered over the package substrate 125 by a protective layer 123.

[0097] Multiple memory chips MC can be vertically stacked on a package substrate 125 in a stepped shape. The multiple memory chips MC can be divided into multiple groups G1 and G2 and respectively connected to multiple buffer chips BF, and the multiple buffer chips BF can each allocate channels to multiple groups G1 and G2 to facilitate signal transmission and reception with an external device controller. As an example, the memory chips MC of the first group G1 and the second group G2 can be connected to the first buffer chip 121 and the second buffer chip 122, respectively. The semiconductor chip of the first group G1 can be connected to the first buffer chip 121 via a first lead W1, and the semiconductor chip of the second group G2 can be connected to the second buffer chip 122 via a second lead W2. In some embodiments, the first lead W1 and the second lead W2 can be directly connected to the memory access pad of the buffer chip BF without passing through the second connector RDL2.

[0098] Multiple buffer chips (BF) can respectively facilitate signal exchange between the memory chips (MC) of corresponding groups G1 and G2 and the device controller 110. The multiple buffer chips (BF) can activate at least some of the multiple memory chips (MC) based on address information received from the external device controller. For example, the first group G1 may include a first memory chip set MCS1 and a second memory chip set MCS2, and the second group G2 may include a third memory chip set MCS3 and a fourth memory chip set MCS4. The first buffer chip 121 can activate or deactivate the first memory chip set MCS1 and / or the second memory chip set MCS2 of the first group G1 based on address information received from the external device controller. The second buffer chip 122 can activate or deactivate the third memory chip set MCS3 and / or the fourth memory chip set MCS4 of the second group G2 based on address information received from the external device controller.

[0099] Multiple buffer chips (BF) can be electrically connected to the memory chip (MC) and the external device controller via connectors (RDL). The first connector (RDL1) connects the first upper bonding pad (BP1a) and the lower bonding pad (BP2) and provides the main path (MP) and branch path (STP). The external device controller and the multiple buffer chips (BF) exchange signals via package bumps (128) through the main path (MP) and branch path (STP).

[0100] The branch path STP may include a horizontal portion HS provided by the connection pattern 125L and a vertical portion VS provided by the connection via 125V. The horizontal portion HS may extend horizontally from the branch point DP and has opposite ends that are respectively connected to the corresponding first upper engagement pad BP1a. The vertical portion VS may extend vertically from the opposite ends of the horizontal portion HS to the corresponding first upper engagement pad BP1a. The opposite ends of the connection pattern 125L providing the horizontal portion HS may be located at the same vertical level. The main path MP may include a lower horizontal portion LHS provided by the connection pattern 125L and a lower vertical portion LVS provided by the connection via 125V. The branch point DP may be defined such that the lower vertical portion LVS connects to (or contacts) the contact area of ​​the horizontal portion HS. The branch point DP may be located in the middle of the connection pattern 125L providing the horizontal portion HS.

[0101] The connection pattern 125L providing the horizontal portion HS can be located between the first buffer chip 121 and the second buffer chip 122. The connection pattern 125L providing the horizontal portion HS can be non-overlapping with the first buffer chip 121 and the second buffer chip 122 in the vertical direction D3. According to the example embodiment, the branch line length (length of the horizontal portion HS) in the signal transmission path (single channel) of the device controller 110 and the buffer chip BF can be reduced, and signal reflection and RC delay can be minimized.

[0102] Figure 10 This is a cross-sectional side view of the memory package 120b according to an example embodiment.

[0103] Reference Figure 10 Apart from the branch path STP, the memory package 120b of the example embodiment may have the same characteristics as the referenced one. Figure 9 The described features are the same or similar. The branch line path STP may consist only of the horizontal portion HS provided by the connection pattern 125L. The branch line path STP may be located at the same vertical level as the first upper engagement pad BP1a. The branch line path STP may overlap with the first upper engagement pad BP1a in the first horizontal direction D1. The branch line path STP may extend horizontally from the branch point DP and have opposite ends that respectively contact the corresponding first upper engagement pad BP1a. The opposite ends of the horizontal portion HS that contact the first upper engagement pad BP1a may be located at the same vertical level. Therefore, the length of the branch line path STP can be minimized, and the SI characteristics can be further improved.

[0104] Figure 11 This is a cross-sectional side view of the memory package 120c according to an example embodiment.

[0105] Reference Figure 11 In addition to the flip-chip bonding of the buffer chip BF, the memory package 120c of the example embodiment may have the same characteristics as the referenced one. Figure 9 and Figure 10 The described features are the same or similar. The buffer chip BF can be connected to the connector RDL via conductive bumps SB. The conductive bumps SB can be arranged between the controller connection pad PAD1 and the first upper bonding pad BP1a, and between the memory connection pad PAD2 and the second upper bonding pad BP1b. Branch path STPs can be formed between the outer surfaces of the buffer chip BF. The branch path STPs can be partially superimposed on the first buffer chip 121 and the second buffer chip 122 in the vertical direction D3, respectively. The connection pattern 125L providing the horizontal portion HS of the branch path STPs can extend longer than the distance between the inner surfaces of the first buffer chip 121 and the second buffer chip 122.

[0106] Figure 12 This is a cross-sectional side view of the memory package 120d according to an example embodiment.

[0107] Reference Figure 12 In addition to the stacked configuration of multiple memory chips (MCs), the memory package 120d of the example embodiment may have the same configuration as the referenced one. Figures 9 to 11 The described features are the same or similar. Multiple memory chips MC can be stacked on at least one pair of buffer chips BF in a vertical direction perpendicular to the upper surface of the package substrate 125. For example, memory chips of a first group G1 and a second group G2 can be stacked vertically on a first buffer chip 121 and a second buffer chip 122. The memory chips MC of the first group G1 and the second group G2 can be stacked in a stepped shape with steps between them, such that each chip pad is exposed. The first group G1 can be connected to a second upper bonding pad BP1b via a first lead W1, and the second group G2 can be connected to the second upper bonding pad BP1b via a second lead W2. A first memory chip set MCS1 and a second memory chip set MCS2 can be arranged such that each chip pad faces away from each other. A third memory chip set MCS3 and a fourth memory chip set MCS4 can be arranged such that each chip pad faces away from each other.

[0108] Figure 13 This is a cross-sectional side view of the memory package 120e according to an example embodiment.

[0109] Reference Figure 13 In addition to the stacked configuration of multiple memory chips (MCs), the memory package 120e of the example embodiment may have the same configuration as the referenced one. Figures 9 to 12The described features are the same or similar. The memory chips MC in each of the first group G1 and the second group G2 can be stacked without steps between them. The memory chips MC can be arranged such that each chip pad is stacked with another memory chip MC that is vertically adjacent to it. The memory chips MC can be interconnected via through-silicon vias (TSVs) instead of leads. Figure 2 Unlike the through-silicon via (TSV) shown, the memory chips MC in the first group G1 are interconnected via TSVs and connected to the second connector RDL2 via a first lead W1. The memory chips MC in the second group G2 are interconnected via TSVs and connected to the second connector RDL2 via a second lead W2.

[0110] Figure 14 This is a cross-sectional side view of the memory package 120f according to an example embodiment.

[0111] Reference Figure 14 Apart from the connection method between the memory chip MC and the connector RDL, the memory package 120f of the example embodiment may have the same characteristics as the referenced method. Figures 9 to 13 The described features are the same or similar. The memory chip MC can be connected to the second connector RDL2 without leads. The memory chips of the first group G1 and the second group G2 can be interconnected via through-silicon vias (TSVs) and directly connected to the second upper bonding pad BP1b. The signal path between the memory chip MC and the buffer chip BF can be shortened.

[0112] Figure 15 This is a cross-sectional side view of the memory package 120g according to an example embodiment.

[0113] Reference Figure 15 Apart from the number of buffer chips BF, the memory package 120g of the example embodiment may have the same characteristics as the reference. Figures 9 to 14 The described features are the same or similar. The memory package 120g may include a first pair of buffer chips BF1 and a second pair of buffer chips BF2, each of the first pair of buffer chips BF1 and the second pair of buffer chips BF2 consisting of a pair of buffer chips BF. The first pair of buffer chips BF1 and the second pair of buffer chips BF2 can be configured with... Figure 8The connector RDL is connected to the package substrate 125 in a manner similar to that described in the figure. Each of the first pair of buffer chips BF1 and the second pair of buffer chips BF2 may include a first buffer chip 121 and a second buffer chip 122, which are respectively connected to an external device controller via the same channel. Therefore, the memory package of the example embodiment may include a greater number of buffer chips BF and memory chips MC than shown in the figures.

[0114] According to an embodiment of the example embodiment, a memory package and storage device may be provided that uses multiple buffer chips to efficiently connect multiple memory chips.

[0115] The various advantages and benefits of the example embodiments are not limited to those described above, and will be more readily understood in the process of explaining specific embodiments of the example embodiments.

[0116] However, the effects of the exemplary embodiments are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of the exemplary embodiments.

[0117] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the exemplary embodiments as defined by the appended claims.

Claims

1. A memory package, comprising: Packaging substrate; Multiple memory chips are disposed on the upper surface of a package substrate and are divided into a first group of memory chips stacked in a vertical direction perpendicular to the upper surface of the package substrate and a second group of memory chips stacked in a vertical direction, wherein the first group of memory chips is spaced apart from the second group of memory chips in a first horizontal direction parallel to the upper surface of the package substrate. A first buffer chip, disposed on the upper surface of the package substrate, is configured to: output control command signals received from an external memory controller to a first set of memory chips; and A second buffer chip is disposed on the upper surface of the package substrate and configured to output control command signals to a second set of memory chips. The first and second buffer chips are disposed in the space between the first and second sets of memory chips and arranged in a first horizontal direction. The packaging substrate includes: The main path, through which control command signals are sent from the external memory controller, and The branch path connects the main path to each of the first and second buffer chips. The branch path is configured such that the control command signal received from the main path branches to the first buffer chip and the second buffer chip, and When viewed in a plan view, the branch line path is set in the space between the first buffer chip and the second buffer chip.

2. The memory package according to claim 1, in, The branch line path includes a horizontal portion extending in the first horizontal direction. The opposite ends of the horizontal section are respectively connected to the first buffer chip and the second buffer chip, and The length of the horizontal portion in the first horizontal direction is less than the distance between the first buffer chip and the second buffer chip in the first horizontal direction.

3. The memory package according to claim 2, in, The end of the main path is connected to the opposite end of the horizontal section at the middle in the first horizontal direction.

4. The memory package according to claim 1, further comprising: A plurality of first upper bonding pads are arranged in a second horizontal direction, parallel to the upper surface of the package substrate and perpendicular to a first horizontal direction, wherein the plurality of first upper bonding pads are connected to a branch line path; and A plurality of second upper engagement pads are arranged in a second horizontal direction, wherein the plurality of second upper engagement pads are connected to the branch line path. When viewed in a plan view, the plurality of first upper bonding pads and the plurality of second upper bonding pads are disposed in the space between the first buffer chip and the second buffer chip. The first buffer chip is connected to the branch line path via the plurality of first upper bonding pads, and The second buffer chip is connected to the branch line path via the plurality of second upper bonding pads.

5. The memory package according to claim 1, in, The first buffer chip includes: Multiple first controller connection pads, connected to an external memory controller, are arranged in a second horizontal direction parallel to the upper surface of the package substrate and perpendicular to a first horizontal direction; and Multiple first memory connection pads are connected to a first group of memory chips and are arranged in a second horizontal direction. When viewed in a plan view, the plurality of first controller connection pads are disposed between the space between the first buffer chip and the second buffer chip and between the plurality of first memory connection pads.

6. The memory package according to claim 5, in, The first buffer chip is configured to receive control command signals through the plurality of first controller connection pads.

7. The memory package according to claim 6, in, The second buffer chip includes: Multiple second controller connection pads, connected to an external memory controller, and arranged in a second horizontal direction; and Multiple second memory connection pads are connected to a second set of memory chips and are arranged in a second horizontal direction. When viewed in a plan view, the plurality of second controller connection pads are disposed between the space between the first buffer chip and the second buffer chip and between the plurality of second memory connection pads. The second buffer chip receives control command signals from the plurality of second controller connection pads. The plurality of first controller connection pads and the plurality of second controller connection pads are disposed in the space between the plurality of first memory connection pads and the plurality of second memory connection pads. In this configuration, one of the first buffer chip and the second buffer chip is configured to mirror the data signal in response to a received control command signal, and The first buffer chip and the second buffer chip have mirror-symmetrical signal paths connected to the plurality of first controller connection pads and the plurality of second controller connection pads.

8. The memory package according to claim 1, further comprising: The system substrate, package substrate, and external memory controller are mounted on the system substrate.

9. The memory package according to claim 8, in, The system substrate includes multiple interconnects that are electrically connected to the main path of the package substrate.

10. The memory package according to claim 1, in, Branch path includes: The horizontal portion extends in the first horizontal direction; and A pair of vertical parts, standing vertically from the horizontal part. The pair of vertical portions are respectively connected to the first buffer chip and the second buffer chip, and The horizontal section is connected to the main path in the middle of the first horizontal direction.

11. A storage device, comprising: The system base consists of multiple interconnect components; The memory controller is mounted on the system substrate; as well as At least one memory package is mounted on the system substrate and configured to operate in response to control command signals received from the memory controller via the plurality of interconnects. Wherein, the at least one memory package includes: Multiple memory chips; A pair of buffer chips, adjacent to each other in a first horizontal direction parallel to the upper surface of the system substrate, are connected to the memory controller and the plurality of memory chips, and are configured to output control command signals received from the memory controller to the plurality of memory chips; A package substrate includes a plurality of connectors and a plurality of upper bonding pads, the plurality of connectors being electrically connected to a plurality of interconnects, and the plurality of upper bonding pads being between and electrically connected to a pair of buffer chips, wherein the plurality of memory chips and the pair of buffer chips are mounted on the package substrate; and A protective layer encapsulates the plurality of memory chips and the pair of buffer chips. The pair of buffer chips are connected to the memory controller via a single channel provided by the plurality of interconnects and connectors. Each channel includes a main path and branch paths. The main path connects to the memory controller, and the branch paths extend from one end of the main path located between the pair of buffer chips and connect to each of the pair of buffer chips. The branch path includes a horizontal portion that extends from one end of the main path in a first horizontal direction and has opposite ends that are respectively connected to corresponding upper engagement pads among the plurality of upper engagement pads. Wherein, one end of the main path is connected to the middle of the opposite end of the horizontal portion of the branch path in the first horizontal direction, and Among them, the opposite ends of the horizontal part of the branch line path are at the same vertical level in the vertical direction perpendicular to the upper surface of the system base.

12. The storage device according to claim 11, in, The pair of buffer chips includes one side facing each other in a first horizontal direction and another side facing away from said side, and Wherein, the length of the horizontal portion of the branch line path in the first horizontal direction is less than the distance between the two sides in the first horizontal direction or the distance between the two sides in the first horizontal direction.

13. The storage device according to claim 11, in, The main path includes a lower horizontal section and a lower vertical section. The lower horizontal section is located below the horizontal section of the branch path, and the lower vertical section extends vertically and connects the lower horizontal section to the horizontal section of the branch path. The main path is located at the upper end of the lower vertical section that contacts the horizontal section of the branch path.

14. The storage device according to claim 13, in, The plurality of connectors include a connecting pattern and a connecting through hole, the connecting pattern providing a horizontal portion and a lower horizontal portion, and the connecting through hole providing a lower vertical portion.

15. The storage device according to claim 11, in, A single channel includes multiple main paths and multiple branch paths extending from the main paths, and The plurality of branch line paths include a plurality of horizontal sections, which are spaced apart from each other in a second horizontal direction that is parallel to the upper surface of the system base and perpendicular to the first horizontal direction.

16. The storage device according to claim 11, in, The branch line path also includes a pair of vertical sections that extend vertically from opposite ends of the horizontal sections to a corresponding pair of upper engagement pads among the plurality of upper engagement pads.

17. The storage device according to claim 11, in, The horizontal portion of the branch line path is located at the same vertical level as the plurality of upper joint pads in the vertical direction, and The horizontal portion includes opposite ends that contact the corresponding upper engagement pad among the plurality of upper engagement pads.

18. The storage device according to claim 11, in, The pair of buffer chips includes a first buffer chip and a second buffer chip. The plurality of memory chips includes a first group of memory chips connected to a first buffer chip and a second group of memory chips connected to a second buffer chip. Specifically, the first buffer chip sends a first control signal to the first group of memory chips. The first control signal branches off from the control command signal at the contact area where the main path connects to the branch path. The second buffer chip will send the second control signal from the control command signal branch to the second set of memory chips at the contact area.

19. A storage device, comprising: System base; The memory controller is mounted on the system substrate; as well as At least one memory package is mounted on the system substrate and configured to operate in response to a control command signal received from the memory controller. Wherein, the at least one memory package includes: Multiple memory chips; A pair of buffer chips, arranged adjacent to each other, are connected to a memory controller and the plurality of memory chips, and are configured to output control command signals received from the memory controller to the plurality of memory chips; and The packaging substrate includes a pair of upper bonding pads electrically connected to the pair of buffer chips. The plurality of memory chips and the pair of buffer chips are mounted on a package substrate. The pair of buffer chips are connected to the memory controller via a main path extending from the memory controller and a branch path extending from the main path. The branch line path contacts the pair of upper bonding pads between the pair of buffer chips.

20. The storage device according to claim 19, in, The branch point where the branch path connects to the main path is located within the package substrate, and The length of the branch line path from the branch point to one of the upper mating pads in the pair is the same as the length of the branch line path from the branch point to the other upper mating pad in the pair.

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