Integrated chip, electronic device, and data processing method

Abstract

The application discloses an integrated chip, an electronic device and a data processing method. The integrated chip comprises a volatile memory chip, a non-volatile memory chip and a logic chip. The logic chip is three-dimensionally bonded with the volatile memory chip. The non-volatile memory chip is arranged on one side of the logic chip and the volatile memory chip and is connected with the logic chip. The thickness of the non-volatile memory chip is less than or equal to the sum of the thicknesses of the volatile memory chip and the logic chip. In this way, the thickness of the integrated chip can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to an integrated chip, an electronic device, and a data processing method. BACKGROUND

[0002] With the rapid growth of application computing scale, the bandwidth and energy consumption overhead of storage access become important factors limiting the development of scale computing circuits. In the related art, different storage media are combined by using 2D packaging technology.

[0003] The disadvantage is that the inventor has found through long-term research that the combination of the related art only has advantages in area and cost over independent storage media. SUMMARY

[0004] The present application provides an integrated chip, an electronic device, and a data processing method, which can reduce the thickness of the integrated chip.

[0005] In a first aspect, the present application provides an integrated chip, comprising: a volatile memory chip; a non-volatile memory chip; a logic chip, the logic chip being three-dimensionally bonded to the volatile memory chip; the non-volatile memory chip being disposed on one side of the logic chip and the volatile memory chip, and being connected to the logic chip; wherein the thickness of the non-volatile memory chip is less than or equal to the sum of the thicknesses of the volatile memory chip and the logic chip.

[0006] The logic chip comprises a first bonding surface, and the first bonding surface comprises a first transmission interface; the volatile memory chip comprises a second bonding surface, and the second bonding surface comprises a second transmission interface; the first bonding surface and the second bonding surface are bonded to connect the logic chip and the volatile memory chip three-dimensionally, wherein the first transmission interface and the second transmission interface are connected one-to-one.

[0007] The logic chip comprises a first bonding surface, and the first bonding surface comprises a first transmission interface; the volatile memory chip comprises a second bonding surface, and the second bonding surface comprises a second transmission interface; the first bonding surface and the second bonding surface are bonded to connect the logic chip and the volatile memory chip three-dimensionally, wherein the first transmission interface and the second transmission interface are connected one-to-one.

[0008] The integrated chip further comprises: a rewiring layer disposed on one side of the first bonding surface of the logic chip; the first transmission interface and the second transmission interface are connected through the rewiring layer.

[0009] The integrated chip further includes a substrate arranged on the side of the redistribution layer away from the logic chip, and the substrate is provided with a third lead-out interface and a fourth lead-out interface on the side close to the redistribution layer; the first lead-out surface further includes a fifth lead-out interface and a sixth lead-out interface, the fifth lead-out interface is connected with the third lead-out interface, thereby forming a first logic interface on the substrate, and the first logic interface is used for data read and write of the volatile storage chip; the fourth lead-out interface is connected with the sixth lead-out interface, thereby forming a second logic interface on the substrate, and the second logic interface is used for data read and write of the non-volatile storage chip.

[0010] The volatile storage chip includes a first storage array; the non-volatile storage chip includes a second storage array; the logic chip includes a test repair unit connected with the first storage array and the second storage array, and used for test repair of the first storage array and / or the second storage array.

[0011] The first storage array includes a data cache array and a data storage array; the data cache array is used for storing write data received by the second logic interface; the data storage array is used for storing write data received by the first logic interface; when the available space of the data cache array is less than a threshold value, the data stored in the data cache array is migrated to the non-volatile storage chip.

[0012] The logic chip further includes a first controller connected with the first logic interface and the first transmission interface, and used for controlling read and write of the volatile storage chip; a second controller connected with the second logic interface and the first lead-out interface, and used for controlling read and write of the non-volatile storage chip; and a direct access module connected with the first controller and the second controller, and used for migrating the data stored in the data cache array to the non-volatile storage chip in cooperation with the first controller and the second controller.

[0013] In response to that the first logic interface receives a first data read instruction, the first controller performs a read operation on the data storage array based on the first data read instruction; in response to that the second logic interface receives a second data read instruction, the second controller and the direct access module perform a read operation on the data cache array based on the second data read instruction, and in response to that there is no data in the data cache array matching the second data read instruction, the second controller performs a read operation on the non-volatile storage chip based on the second data read instruction.

[0014] The logic chip further includes a multiplexer, one end of the multiplexer is connected with the first controller, the test repair unit, the other end is connected with the first storage array and the second storage array; or one end of the multiplexer is connected with the first controller, the test repair unit and the second controller, the other end is connected with the first storage array and the second storage array.

[0015] In a second aspect, the present application provides a data processing method applied to the integrated chip provided in the first aspect, the method comprising: in response to the second logic interface of the integrated chip receiving a data write instruction and corresponding write data; writing the write data into the data cache array of the volatile storage chip; in response to the available space of the data cache array being less than a threshold value, migrating the data stored in the data cache array to the non-volatile storage chip.

[0016] In the method, the method further comprises: in response to the first logic interface of the integrated chip receiving a first data read instruction, the first controller of the integrated chip performing a read operation on the data storage array based on the first data read instruction; or, in response to the second logic interface receiving a second data read instruction, the second controller of the integrated chip and the direct access module performing a read operation on the data cache array of the volatile storage chip based on the second data read instruction, and in response to there being no data matching the second data read instruction in the data cache array, the second controller performing a read operation on the non-volatile storage chip based on the second data read instruction.

[0017] In a third aspect, the present application provides an electronic device comprising the integrated chip provided in the first aspect.

[0018] The present application has the beneficial effect that: different from the prior art, the integrated chip, the electronic device and the data processing method provided by the present application take into account the problem that the thickness of the non-volatile storage chip is relatively large, and the logic chip and the volatile storage chip are connected in three dimensions, and the non-volatile storage chip is arranged on one side of the logic chip and the volatile storage chip, so that the thickness of the integrated chip is at most the sum of the thickness of the volatile storage chip and the thickness of the logic chip, thereby reducing the thickness of the integrated chip. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort. Among them:

[0020] Figure 1 is a structural schematic diagram of an embodiment of the integrated chip provided by the present application;

[0021] Figure 2 is a structural schematic diagram of another embodiment of the integrated chip provided by the present application;

[0022] Figure 3 is a structural schematic diagram of another embodiment of the integrated chip provided by the present application;

[0023] Figure 4 This is a schematic diagram of the structure of an embodiment of the first storage array provided in this application;

[0024] Figure 5 This is a schematic diagram of another embodiment of the integrated chip provided in this application;

[0025] Figure 6 This is a schematic diagram of another embodiment of the integrated chip provided in this application;

[0026] Figure 7 This is a schematic diagram of another embodiment of the integrated chip provided in this application;

[0027] Figure 8 This is a flowchart illustrating an embodiment of the data processing method provided in this application;

[0028] Figure 9 This is a flowchart illustrating another embodiment of the data processing method provided in this application;

[0029] Figure 10 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the integrated chip provided in this application. The integrated chip 100 includes: a volatile memory chip 10, a non-volatile memory chip 20, and a logic chip 30.

[0033] The logic chip 30 is three-dimensionally bonded with the volatile memory chip 10; the non-volatile memory chip 20 is arranged on one side of the logic chip 30 and the volatile memory chip 10, and is connected with the logic chip 30; the thickness d3 of the non-volatile memory chip 10 is less than or equal to the sum of the thickness d1 of the volatile memory chip and the thickness d2 of the logic chip. That is, d3 is less than or equal to the sum of d1 and d2.

[0034] In the embodiment, considering the problem of large thickness of the non-volatile memory chip 20, the logic chip 30 is three-dimensionally bonded with the volatile memory chip 10; the non-volatile memory chip 20 is arranged on one side of the logic chip 30 and the volatile memory chip 10, so that the integrated chip 100 has a thickness of at most the sum of the thickness d1 of the volatile memory chip and the thickness d2 of the logic chip, thereby reducing the thickness of the integrated chip 100.

[0035] In some embodiments, the data bit width of the volatile memory chip 10 is greater than the data bit width of the non-volatile memory chip 10. Thus, the volatile memory chip 10 can be used as internal storage to store relevant data, provide a larger data bit width, and improve the data read / write speed. The non-volatile memory chip 10 can be used as external storage to store relevant data.

[0036] In some embodiments, the non-volatile memory chip 20 can be NAND, and the volatile memory chip 10 can be DRAM (Dynamic Random Access Memory).

[0037] In addition to the bonding mode described above, there are other ways of three-dimensionally integrated structures of heterogeneous materials, such as epitaxial growth or transfer of sight system-level multifunctional integration. The structure integration of the present application can also be D2I (Die to Interposer, integrated on the adapter plate), D2W (Die to Wafer, integrated on the wafer), W2W (Wafer to Wafer, wafer stacking integration), etc.

[0038] Referring to Figure 2 , Figure 2 is a structural schematic diagram of another embodiment of the integrated chip provided by the present application. The integrated chip 100 includes a volatile memory chip 10, a non-volatile memory chip 20, and a logic chip 30. The volatile memory chip 10, the non-volatile memory chip 20, and the logic chip 30 are connected as shown in Figure 1 .

[0039] Specifically, the logic chip 30 comprises a first bonding surface 31 comprising a first transmission interface 311; the volatile storage chip 10 comprises a second bonding surface 11 comprising a second transmission interface 111, the first bonding surface 31 is bonded to the second bonding surface 11 to three-dimensionally bond the logic chip 30 to the volatile storage chip 10, wherein the first transmission interface 311 is connected to the second transmission interface 111 one by one.

[0040] By bonding the first bonding surface 31 to the second bonding surface 11 to three-dimensionally bond the logic chip 30 to the volatile storage chip 10, the first transmission interface 311 of the logic chip 30 is connected to the second transmission interface 111 of the volatile storage chip 10 one by one, and thus the logic chip 30 and the volatile storage chip 10 have the same data bit width.

[0041] Further, since the logic chip 30 and the volatile storage chip 10 are three-dimensionally bonded, data reading or data writing can be directly performed from the first storage array of the volatile storage chip 10, and thus it is not necessary to add relevant circuits for data bit width conversion between the logic chip 30 and the volatile storage chip 10, the circuit or data path for the logic to access the first storage array of the volatile storage chip 10 is improved or simplified, the access data bandwidth is greatly improved, and the power consumption and delay are reduced.

[0042] The logic chip 30 comprises a first lead-out surface 32 comprising a first lead-out interface 321; the non-volatile storage chip 20 comprises a second lead-out surface 21 comprising a second lead-out interface 211, the first lead-out interface 321 is connected to the second lead-out interface 211 one by one to connect the non-volatile storage chip 20 to the logic chip 30.

[0043] By connecting the first lead-out interface 321 to the second lead-out interface 211 one by one to connect the non-volatile storage chip 20 to the logic chip 30, the logic chip 30 and the non-volatile storage chip 20 have the same data bit width.

[0044] Further, since the first lead-out interface 321 is connected to the second lead-out interface 211 one by one, data reading or data writing can be directly performed from the second storage array of the non-volatile storage chip 20, and thus it is not necessary to add relevant circuits for data bit width conversion between the logic chip 30 and the non-volatile storage chip 20, the circuit or data path for the logic to access the second storage array of the non-volatile storage chip 20 is improved or simplified, the access data bandwidth is greatly improved, and the power consumption and delay are reduced.

[0045] Continuing to refer to Figure 2The integrated chip 100 further comprises: a redistribution layer 40 disposed on one side of the first lead-out surface 32 of the logic chip 30; the first lead-out interface 321 and the second lead-out interface 211 are connected through the redistribution layer 40.

[0046] With reference to Figure 2 The integrated chip 100 further comprises: a substrate 50 disposed on the side of the redistribution layer 40 away from the logic chip 30, and the substrate 50 is provided with a third lead-out interface 511 and a fourth lead-out interface 512 on the side close to the redistribution layer 40; the first lead-out surface 32 further comprises a fifth lead-out interface 322 and a sixth lead-out interface 323, the fifth lead-out interface 322 is connected with the third lead-out interface 511, thereby forming a first logic interface on the substrate 50, and the first logic interface is used for data read-write of the volatile storage chip 10; the fourth lead-out interface 512 is connected with the sixth lead-out interface 323, thereby forming a second logic interface on the substrate 50, and the second logic interface is used for data read-write of the non-volatile storage chip 20.

[0047] In the embodiment, considering the problem of large thickness of the non-volatile storage chip 10, the logic chip 30 and the volatile storage chip 10 are connected in three-dimensional bonding, and the non-volatile storage chip 20 is disposed on one side of the logic chip 30 and the volatile storage chip 10, so that the thickness of the integrated chip 100 is at most the sum of the thickness of the volatile storage chip and the thickness of the logic chip, thereby reducing the thickness of the integrated chip 100.

[0048] Further, the logic chip 30 and the volatile storage chip 10 are connected in three-dimensional bonding, and the first lead-out interface 321 and the second lead-out interface 211 are connected one by one, so that the logic chip 30 and the volatile storage chip 10 have the same data bit width. In addition, the logic chip 30 and the non-volatile storage chip 20 have the same data bit width, thereby eliminating the need to add related circuits for data bit width conversion between the logic chip 30 and the non-volatile storage chip 20 and between the logic chip 30 and the volatile storage chip 10, improving or simplifying the circuit or data path for accessing the non-volatile storage chip 20 and the volatile storage chip 10, greatly improving the access data bandwidth, and reducing power consumption and delay.

[0049] With reference to Figure 3 , Figure 3 is a structural schematic diagram of another embodiment of the integrated chip provided by the present application. The volatile storage chip 10 comprises a first storage array 12; the non-volatile storage chip 20 comprises a second storage array 22; the logic chip 30 comprises: a test repair unit 33 connected with the first storage array 12 and the second storage array 22, and used for testing and repairing the first storage array 12 and / or the second storage array 22.

[0050] With reference toFigure 4 , Figure 4 is a structural schematic diagram of an embodiment of the first storage array provided by the present application. The first storage array 12 comprises a data cache array 121 and a data storage array 122; the data cache array 121 is used to store the write data received by the second logical interface; the data storage array 122 is used to store the write data received by the first logical interface; wherein when the available space of the data cache array 121 is less than a threshold value, the data stored in the data cache array 121 is migrated to the non-volatile storage chip 20. In some embodiments, the capacity of the data cache array 121 is set to 16MB, and when the data stored in the data cache array 121 exceeds a preset proportion, such as 50%, 55%, 60% or 65%, it indicates that the available space of the data cache array 121 is insufficient, and then the data stored in the data cache array 121 is migrated to the non-volatile storage chip 20, so as to release the storage space of the data cache array 121.

[0051] In the present embodiment, considering that the number of erasing and writing times of the non-volatile storage chip 20 is limited, if the data is directly written to the non-volatile storage chip 20, the service life of the non-volatile storage chip 20 will be shortened, therefore, the data cache array is arranged in the volatile storage chip 10 to cache the data written to the non-volatile storage chip 20.

[0052] Further, the data bit width of the volatile storage chip 10 is greater than that of the non-volatile storage chip 20, therefore, the data cache array is arranged in the volatile storage chip 10 to cache the data written to the non-volatile storage chip 20, which can accelerate the reading or writing speed of the data.

[0053] Further, referring to Figure 5 , the logic chip 30 further comprises a first controller 34, a second controller 35 and a direct access module 36.

[0054] The first controller 34 is connected with the first logical interface and the first transmission interface 311, and is used to control the reading and writing of the volatile storage chip 10; the second controller 35 is connected with the second logical interface and the first lead-out interface 321, and is used to control the reading and writing of the non-volatile storage chip 20; the direct access module 36 is connected with the first controller 34 and the second controller 35, and is used to cooperate with the first controller 34 and the second controller 35 to migrate the data stored in the data cache array of the volatile storage chip 10 to the non-volatile storage chip 20.

[0055] In response to the first logic interface receiving a first data read instruction, the first controller 34 performs a read operation on the data storage array in the volatile storage chip 10 based on the first data read instruction; in response to the second logic interface receiving a second data read instruction, the second controller 35 and the direct access module 36 perform a read operation on the data cache array in the volatile storage chip 10 based on the second data read instruction, and in response to the data cache array in the volatile storage chip 10 not having data matching the second data read instruction, the second controller 35 performs a read operation on the non-volatile storage chip 20 based on the second data read instruction.

[0056] In the embodiments of the present application, because the direct access module 36 is provided, in response to the second controller 35 receiving a data write instruction from the second logic interface, the second controller 35 writes the data corresponding to the data write instruction into the data cache array of the volatile storage chip 10 through the direct access module 36 and the first controller 34.

[0057] In an application scenario, in response to the second controller 35 receiving a data read instruction from the second logic interface, the second controller 35 determines the first storage array or the second storage array corresponding to the target data corresponding to the data read instruction, reads the target data from the second storage array through the second controller 35, or reads the target data from the first storage array through the direct access module 36.

[0058] Optionally, in response to the second controller 35 receiving a data read instruction from the second logic interface, the second controller 35 determines that the target data corresponding to the data read instruction is stored in the second storage array, and reads the target data from the second storage array through the second controller 35.

[0059] Optionally, in response to the second controller 35 receiving a data read instruction from the second logic interface, the second controller 35 determines that the target data corresponding to the data read instruction is stored in the first storage array, and reads the target data from the first storage array through the direct access module 36. Specifically, the second controller 35 sends the data read instruction to the direct access module 36, the direct access module 36 sends the data read instruction to the first controller 34, the first controller 34 reads the target data from the data cache array in the first storage array according to the data read instruction, and sends the target data to the second controller 35 through the direct access module 36, and the second controller 35 feeds back the target data to the external device through the second logic interface.

[0060] In some embodiments, referring to Figure 6 The logic chip 30 further includes a multiplexer 37. One end of the multiplexer 37 is connected to the first controller 34 and the test repair unit 33, and the other end of the multiplexer 37 is connected to the first storage array 12 of the volatile storage chip 10 and the second storage array 22 of the non-volatile storage chip 20.

[0061] The volatile memory chip 10 includes a row decoding circuit 13, a column decoding circuit 14, a first sense amplification circuit 15, and a first memory array 12. The data write instruction or the data read instruction is input to the row decoding circuit 13 and the column decoding circuit 14 through the first logic interface, the first controller 34, and the multiplexer 37, and then the data read or the data write is performed on the first memory array 12 through the first sense amplification circuit 15.

[0062] It can be understood that the memory cells of the volatile memory chip 10 are arranged in an array form, and thus there is physical address information composed of corresponding rows and columns. Therefore, the target row is parsed by the row decoding circuit 13, the target column is parsed by the column decoding circuit 14, and thus the target memory cell is determined, and then the write data is written into the target memory cell or the data is read from the target memory cell. The first sense amplification circuit 15 is used to amplify the electrical signal stored in the memory cell.

[0063] The non-volatile memory chip 20 includes a second sense amplification circuit 23 and a second memory array 22. The data write instruction or the data read instruction is input to the row decoding circuit 13 and the column decoding circuit 14 through the first logic interface, the first controller 34, and the multiplexer 37, and then the data read or the data write is performed on the first memory array 12 through the first sense amplification circuit 15.

[0064] When the available space of the data cache array in the first memory array 12 is less than a threshold value, the first controller 34 reads the data from the data cache array in the first memory array 12 through the multiplexer 37, and then migrates the data stored in the data cache array to the second memory array of the non-volatile memory chip 20 through the multiplexer 37.

[0065] In some embodiments, referring to Figure 7 The logic chip 30 further includes a multiplexer 37. One end of the multiplexer 37 is connected to the first controller 34, the test repair unit 33, and the second controller 35, and the other end of the multiplexer 37 is connected to the first memory array of the volatile memory chip 10 and the second memory array of the non-volatile memory chip 20.

[0066] When the second data write instruction is received by the second logic interface, the second controller 35 and the direct access module 36 select, based on the second data write instruction, to write the data corresponding to the second data write instruction into the data cache array in the volatile memory chip 10 through the multiplexer 37.

[0067] Referring to Figure 8 , Figure 8is a flowchart of an embodiment of a data processing method provided by the present application, which is applied to the integrated chip in any of the above embodiments. The method comprises:

[0068] Step 81: in response to the second logic interface of the integrated chip receiving a data write instruction and corresponding write data.

[0069] Step 82: write the write data into the data cache array of the volatile storage chip.

[0070] In some embodiments, in response to the available space of the data cache array being less than a threshold value, migrate the data stored in the data cache array to the non-volatile storage chip.

[0071] In some embodiments, in response to the first logic interface of the integrated chip receiving a corresponding data read instruction, read the data from the first storage array of the volatile storage chip. Specifically, read the data from the data storage array in the first storage array.

[0072] In some embodiments, in response to the first logic interface of the integrated chip receiving a corresponding data write instruction, write the data to the first storage array of the volatile storage chip. Specifically, write the data to the data storage array in the first storage array.

[0073] In some embodiments, in response to the second logic interface of the integrated chip receiving a corresponding data read instruction, read the data from the data cache array in the first storage array, or read the data from the second storage array. Specifically, it can be determined whether there is corresponding read data in the data cache array in the first storage array, if yes, read the data from the data cache array in the first storage array. If not, read the data from the second storage array.

[0074] In some embodiments, in response to the second logic interface of the integrated chip receiving a corresponding data write instruction and write data, write the write data into the data cache array in the first storage array.

[0075] In some embodiments, the integrated chip can also respond to a corresponding data write instruction of the first logic interface when responding to a corresponding data write instruction of the second logic interface. At this time, in response to the corresponding data write instruction of the second logic interface, write the data to the second storage array.

[0076] In some embodiments, the integrated chip can also respond to a corresponding data read instruction of the first logic interface when responding to a corresponding data write instruction of the second logic interface. At this time, in response to the corresponding data write instruction of the second logic interface, write the data to the second storage array.

[0077] In some embodiments, the integrated chip can also respond to a data read instruction corresponding to the first logical interface when responding to the data read instruction corresponding to the second logical interface.

[0078] In some embodiments, the integrated chip can also respond to a data write instruction corresponding to the first logical interface when responding to the data read instruction corresponding to the second logical interface.

[0079] Referring to Figure 9 , Figure 9 is a flowchart of another embodiment of a data processing method provided by the present application, which is applied to the integrated chip of any of the above embodiments. The method comprises:

[0080] Step 91: In response to the second logical interface receiving a second data read instruction, the second controller and the direct access module of the integrated chip perform a read operation on the data cache array of the volatile storage chip based on the second data read instruction.

[0081] Step 92: In response to there being no data in the data cache array matching the second data read instruction, the second controller performs a read operation on the non-volatile storage chip based on the second data read instruction.

[0082] In some embodiments, in response to the first logical interface of the integrated chip receiving a first data read instruction, the first controller of the integrated chip performs a read operation on the data storage array based on the first data read instruction.

[0083] In an application scenario, the volatile storage chip 10 can be a DRAM (dynamic random access memory), and the non-volatile storage chip 20 can be a 3D NVM (non-volatile memory). The volatile storage chip 10, the non-volatile storage chip 20, and the logic chip 30 are integrated in the manner of the application, to realize a heterogeneous memory with large bandwidth and high capacity. Taking a common NAND grain as the non-volatile storage chip 20, the integrated chip 100 has external access interfaces of DRAM and NAND, and when accessing the internal volatile storage chip 10, the test repair unit 33 is used for wafer-level test repair on the data path of the internal volatile storage chip 10. In normal operation, the read-write command enters the first controller 34 (i.e., a memory controller) after passing through the first logic interface, the memory controller analyzes the read-write command, and then sends the read-write command to the row decoding circuit 13 and the column decoding circuit 14 of the first storage array of the volatile storage chip 10, and then reads and writes the first storage array 12 through the first sense amplifier circuit 15. Compared with the DRAM in the related art, the application reduces the data path circuit and the control path circuit by embedding the DRAM, which greatly reduces the memory access power consumption. Since the memory controller accesses the DRAM storage array with a wider data bit width (for example, the data bit width of a 1 Gb DRAM array can be 1024b or even wider), the embedded DRAM access bandwidth is greatly improved, such as an access bandwidth > 50 Gbps / Gb. For the external access interface of the integrated chip 100, the interface rate can be effectively improved, or it can be operated in a super frequency mode. For data transfer between the DRAM and the NVM, the bandwidths of accessing the two storage media are consistent. If the internal IO bit width is consistent, the serial / parallel and parallel / serial conversion between the wide array data bit width and the narrow IO data bit width in the traditional DDR is not needed, thereby reducing the data link delay and reducing the power consumption.

[0084] For the non-volatile storage chip 20, the external read-write command is buffered, analyzed, and then directly operated on the wide IO array.

[0085] Further, the application divides the capacity of the embedded DRAM into a data storage area and a data cache area according to functions. The data storage area is used to store data access of the external device to the volatile storage chip 10, and the data cache area is used to store buffered data of the external storage interface written to the non-volatile storage chip 20. When the buffered data of the data cache area occupies a certain water level of the reserved storage space (for example, the buffer space is 16 MB, and the buffered data is 8 MB), the buffered data is transferred from the volatile storage chip 10 to the non-volatile storage chip 20, to maintain a certain buffer space.

[0086] Further, when writing data to the non-volatile storage chip 20, the data is first written to the volatile storage chip 10 via the direct access module 36, and when the volatile storage chip 10 runs out of buffer space, the data is moved from the volatile storage chip 10 to the non-volatile storage chip 20.

[0087] Further, the present application also supports moving data of the non-volatile storage chip 20 to the volatile storage chip 10. When receiving an instruction to move data of an address segment of the non-volatile storage chip 20 to the volatile storage chip 10, the second controller 35 reads out the data and moves it to the first controller 34 via the direct access module 36, and then the first controller 34 writes the data to the corresponding target address of the volatile storage chip 10.

[0088] Referring to Figure 10 , Figure 10 is a structural schematic diagram of an embodiment of an electronic device provided by the present application. The electronic device 200 includes the integrated chip 100 provided by any of the above embodiments.

[0089] In the present embodiment, the integrated chip 100 is integrated in any of the above manners, so that no related circuit for data bit width conversion needs to be added between the logic chip 30 and the non-volatile storage chip 20, and between the logic chip 30 and the volatile storage chip 10, and data can be directly exchanged between the logic chip 30 and the non-volatile storage chip 20, and directly exchanged between the logic chip 30 and the volatile storage chip 10, which can reduce data delay and power consumption, and the integrated chip 100 integrated in the above manner has a smaller planar area and thickness.

[0090] In several embodiments provided by the present application, it should be understood that the disclosed methods and devices can be implemented in other manners. For example, the above-described device embodiments are merely schematic, and the division of the modules or units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0091] The integrated units in the above other embodiments, if implemented in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0092] The above is only the embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, which is made by using the content of the specification and drawings of the present application, is also included in the patent protection scope of the present application.

Claims

1. An integrated chip, characterized by The integrated chip comprises: a volatile memory chip; a non-volatile memory chip; a logic chip, which is three-dimensionally bonded to the volatile memory chip; the non-volatile memory chip is arranged on the side of the logic chip and the volatile memory chip in a non-thickness direction, and is connected to the logic chip; wherein the thickness of the non-volatile memory chip is less than or equal to the sum of the thicknesses of the volatile memory chip and the logic chip.

2. The integrated chip according to claim 1, wherein the logic chip comprises a first bonding surface, and the first bonding surface comprises a first transmission interface; the volatile memory chip comprises a second bonding surface, and the second bonding surface comprises a second transmission interface; the first bonding surface is bonded to the second bonding surface to three-dimensionally bond the logic chip to the volatile memory chip, wherein the first transmission interface and the second transmission interface are connected one by one.

3. The integrated chip according to claim 2, wherein the logic chip comprises a first lead-out surface, and the first lead-out surface comprises a first lead-out interface; the non-volatile memory chip comprises a second lead-out surface, and the second lead-out surface comprises a second lead-out interface; the first lead-out interface and the second lead-out interface are connected one by one to connect the non-volatile memory chip to the logic chip.

4. The integrated chip of claim 3, wherein, The integrated chip further comprises: a rewiring layer arranged on one side of the first lead-out surface of the logic chip; the first lead-out interface and the second lead-out interface are connected through the rewiring layer.

5. The integrated chip of claim 4, wherein, The integrated chip further comprises: a substrate arranged on the side of the rewiring layer away from the logic chip, and the substrate is provided with a third lead-out interface and a fourth lead-out interface on the side close to the rewiring layer; the first lead-out surface further comprises a fifth lead-out interface and a sixth lead-out interface, the fifth lead-out interface is connected to the third lead-out interface, thereby forming a first logic interface on the substrate, and the first logic interface is used for data read-write of the volatile memory chip; the fourth lead-out interface is connected to the sixth lead-out interface, thereby forming a second logic interface on the substrate, and the second logic interface is used for data read-write of the non-volatile memory chip.

6. The integrated chip according to any one of claims 1-5, wherein the volatile memory chip comprises a first storage array; the non-volatile memory chip comprises a second storage array; the logic chip comprises a test repair unit (DFT) connected to the first storage array and the second storage array, and used for test repair of the first storage array and / or the second storage array.

7. The integrated chip of claim 6, wherein, the first storage array comprises a data cache array and a data storage array; the data cache array is used for storing write data received by the second logic interface; and the data storage array is used for storing write data received by the first logic interface; when the available space of the data cache array is less than a threshold value, the data stored in the data cache array is migrated to the non-volatile memory chip.

8. The integrated chip of claim 7, wherein, the logic chip further comprises: a first controller connected to the first logic interface and the first transmission interface, configured to control reading and writing of the volatile storage chip; a second controller connected to the second logic interface and the first lead-out interface, configured to control reading and writing of the non-volatile storage chip; a direct access module connected to the first controller and the second controller, configured to cooperate with the first controller and the second controller to migrate data stored in the data cache array to the non-volatile storage chip.

9. The integrated chip of claim 8, wherein, in response to the first logic interface receiving a first data read instruction, the first controller performs a read operation on the data storage array based on the first data read instruction; in response to the second logic interface receiving a second data read instruction, the second controller and the direct access module perform a read operation on the data cache array based on the second data read instruction, and in response to the data cache array not having data matching the second data read instruction, the second controller performs a read operation on the non-volatile storage chip based on the second data read instruction.

10. The integrated chip of claim 8, wherein, The logic chip further comprises: a multiplexer having one end connected to the first controller, the test repair unit, and the other end connected to the first storage array and the second storage array; or a multiplexer having one end connected to the first controller, the test repair unit, and the second controller, and the other end connected to the first storage array and the second storage array.

11. A data processing method, characterized by, The data processing method is applied to the integrated chip of any one of claims 1-10, and the method comprises: in response to the second logic interface of the integrated chip receiving a data write instruction and corresponding write data; writing the write data into the data cache array of the volatile storage chip; in response to available space of the data cache array being less than a threshold value, migrating data stored in the data cache array to the non-volatile storage chip.

12. The method of claim 11, wherein, The method further comprises: in response to the first logic interface of the integrated chip receiving a first data read instruction, the first controller of the integrated chip performing a read operation on the data storage array based on the first data read instruction; or in response to the second logic interface receiving a second data read instruction, the second controller and the direct access module of the integrated chip performing a read operation on the data cache array of the volatile storage chip based on the second data read instruction, and in response to the data cache array not having data matching the second data read instruction, the second controller performing a read operation on the non-volatile storage chip based on the second data read instruction.

13. An electronic device, comprising: The electronic device comprises the integrated chip of any one of claims 1-10.

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