High-speed cache memory and data processing method, medium, chip, and server thereof
By splitting the tag memory into multiple small-capacity single-port random access memories, the read-write conflict problem when single-port random access memory is used as a cache is solved, and the access efficiency of the cache is improved.
Patent Information
- Application Number
- CN202211343320.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-31
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2042-10-31
AI Technical Summary
In the prior art, when using a single-port random access memory as the tag memory of the cache, there is a problem of low cache pipeline access efficiency due to read and write operation conflicts.
The tag memory is divided into multiple small-capacity single-port random access memories. Through precise control, read and write operations can be performed simultaneously. By taking advantage of the tag memory's characteristic that only one WAY's TAG information is updated when writing back, read and write conflicts can be avoided.
It improves the access efficiency of the cache, solves the problem of low access efficiency when a single-port random access memory is used as a cache, and realizes parallel processing of read and write operations.
Smart Images
Figure CN115620766B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of cache memory technology, and more specifically to a data processing method for a cache memory, a computer-readable storage medium, a chip, and a server. Background Technology
[0002] The purpose of a cache is to better utilize the principle of locality and reduce the number of accesses to main memory. Simply put, if a piece of data 'a' is being accessed, it may be accessed multiple times later. Therefore, when this area is accessed for the first time, it is written into the cache. Subsequent accesses to data 'a' do not need to read it from main memory; instead, it is read from the cache, thus reducing waiting time.
[0003] Generally speaking, the cache includes tag memory (TAG_RAM) and data memory (DATA_RAM).
[0004] For a cache access command, the following steps are included:
[0005] Step 1: Read TAG_RAM, compare the read data corresponding to the set_index address in TAG_RAM (i.e., the TAG information of all WAYs) with the TAG information of the Cache access command, and obtain the HIT (hit) or MISS (miss) result after comparison;
[0006] Step 2.1: If HIT is hit and the cache access command is a read command, then read the corresponding read data from DATA_RAM;
[0007] Step 2.2: If HIT occurs and the cache access command is a write command, then the corresponding write data is written to DATA_RAM;
[0008] Step 2.3: If MISS occurs and the cache access command is a read command, the corresponding read data is retrieved from main memory DDR. After the read data is received, the TAG information of the cache access command is written to TAG_RAM. At the same time, the vld flag bit corresponding to the TAG information is written to 1 and the dirty flag bit is written to 0. Then, the corresponding read data is written to DATA_RAM. If the old cache line is replaced, the old data needs to be read out and written back to main memory DDR first, and the corresponding read data is written to DATA_RAM.
[0009] Step 2.3: If MISS occurs and the cache access command is a write command, write the TAG information of the cache access command into TAG_RAM, set the vld flag corresponding to the TAG information to 1 and the dirty flag to 0, and then write the corresponding write data into DATA_RAM. If the old cache line is replaced, the old data needs to be read out and written back to the main memory DDR before writing the corresponding write data into DATA_RAM.
[0010] In the process of realizing this invention, the inventors discovered that the prior art has at least the following technical problems:
[0011] The advantage of single-port RAM (SPRAM) over two-port RAM (TPRAM) is that its area is almost half that of TPRAM. The disadvantage is that it cannot perform read and write operations simultaneously. That is, only read or write operations can be performed at the same time. Therefore, when SPRAM is used as the TAG_RAM of the cache for the sake of area cost, if commands access the TAG_RAM consecutively, there will be a conflict between read and write operations. Executing one operation will make the other command wait, resulting in low access efficiency of the cache pipeline. Summary of the Invention
[0012] The purpose of this invention is to propose a high-speed cache memory and its data processing method, a computer-readable storage medium, a chip, and a server, in order to solve the technical problem of low access efficiency of the cache pipeline when using a single-port random access memory as a tag memory for cache due to area cost considerations.
[0013] Embodiments of the present invention provide a high-speed cache memory, comprising:
[0014] The data caching module includes a tag memory and a data memory. The tag memory includes multiple single-port random access memories, which are divided into multiple WAYs. Each WAY is used to store the TAG information corresponding to the data of one or more cache lines. The data memory is used to store the data of one or more cache lines written to the cache memory.
[0015] The control module is used to receive the current access command sent by the processor, read the target read data corresponding to the current access command from the data cache module according to the current access command, or write the target write data corresponding to the current access command into the data cache module.
[0016] Preferably, the current access command includes TAG information;
[0017] The control module is specifically used for:
[0018] When a current access command is received, it is determined whether any single-port random access memory of the tag memory is being operated by other access commands.
[0019] If any of the single-port random access memories of the tag memory is being operated by other access commands, then all TAG information stored in the single-port random access memories that are not being operated by the other access commands shall be read according to the current access command.
[0020] If one of the TAG information stored in the single-port random access memory of the other access command operation matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written into the data memory.
[0021] Preferably, the control module is further configured to:
[0022] If all the TAG information stored in the single-port random access memory operated by the other access command does not match the TAG information of the current access command, then all the TAG information stored in the single-port random access memory operated by the other access command will be read in the next clock cycle.
[0023] If there is a TAG information in all the TAG information stored in the single-port random access memory operated by other access commands that matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
[0024] Preferably, the current access command includes TAG information;
[0025] The control module is specifically used for:
[0026] When a current access command is received, it is determined whether any single-port random access memory of the tag memory is being operated by other access commands.
[0027] If none of the single-port random access memories of the tag memory are currently being accessed by other access commands, then all TAG information stored in all single-port random access memories is read according to the current access command.
[0028] If any TAG information among all the TAG information stored in all the single-port random access memories matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
[0029] As part of the same inventive concept, embodiments of the present invention also propose a data processing method for the above-mentioned high-speed cache memory, the method comprising the following steps:
[0030] When the control module receives the current access command, it determines whether any single-port random access memory of the tag memory is being operated by other access commands; wherein, the current access command includes TAG information;
[0031] If any of the single-port random access memories of the tag memory is being operated by other access commands, the control module reads all TAG information stored in the single-port random access memories that are not being operated by the other access commands according to the current access command.
[0032] If one of the TAGs stored in the single-port random access memory that has not been operated by the other access commands matches the TAG of the current access command, then the control module reads the target read data corresponding to the current access command from the data memory, or writes the target write data corresponding to the current access command into the data memory.
[0033] Preferably, the method further includes the following steps:
[0034] If all TAG information stored in the single-port random access memory that has not been operated by the other access commands does not match the TAG information of the current access command, then all TAG information stored in the single-port random access memory that has been operated by the other access commands will be read in the next clock cycle.
[0035] If there is a TAG information in all the TAG information stored in the single-port random access memory operated by other access commands that matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
[0036] Preferably, the method further includes the following steps:
[0037] If all the TAG information stored in the single-port random access memory operated by other access commands does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the tag memory.
[0038] If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the target write data corresponding to the current access command into the data memory.
[0039] If there is no free way, the control module reads the TAG information of any way and sends it to the main memory DDR to obtain a free way. Then, the TAG information of the current access command is written into the free way. Furthermore, the target write data corresponding to the current access command is written into the data memory.
[0040] Preferably, the method further includes the following steps:
[0041] If all the TAG information stored in the single-port random access memory operated by other access commands does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory DDR or the next level cache, and determines whether there is at least one free WAY in the tag memory.
[0042] If at least one free way exists, the control module writes the TAG information of the current access instruction into any free way; and writes the acquired target read data into the data memory.
[0043] If there is no free way, the control module reads the TAG information of any way and sends it to the main memory DDR to obtain a free way. Then, the TAG information of the current access instruction is written into the free way; and the acquired target read data is written into the data memory.
[0044] Preferably, the method further includes the following steps:
[0045] If none of the single-port random access memories of the tag memory are currently being accessed by other access commands, the control module reads all TAG information stored in all single-port random access memories according to the current access command;
[0046] If one of the TAGs stored in all the single-port random access memories matches the TAG of the current access command, the control module reads the target read data corresponding to the current access command from the data memory, or writes the target write data corresponding to the current access command into the data memory.
[0047] Preferably, the method further includes the following steps:
[0048] If all the TAG information stored in all the single-port random access memories does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the tag memory.
[0049] If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the target write data corresponding to the current access command into the data memory.
[0050] If there is no free way, the control module reads the TAG information of any way and sends it to the main memory DDR to obtain a free way. Then, the TAG information of the current access command is written into the free way. Furthermore, the target write data corresponding to the current access command is written into the data memory.
[0051] Preferably, the method further includes the following steps:
[0052] If all the TAG information stored in all the single-port random access memories does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory DDR or the next level cache; and determines whether there is at least one free WAY in the tag memory.
[0053] If at least one free way exists, the control module writes the TAG information of the current access instruction into any free way; and writes the acquired target read data into the data memory.
[0054] If there is no free way, the control module reads the TAG information of any way and sends it to the main memory DDR to obtain a free way. Then, the TAG information of the current access instruction is written into the free way; and the acquired target read data is written into the data memory.
[0055] As part of the same inventive concept, embodiments of the present invention also propose a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which, when executed by a processor, implements the data processing method of the cache memory as described above.
[0056] As part of the same inventive concept, embodiments of the present invention also propose a chip including the cache memory described above.
[0057] As part of the same inventive concept, embodiments of the present invention also propose a chip, including a processor and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the data processing method of the cache memory as described above.
[0058] As part of the same inventive concept, embodiments of the present invention also propose a server comprising the chip described above.
[0059] The embodiments of the present invention have the following beneficial effects:
[0060] This invention improves access efficiency for tag memory caches using single-port random access memory (SRAM). It leverages the characteristic that tag memory only updates the tag information of one way during write-back by splitting the single-port SRAM into multiple smaller-capacity SRAMs. This allows for simultaneous read and write operations on the split tag memory; data can be read from one SRAM while data can be written to the others. By providing more precise control over the split tag memory, partial cache access is possible even during read / write conflicts, improving cache command access efficiency and effectively solving the problem of low cache pipeline access efficiency when using single-port SRAM as a cache for area cost considerations.
[0061] Other features and advantages of the present invention will be set forth in the following description. Attached Figure Description
[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0063] Figure 1 This is a schematic diagram of the structure of a high-speed cache memory in an embodiment of the present invention.
[0064] Figure 2 This is a schematic diagram of the write command processing flow of a cache memory according to an embodiment of the present invention.
[0065] Figure 3 This is a schematic diagram of the read command processing flow of a cache memory according to an embodiment of the present invention.
[0066] Figure 4 This is a specific example structure of a high-speed cache memory according to an embodiment of the present invention.
[0067] Figure 5 This is a schematic diagram of the pipelined processing steps of a cache memory.
[0068] Figure 6 This is a schematic diagram illustrating a pipelined command processing example for a traditional cache memory.
[0069] Figure 7 This is a schematic diagram of a pipelined command processing example of a cache memory according to an embodiment of the present invention. Detailed Implementation
[0070] The detailed description of the accompanying drawings is intended to illustrate the presently preferred embodiments of the invention and is not intended to represent only the forms in which the invention can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of the invention.
[0071] Those skilled in the art will understand that the means and functions described herein can be implemented using software functions combining a programmable microprocessor and a general-purpose computer, and / or using application-specific integrated circuits (ASICs). It should also be understood that although the invention is primarily described in the form of apparatuses and methods, it can also be embodied as a computer program product and a system comprising a computer processor and memory coupled to the processor, wherein the memory is encoded with one or more programs capable of performing the functions disclosed herein.
[0072] See Figure 1 One embodiment of the present invention provides a cache memory, comprising:
[0073] The data caching module includes a tag memory (TAG_RAM) and a data memory (DATA_RAM). The TAG_RAM includes multiple single-port random access memories (SPRAMs), which are divided into multiple ways. Each way is used to store the TAG information corresponding to the data of one or more cache lines. The DATA_RAM is used to store the data written to one or more cache lines of the cache memory.
[0074] The control module is used to receive the current access command sent by the processor, read the target read data corresponding to the current access command from the data cache module according to the current access command, or write the target write data corresponding to the current access command into the data cache module.
[0075] Specifically, each SPRAM is the same size. For example, a TAG_RAM of 512M can be split into two 256M SPRAMs and joined together, or into four 128M SPRAMs and joined together. Each SPRAM also contains the same number of WAYs. A Cacheline is a unit of data, and its commonly used size is 64 bytes. Based on the Cacheline size and the SPRAM size, the maximum number of Cacheline data that an SPRAM can store can be determined. Data required for CPU processing is stored in the DATA_RAM in units of Cachelines. The TAG_RAM does not store the actual data content, but rather the TAG information corresponding to the data.
[0076] Taking the example of TAG_RAM being composed of two SPRAMs concatenated together, the two SPRAMs are TAG_RAM0 and TAG_RAM1. Assuming that TAG_RAM0 is being operated on during data reading and writing, TAG_RAM1 can be operated on at this time. If a hit occurs (commonly referred to as a Hit in the art), data reading or writing will proceed normally. If a miss occurs (commonly referred to as a Miss in the art), TAG_RAM0 will be operated on in the next clock cycle.
[0077] It should be noted that the embodiments of the present invention improve the access efficiency of using SPRAM as TAG_RAM cache. This is achieved by leveraging the characteristic that TAG_RAM only updates the TAG information of one WAY during write-back. The SPRAM of the TAG_RAM is split, i.e., improved by combining multiple small-capacity SPRAMs. The split TAG_RAM can then perform simultaneous read and write operations; that is, while reading data from one SPRAM, data can be written to the others. By providing more precise control over the split TAG_RAM, the embodiments of the present invention can also perform partial cache access during read-write conflicts, improving the access efficiency of cache commands and effectively solving the technical problem of low cache pipeline access efficiency when using SPRAM as TAG_RAM for cache due to area cost considerations.
[0078] In some embodiments, the current access command includes TAG information, which is the TAG information corresponding to the target read data or target write data, and is used to determine Hi or Miss. If the TAG_RAM stores TAG information that matches the TAG information, then it is Hi; otherwise, it is Miss.
[0079] In the first scenario, if any SPRAM of the currently defined TAG_RAM is accessed by other commands, then:
[0080] The control module is specifically used for:
[0081] When the current access command is received, it is determined whether any SPRAM of the TAG_RAM is being operated by other access commands;
[0082] If any SPRAM of the current TAG_RAM is being operated by other access commands, then all TAG information stored in the SPRAM that is not being operated by the other access commands is read according to the current access command.
[0083] If one of the TAG information stored in the SPRAM of the other access command operations matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the DATA_RAM, or the target write data corresponding to the current access command is written into the DATA_RAM.
[0084] Furthermore, if all the TAG information stored in the SPRAM operated by the other access commands does not match the TAG information of the current access command, then all the TAG information stored in the SPRAM operated by the other access commands will be read in the next clock cycle.
[0085] If there is a TAG information in the SPRAM that is operated by other access commands that matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the DATA_RAM, or the target write data corresponding to the current access command is written into the DATA_RAM.
[0086] Furthermore, in the second scenario, if any SPRAM of the currently described TAG_RAM is operated on by other access commands, then:
[0087] The control module is specifically used for:
[0088] When the current access command is received, it is determined whether any SPRAM of the TAG_RAM is being operated by other access commands;
[0089] If none of the SPRAMs in the current TAG_RAM have been accessed by other commands, then all TAG information stored in all SPRAMs is read according to the current access command.
[0090] If any of the TAG information stored in all SPRAMs matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the DATA_RAM, or the target write data corresponding to the current access command is written into the DATA_RAM.
[0091] For the two scenarios above, the following examples illustrate the data writing and data reading processes, using the example of TAG_RAM being composed of TAG_RAM0 and TAG_RAM1.
[0092] Figure 2 The diagram shown illustrates the cache write process. Please refer to [link / reference]. Figure 2 When the cache receives a write command (current access command) from the CPU, it performs the following steps:
[0093] Step 1.1: Determine if there are other access commands operating on TAG_RAM0 or TAG_RAM1. If not, the current access command can read the TAG information of both TAG_RAM0 and TAG_RAM1 at the same time. Otherwise, if TAG_RAM0 is being written to, the TAG information of TAG_RAM1 can only be read, and the TAG information of TAG_RAM0 cannot be read.
[0094] Step 1.2: If both TAG_RAM0 and TAG_RAM1 are read simultaneously, compare all the read TAG information with the TAG information of the current access command to determine whether it is a Hit or a Miss.
[0095] If Hit occurs, the target write data corresponding to the current access command will be written to DATA_RAM, and the TAG_RAM0 or TAG_RAM1 containing the Hit's TAG information will be updated, including the update of the vld flag and dirty flag of the TAG information.
[0096] If a miss occurs, and there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command into DATA_RAM.
[0097] If a miss occurs and neither TAG_RAM0 nor TAG_RAM1 has a free way, then a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storage, thus obtaining a free way. The TAG information of the current access command is then written into this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command is written into DATA_RAM.
[0098] Step 1.3: If TAG_RAM0 is being operated on, read the TAG information of TAG_RAM1, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit. If it is a hit, update TAG_RAM1, including updating the vld flag and dirty flag of the TAG information; and write the target write data corresponding to the current access command into DATA_RAM. If it is a miss, read the TAG information of TAG_RAM0 again in the next clock cycle, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit or a miss.
[0099] If Hit occurs, then update TAG_RAM0, including updating the vld flag and dirty flag of the TAG information; and write the target write data corresponding to the current access command into DATA_RAM.
[0100] If a miss occurs, a WAY is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one of the WAYs and sending it to the main memory (DDR) for storage, thus obtaining a free WAY. The TAG information of the current access command is then written into this free WAY, and the TAG_RAM0 or TAG_RAM1 where the free WAY is located is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command is written into DATA_RAM.
[0101] Figure 3 The diagram shown illustrates the cache data reading process. Please refer to [link / reference]. Figure 3 When the cache receives a read command (current access command) from the CPU, it performs the following steps:
[0102] Step 2.1: Determine if there are other access commands operating on TAG_RAM0 or TAG_RAM1. If not, the current access command can read the TAG information of both TAG_RAM0 and TAG_RAM1 at the same time. Otherwise, if TAG_RAM0 is being written to, the TAG information of TAG_RAM1 can only be read, and the TAG information of TAG_RAM0 cannot be read.
[0103] Step 2.2: If both TAG_RAM0 and TAG_RAM1 are read simultaneously, compare all the read TAG information with the TAG information of the current access command to determine whether it is a Hit or Miss.
[0104] If Hit, then read the target read data corresponding to the current access command from DATA_RAM;
[0105] If a miss occurs, the system first reads the main memory DDR or the next level cache. Specifically, some computer devices have multiple levels of cache. If the previous level cache does not have a hit, the system searches for the target data in the next level cache. If there is no next level cache or the last level cache does not have a hit, the system reads the target data from the main memory DDR. After the target data is returned, the system accesses the cache again to find an available way (free).
[0106] If there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command read from main memory DDR or the next level cache into DATA_RAM;
[0107] If neither TAG_RAM0 nor TAG_RAM1 has a free way, a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory DDR for storage, then obtaining a free way. The TAG information of the current access command is written to this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command, which is read from the main memory DDR or the next level cache, is written to DATA_RAM.
[0108] Step 2.3: If TAG_RAM0 is being operated on, read the TAG information of TAG_RAM1, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit. If it is a hit, read the target read data corresponding to the current access command from DATA_RAM; if it is a miss, read the TAG information of TAG_RAM0 again in the next clock cycle, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit or a miss.
[0109] If Hit, then read the target read data corresponding to the current access command from DATA_RAM;
[0110] If a miss occurs, the system first reads the main memory (DDR) or the next level cache. Specifically, some computer devices have multiple levels of cache. If the previous level cache does not have a hit, the system searches for the target data in the next level cache. If there is no next level cache or the last level cache does not have a hit, the system reads the target data from the main memory (DDR). After the target data is returned, the system accesses the cache again to find an available way (free).
[0111] If there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command read from main memory DDR or the next level cache into DATA_RAM;
[0112] If neither TAG_RAM0 nor TAG_RAM1 has a free way, a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory (DDR) for storage, then obtaining a free way. The TAG information of the current access command is written to this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld and dirty flags of the TAG information. At the same time, the target write data corresponding to the current access command, which is read from the main memory (DDR) or the next-level cache, is written to DATA_RAM.
[0113] like Figure 4 The diagram shows a specific example structure of a cache memory according to an embodiment of the present invention. Figure 4 The control module in the embodiments of the present invention is specifically designed as an example. It should be noted that... Figure 4 This is merely an illustrative example to better understand the technical principles of the embodiments of the present invention, but... Figure 4 The framework structure does not constitute a specific limitation on the cache memory of the present invention.
[0114] Among them, pipeline command scheduling is responsible for scheduling commands that access the cache and commands that write back data read from DDR / the next level cache after a MISS to the cache;
[0115] The pipeline processing module performs common pipelined processing on commands that access the cache, including reading TAG_RAM, performing Hit / Miss checks, updating TAG_RAM, reading DATA_RAM, and updating DATA_RAM.
[0116] The data cache module includes TAG_RAM and DATA_RAM, which are mainly responsible for storing command information and data information for accessing the cache, as well as controlling the read and write operations of multiple SPRAMs in TAG_RAM in cooperation with the pipeline processing module.
[0117] Among them, the MISS command / write-back command cache is responsible for caching read command information after MISS, as well as write-back commands and data when the old cacheline is kicked out of the cache, and sending them to the DDR / next-level cache through the command scheduling unit;
[0118] Command scheduling is responsible for scheduling read or write commands in the command cache, as well as rescheduling read commands after read data returns, and sending them to the pipeline processing module.
[0119] Figure 5 This is a diagram illustrating the cache pipeline processing steps; please refer to [link / reference]. Figure 5 P0: Indicates the entry point into the pipeline, requiring a read of TAG_RAM; P1 and P2: Both are waiting for RAM read data to return, assuming a RAM read latency of 3 clock cycles; P3 is the clock cycle when RAM read data is valid, simultaneously performing Hit / Miss checks; P4: If it's a Hit write command, update the dirty flag of TAG_RAM; if it's a Miss write command and a usable way exists, update the TAG information, dirty flag, and vld flag of TAG_RAM; if it's a Hit read command, read DATA_RAM; if it's a Miss read command, read main memory DDR / next-level cache.
[0120] To facilitate understanding of the improved access efficiency of this invention compared to traditional caches, two examples are provided below for comparison:
[0121] Example 1, Figure 6 For a schematic diagram of a traditional pipeline command processing method, please refer to [link / reference]. Figure 6 WCMD stands for Write Command, RCMD stands for Read Command, and WCMD0 to WCMD3 represent four consecutive write commands that access the cache. These write commands may be natural write commands, or they may be due to a read command missing and then reading the target read data from DDR or the next level cache. The obtained target read data needs to access the cache again and be written to the cache as a write command. If all of them miss, then P4 needs to update TAG_RAM. When updating TAG_RAM, since it is SPRAM, TAG_RAM cannot be read at the same time. Therefore, there is a pipeline vacuum period. Four NAs indicate that no new commands enter the pipeline. RCMD4 can only enter the pipeline for execution when there is no operation on TAG_RAM.
[0122] Example 2, Figure 7 This is a schematic diagram of a pipeline command processing example according to an embodiment of the present invention. Please refer to [link / reference]. Figure 7WCMD stands for Write Command, RCMD stands for Read Command. WCMD0 enters the pipeline first. Since TAG_RAM0 and TAG_RAM1 are both idle, they can be read simultaneously. P3 determines that it is a Miss and there is a usable WAY. P4 selects to update TAG_RAM0 and writes the corresponding target write data to DATA_RAM.
[0123] WCMD1, WCMD2, and RCMD3 enter the cache pipeline in sequence. Each of them can simultaneously read TAG_RAM0 and TAG_RAM1 to perform Hit / Miss judgment and update TAG_RAM0 and TAG_RAM1.
[0124] When RCMD4 enters the cache pipeline, since WCMD0 generated a write request to update TAG_RAM0 at P4, RCMD4 can first read TAG_RAM1 and determine it as a Miss. Then, at P4, it needs to read TAG_RAM0 again. At this time, external commands cannot enter and it is determined as a Hit. Then, it reads the target data from DATA_RAM.
[0125] When WCMD5 enters the cache pipeline, since WCMD1 is updating TAG_RAM1, WCMD5 can first read TAG_RAM0. If it is determined to be a Hit, it updates TAG_RAM0 and writes the target write data to DATA_RAM.
[0126] When RCMD6 enters the cache pipeline, since WCMD2 is updating TAG_RAM1, RCMD6 can first read TAG_RAM0. If it is determined to be a Hit, it can then read the target data from DATA_RAM.
[0127] As mentioned above, WCMD5 and RCMD6 fully utilize the characteristic of the cache updating only one WAY at a time. For example, when TAG_RAM is split into two SPRAMs according to WAY, updating one WAY only requires updating one SPRAM, while the other SPRAM can be read and written normally. At the same time, it makes full use of the waiting time required when operating TAG_RAM together in the traditional method. If it hits, it reduces one access to the cache. If it misses, it only requires reading the other SPRAM for judgment. It can be seen that for scenarios with write command hits or read command hits, this method can improve the access efficiency of using SPRAM as the cache of TAG_RAM.
[0128] Another embodiment of the present invention provides a data processing method for the above-mentioned cache memory, the method comprising the following steps:
[0129] Step S1: When the control module receives the current access command, it determines whether any SPRAM of the TAG_RAM is being operated by other access commands; wherein, the current access command includes TAG information, which is the TAG information corresponding to the target read data or target write data, and is used to determine Hit or Miss. If the TAG_RAM stores TAG information that matches the TAG information, then Hit; otherwise, Miss.
[0130] Step S2: If any SPRAM of the TAG_RAM is being operated by other access commands, the control module reads all TAG information stored in the SPRAM that is not being operated by the other access commands according to the current access command.
[0131] Step S3: If there is a TAG information in all the TAG information stored in the SPRAM that has not been operated by the other access commands that matches the TAG information of the current access command, then the control module reads the target read data corresponding to the current access command from the DATA_RAM, or writes the target write data corresponding to the current access command into the DATA_RAM.
[0132] In some embodiments, the method further includes the following steps:
[0133] Step S4: If all TAG information stored in the SPRAM that has not been operated by the other access commands does not match the TAG information of the current access command, then in the next clock cycle, read all TAG information stored in the SPRAM that has been operated by the other access commands.
[0134] Step S5: If there is a TAG information in all the TAG information stored in the SPRAM operated by other access commands that matches the TAG information of the current access command, then read the target read data corresponding to the current access command from the DATA_RAM, or write the target write data corresponding to the current access command into the DATA_RAM.
[0135] Furthermore, the method further includes the following steps:
[0136] Step S6: If all the TAG information stored in the SPRAM operated by other access commands does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the TAG_RAM.
[0137] Step S7: If there is at least one free WAY, the control module writes the TAG information of the current access command into any free WAY; and writes the target write data corresponding to the current access command into the DATA_RAM.
[0138] Step S8: If there is no free WAY, the control module reads the TAG information of any WAY and sends it to the main memory DDR to obtain a free WAY. Then, the TAG information of the current access command is written into the free WAY. Furthermore, the target write data corresponding to the current access command is written into the DATA_RAM.
[0139] Furthermore, the method further includes the following steps:
[0140] Step S9: If all the TAG information stored in the SPRAM operated by other access commands does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory DDR or the next level cache, and determines whether there is at least one free WAY in the TAG_RAM.
[0141] Step S10: If there is at least one free WAY, the control module writes the TAG information of the current access instruction into any free WAY; and writes the acquired target read data into the DATA_RAM.
[0142] Step S11: If there is no free WAY, the control module reads the TAG information of any WAY and sends it to the main memory DDR to obtain a free WAY. Then, the TAG information of the current access instruction is written into the free WAY. Furthermore, the acquired target read data is written into the DATA_RAM.
[0143] Specifically, in the first scenario, any SPRAM of the TAG_RAM is being operated by other access commands. The following examples illustrate the data writing and data reading processes of TAG_RAM, which is formed by concatenating TAG_RAM0 and TAG_RAM1.
[0144] Figure 2 The diagram shown illustrates the cache write process. Please refer to [link / reference]. Figure 2 When the cache receives a write command (current access command) from the CPU, it performs the following steps:
[0145] Step 1.1: Determine if there are other access commands operating on TAG_RAM0 or TAG_RAM1. If not, the current access command can read the TAG information of both TAG_RAM0 and TAG_RAM1 at the same time. Otherwise, if TAG_RAM0 is being written to, the TAG information of TAG_RAM1 can only be read, and the TAG information of TAG_RAM0 cannot be read.
[0146] Step 1.2: If both TAG_RAM0 and TAG_RAM1 are read simultaneously, compare all the read TAG information with the TAG information of the current access command to determine whether it is a Hit or a Miss.
[0147] If Hit occurs, the target write data corresponding to the current access command will be written to DATA_RAM, and the TAG_RAM0 or TAG_RAM1 containing the Hit's TAG information will be updated, including the update of the vld flag and dirty flag of the TAG information.
[0148] If a miss occurs, and there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command into DATA_RAM.
[0149] If a miss occurs and neither TAG_RAM0 nor TAG_RAM1 has a free way, then a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storage, thus obtaining a free way. The TAG information of the current access command is then written into this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command is written into DATA_RAM.
[0150] Step 1.3: If TAG_RAM0 is being operated on, read the TAG information of TAG_RAM1, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit. If it is a hit, update TAG_RAM1, including updating the vld flag and dirty flag of the TAG information; and write the target write data corresponding to the current access command into DATA_RAM. If it is a miss, read the TAG information of TAG_RAM0 again in the next clock cycle, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit or a miss.
[0151] If Hit occurs, then update TAG_RAM0, including updating the vld flag and dirty flag of the TAG information; and write the target write data corresponding to the current access command into DATA_RAM.
[0152] If a miss occurs, a WAY is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one of the WAYs and sending it to the main memory (DDR) for storage, thus obtaining a free WAY. The TAG information of the current access command is then written into this free WAY, and the TAG_RAM0 or TAG_RAM1 where the free WAY is located is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command is written into DATA_RAM.
[0153] In some embodiments, the method further includes the following steps:
[0154] Step S12: If none of the SPRAMs of the current TAG_RAM have been operated by other access commands, the control module reads all TAG information stored in all SPRAMs according to the current access command.
[0155] Step S13: If there is a TAG information in all the TAG information stored in all SPRAM that matches the TAG information of the current access command, then the control module reads the target read data corresponding to the current access command from the DATA_RAM, or writes the target write data corresponding to the current access command into the DATA_RAM.
[0156] In some embodiments, the method further includes the following steps:
[0157] Step S14: If all the TAG information stored in all SPRAMs does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the TAG_RAM.
[0158] Step S15: If there is at least one free WAY, the control module writes the TAG information of the current access command into any free WAY; and writes the target write data corresponding to the current access command into the DATA_RAM.
[0159] Step S16: If there is no free WAY, the control module reads the TAG information of any WAY and sends it to the main memory DDR to obtain a free WAY. Then, the TAG information of the current access instruction is written into the free WAY. Furthermore, the target write data corresponding to the current access command is written into the DATA_RAM.
[0160] In some embodiments, the method further includes the following steps:
[0161] Step S17: If all TAG information stored in all SPRAMs does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory DDR or the next level cache; and determines whether there is at least one free WAY in the TAG_RAM.
[0162] Step S18: If there is at least one free WAY, the control module writes the TAG information of the current access instruction into any free WAY; and writes the acquired target read data into the DATA_RAM.
[0163] Step S19: If there is no free way, the control module reads the TAG information of any way and sends it to the main memory DDR to obtain a free way. Then, the TAG information of the current access instruction is written into the free way. The acquired target read data is written into the DATA_RAM.
[0164] Specifically, in the second scenario, any SPRAM of the TAG_RAM is being operated by other access commands. The following examples illustrate the data writing and data reading processes of TAG_RAM, which is formed by concatenating TAG_RAM0 and TAG_RAM1.
[0165] Figure 3The diagram shown illustrates the cache data reading process. Please refer to [link / reference]. Figure 3 When the cache receives a read command (current access command) from the CPU, it performs the following steps:
[0166] Step 2.1: Determine if there are other access commands operating on TAG_RAM0 or TAG_RAM1. If not, the current access command can read the TAG information of both TAG_RAM0 and TAG_RAM1 at the same time. Otherwise, if TAG_RAM0 is being written to, the TAG information of TAG_RAM1 can only be read, and the TAG information of TAG_RAM0 cannot be read.
[0167] Step 2.2: If both TAG_RAM0 and TAG_RAM1 are read simultaneously, compare all the read TAG information with the TAG information of the current access command to determine whether it is a Hit or Miss.
[0168] If Hit, then read the target read data corresponding to the current access command from DATA_RAM;
[0169] If a miss occurs, the system first reads the main memory DDR or the next level cache. Specifically, some computer devices have multiple levels of cache. If the previous level cache does not have a hit, the system searches for the target data in the next level cache. If there is no next level cache or the last level cache does not have a hit, the system reads the target data from the main memory DDR. After the target data is returned, the system accesses the cache again to find an available way (free).
[0170] If there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command read from main memory DDR or the next level cache into DATA_RAM;
[0171] If neither TAG_RAM0 nor TAG_RAM1 has a free way, a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory DDR for storage, then obtaining a free way. The TAG information of the current access command is written to this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld flag and dirty flag of the TAG information. At the same time, the target write data corresponding to the current access command, which is read from the main memory DDR or the next level cache, is written to DATA_RAM.
[0172] Step 2.3: If TAG_RAM0 is being operated on, read the TAG information of TAG_RAM1, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit. If it is a hit, read the target read data corresponding to the current access command from DATA_RAM; if it is a miss, read the TAG information of TAG_RAM0 again in the next clock cycle, compare all the read TAG information with the TAG information of the current access command, and determine whether it is a hit or a miss.
[0173] If Hit, then read the target read data corresponding to the current access command from DATA_RAM;
[0174] If a miss occurs, the system first reads the main memory (DDR) or the next level cache. Specifically, some computer devices have multiple levels of cache. If the previous level cache does not have a hit, the system searches for the target data in the next level cache. If there is no next level cache or the last level cache does not have a hit, the system reads the target data from the main memory (DDR). After the target data is returned, the system accesses the cache again to find an available way (free).
[0175] If there is a free way in TAG_RAM0 and TAG_RAM1, then select an SPRAM that is not being operated on, write the TAG information of the current access command into its free way, update TAG_RAM0 or TAG_RAM1 where the free way is located, including updating the vld flag and dirty flag of the TAG information; at the same time, write the target write data corresponding to the current access command read from main memory DDR or the next level cache into DATA_RAM;
[0176] If neither TAG_RAM0 nor TAG_RAM1 has a free way, a way is selected for replacement according to the replacement algorithm. This involves reading the TAG information of one way and sending it to the main memory (DDR) for storage, then obtaining a free way. The TAG information of the current access command is written to this free way, and the TAG_RAM0 or TAG_RAM1 containing the free way is updated, including updating the vld and dirty flags of the TAG information. At the same time, the target write data corresponding to the current access command, which is read from the main memory (DDR) or the next-level cache, is written to DATA_RAM.
[0177] It should be noted that the method in this embodiment is a data processing method of the apparatus in the above embodiments. Therefore, the parts of the method not described in detail in this embodiment can be obtained by referring to the specific content of the apparatus in the above embodiments, and will not be described in detail here.
[0178] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the data processing method of the cache memory described in the above embodiments.
[0179] Specifically, the computer-readable storage medium may include any entity or recording medium capable of carrying the computer program instructions, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media.
[0180] An embodiment of the present invention also proposes a chip including the cache memory described in the above embodiments.
[0181] Another embodiment of the present invention provides a chip including a processor and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the data processing method of the cache memory described in the above embodiment.
[0182] Another embodiment of the present invention provides a server comprising a chip including the cache memory described in the above embodiments, or including a processor and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, which are executed by the processor to enable the processor to perform the data processing method of the cache memory described in the above embodiments.
[0183] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A high-speed cache memory, characterized in that, include: The data caching module includes a tag memory and a data memory. The tag memory includes multiple single-port random access memories, which are divided into multiple WAYs. Each WAY is used to store the TAG information corresponding to data in one or more cache lines. The data memory is used to store data written to one or more cache lines of the cache memory. The control module is used to receive the current access command sent by the processor, read the target read data corresponding to the current access command from the data cache module according to the current access command, or write the target write data corresponding to the current access command into the data cache module. The current access command includes TAG information; The control module is specifically used for: When a current access command is received, it is determined whether any single-port random access memory of the tag memory is being operated by other access commands. If any of the single-port random access memories of the tag memory is being operated by other access commands, then all TAG information stored in the single-port random access memories that are not being operated by the other access commands shall be read according to the current access command. If one of the TAG information stored in the single-port random access memory of the other access command operation matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written into the data memory.
2. The cache memory according to claim 1, characterized in that, The control module is further used for: If all the TAG information stored in the single-port random access memory operated by the other access command does not match the TAG information of the current access command, then all the TAG information stored in the single-port random access memory operated by the other access command will be read in the next clock cycle. If there is a TAG information in all the TAG information stored in the single-port random access memory operated by other access commands that matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
3. The cache memory according to claim 1, characterized in that, in, The current access command includes TAG information; The control module is specifically used for: When a current access command is received, it is determined whether any single-port random access memory of the tag memory is being operated by other access commands. If none of the single-port random access memories of the tag memory are currently being accessed by other access commands, then all TAG information stored in all single-port random access memories is read according to the current access command. If any TAG information among all the TAG information stored in all the single-port random access memories matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
4. The data processing method for a high-speed cache memory as described in claim 1, characterized in that, The method includes the following steps: When the control module receives the current access command, it determines whether any single-port random access memory of the tag memory is being operated by other access commands; wherein, the current access command includes TAG information; If any of the single-port random access memories of the tag memory is being operated by other access commands, the control module reads all TAG information stored in the single-port random access memories that are not being operated by the other access commands according to the current access command. If one of the TAGs stored in the single-port random access memory that has not been operated by the other access commands matches the TAG of the current access command, then the control module reads the target read data corresponding to the current access command from the data memory, or writes the target write data corresponding to the current access command into the data memory.
5. The data processing method as described in claim 4, characterized in that, The method further includes the following steps: If all TAG information stored in the single-port random access memory that has not been operated by the other access commands does not match the TAG information of the current access command, then all TAG information stored in the single-port random access memory that has been operated by the other access commands will be read in the next clock cycle. If there is a TAG information in all the TAG information stored in the single-port random access memory operated by other access commands that matches the TAG information of the current access command, then the target read data corresponding to the current access command is read from the data memory, or the target write data corresponding to the current access command is written to the data memory.
6. The data processing method as described in claim 5, characterized in that, The method further includes the following steps: If all the TAG information stored in the single-port random access memory operated by other access commands does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the tag memory. If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the target write data corresponding to the current access command into the data memory. If there is no free way, the control module reads the TAG information of any way and sends it to the main memory to obtain a free way. Then, it writes the TAG information of the current access command into the free way and writes the target write data corresponding to the current access command into the data memory.
7. The data processing method as described in claim 5, characterized in that, The method further includes the following steps: If all the TAG information stored in the single-port random access memory operated by other access commands does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory or the next level cache, and determines whether there is at least one free WAY in the tag memory. If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the acquired target read data into the data memory. If there is no free way, the control module reads the TAG information of any way and sends it to the main memory to obtain a free way. Then, it writes the TAG information of the current access command into the free way and writes the acquired target read data into the data memory.
8. The data processing method as described in claim 4, characterized in that, The method further includes the following steps: If none of the single-port random access memories of the tag memory are currently being accessed by other access commands, the control module reads all TAG information stored in all single-port random access memories according to the current access command; If one of the TAGs stored in all the single-port random access memories matches the TAG of the current access command, the control module reads the target read data corresponding to the current access command from the data memory, or writes the target write data corresponding to the current access command into the data memory.
9. The data processing method as described in claim 8, characterized in that, The method further includes the following steps: If all the TAG information stored in all the single-port random access memories does not match the TAG information of the current access command, and the current access command is to write data, then the control module determines whether there is at least one free WAY in the tag memory. If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the target write data corresponding to the current access command into the data memory. If there is no free way, the control module reads the TAG information of any way and sends it to the main memory to obtain a free way. Then, it writes the TAG information of the current access command into the free way and writes the target write data corresponding to the current access command into the data memory.
10. The data processing method as described in claim 8, characterized in that, The method further includes the following steps: If all the TAG information stored in all the single-port random access memories does not match the TAG information of the current access command, and the current access command is to read data, then the control module obtains the target read data corresponding to the current access command from the main memory or the next level cache; and determines whether there is at least one free WAY in the tag memory. If at least one free way exists, the control module writes the TAG information of the current access command into any free way; and writes the acquired target read data into the data memory. If there is no free way, the control module reads the TAG information of any way and sends it to the main memory to obtain a free way. Then, it writes the TAG information of the current access command into the free way and writes the acquired target read data into the data memory.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the data processing method of the cache memory as described in any one of claims 4 to 10.
12. A chip, characterized in that, Includes the cache memory as described in any one of claims 1 to 3.
13. A chip, characterized in that, The system includes a processor and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, which are executed by the processor to enable the processor to perform a data processing method for a cache memory as described in any one of claims 4 to 10.
14. A server, characterized in that, Includes the chip as described in claim 12 or 13.
Citation Information
Patent Citations
Cache tag memory having first and second single-port arrays and a dual-port array
US5513335A