Data control channel reconstruction method, data decoupling transmission method, equipment and medium

Abstract

The invention provides a data control channel reconstruction method, a data decoupling transmission method, equipment and a medium, and relates to the technical field of data processing and communication.The method comprises the steps that an AXI-DMA controller is constructed between a processing system end and a programmable logic end of a processing system-programmable logic architecture, and a target data channel is obtained; an AXI-Lite bus is constructed between the processing system end and the programmable logic end, and a target control channel is obtained; and respectively carrying out driving initialization processing and parameter configuration on the target data channel and the target control channel, and constructing to obtain a data control channel. According to the invention, mutual interference between data transmission and control operation is effectively avoided, and the response speed and stability of the system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing and communication, and in particular to a data control channel reconstruction method, a data decoupling transmission method, equipment and a medium. BACKGROUND

[0002] In the current complex data processing and communication system, efficient transmission and accurate control of data are key elements to ensure system performance. With the continuous growth of data volume and the continuous expansion of system functions, the traditional design of data control channel is facing a series of severe challenges.

[0003] The data channel and control channel in the existing system are often tightly coupled, which makes it easy for mutual interference between data transmission and control operation. In the scenario of a large amount of data transmission, the control channel resources may be occupied by data traffic, causing the control instructions to be unable to be conveyed to the target module in time. This situation not only affects the response speed of the system, but also may adversely affect the overall stability of the system, making it difficult for the system to maintain reliable operation when facing sudden situations or high-load tasks.

[0004] Therefore, there is an urgent need for a data control channel reconstruction method, a data decoupling transmission method, equipment and a medium to solve the above problems. SUMMARY

[0005] In view of the problems existing in the prior art, the present application provides a data control channel reconstruction method, a data decoupling transmission method, equipment and a medium.

[0006] The present application provides a data control channel reconstruction method, comprising: building an AXI-DMA controller between the processing system end and the programmable logic end of the processing system-programmable logic architecture to obtain a target data channel; building an AXI-Lite bus between the processing system end and the programmable logic end to obtain a target control channel; respectively driving and initializing processing and parameter configuration of the target data channel and the target control channel to obtain a data control channel; The method further comprises: setting a data channel first-in-first-out buffer on a data transmission path between the processing system end and the programmable logic end, wherein the data channel first-in-first-out buffer is used to buffer the data received by the processing system end; the write clock of the data channel first-in-first-out buffer is synchronized with the system clock of the processing system end; and the read clock of the data channel first-in-first-out buffer is synchronized with the system clock of the programmable logic end.

[0007] According to a data control channel reconstruction method provided by the present invention, the processing system terminal is provided with a receiving channel and a transmitting channel, and the data channel first-in-first-out (FIFO) buffer includes a first FIFO buffer and a second FIFO buffer, wherein the first FIFO buffer is used to buffer data sent from the processing system terminal to the programmable logic terminal; and the second FIFO buffer is used to buffer data sent from the programmable logic terminal to the processing system terminal.

[0008] According to a data control channel reconstruction method provided by the present invention, the method further includes: A control channel first-in-first-out (FIFO) buffer is set on the control instruction transmission path between the programmable logic terminal and the processing system terminal. The control channel FIFO buffer is used to buffer the control instructions sent from the processing system terminal to the programmable logic terminal, and send the control instructions to the corresponding register in the programmable logic terminal based on a preset clock domain.

[0009] According to a data control channel reconstruction method provided by the present invention, the step of performing drive initialization processing and parameter configuration on the target data channel and the target control channel respectively to construct a data control channel includes: The driver initialization process is performed on the AXI-DMA controller in the target data channel, and the transmission mode, data width, and buffer address are configured; the driver initialization process is performed on the AXI-Lite bus in the target control channel, and the clock frequency and address mapping relationship are configured. After the driver initialization process and parameter configuration of the target data channel and the target control channel are determined, the data control channel is constructed.

[0010] The present invention also provides a data decoupling transmission method, comprising: Based on the target data channel, data from the processing system end of the processing system-programmable logic architecture is sent to the programmable logic end of the processing system-programmable logic architecture; or, data obtained by the programmable logic end is sent to the processing system end; wherein, the target data channel is constructed based on the above-mentioned data control channel reconstruction method.

[0011] According to a data decoupling transmission method provided by the present invention, the method further includes: The data received by the processing system is buffered by a first-in-first-out (FIFO) buffer set on the data transmission path between the processing system and the programmable logic.

[0012] The present invention also provides a data decoupling transmission method, comprising: Based on the target control channel, control commands generated by the processing system end of the processing system-programmable logic architecture are sent to the programmable logic end of the processing system-programmable logic architecture; wherein, the target control channel is constructed based on the above-mentioned data control channel reconstruction method.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the data decoupling transmission method as described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data decoupling transmission method as described above.

[0015] The data control channel reconstruction method, data decoupling transmission method, device, and medium provided by this invention achieve efficient data transmission by constructing an AXI-DMA controller between the processing system and the programmable logic end to form a target data channel; at the same time, an AXI-Lite bus is constructed as a target control channel to ensure accurate transmission of control commands, effectively avoiding mutual interference between data transmission and control operations, and improving system response speed and stability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating the data control channel reconstruction method provided by the present invention; Figure 2 A schematic diagram of the overall architecture of the data control channel decoupling and reconfiguration design provided by this invention; Figure 3 This is one of the flowcharts illustrating the data decoupling and transmission method provided by the present invention; Figure 4 A schematic diagram illustrating the workflow of data transmission via the data channel provided by this invention; Figure 5 A schematic diagram illustrating the workflow of the data channel receiving data provided by this invention; Figure 6 The second schematic diagram of the data decoupling transmission method provided by the present invention; Figure 7 A schematic diagram of the workflow of the control channel provided by the present invention; Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0019] In current data processing and communication systems, achieving efficient data transmission and precise control is crucial. However, with the rapid growth of data volume and the increasing complexity of system functions, traditional data control channel design is facing numerous challenges.

[0020] On the one hand, in existing systems requiring efficient data transmission and precise control, such as satellite communication and high-speed data acquisition and processing systems, the data channel and control channel are tightly coupled, leading to mutual interference between data transmission and control operations. During large-scale data transmission, control channel resources are easily occupied, causing control commands to fail to be transmitted in a timely manner, thus affecting the system's response speed and stability. Simultaneously, traditional designs struggle to handle multi-clock domain and multi-register operations, failing to meet the diverse clock frequency and register access requirements of various functional modules.

[0021] On the other hand, the development of big data applications has placed higher demands on data transmission rates and throughput. However, existing data transmission methods fail to fully utilize hardware resources, making it difficult to achieve high-speed and stable data transmission, resulting in low data processing efficiency and making it difficult to meet the stringent real-time requirements of application scenarios such as real-time video streaming and high-speed network data transmission.

[0022] Figure 1 This is a flowchart illustrating the data control channel reconstruction method provided by the present invention, as shown below. Figure 1 As shown, the present invention provides a data control channel reconstruction method, comprising: Step 101: Construct an AXI-DMA controller between the processing system end and the programmable logic end of the processing system-programmable logic architecture to obtain the target data channel.

[0023] In this invention, to achieve efficient data transmission within the Processing System (PS) and Programmable Logic (PL) architecture of the ZYNQ platform, an AXI-DMA (Direct Memory Access) controller is constructed between the PS and PL ends. The AXI-DMA controller allows direct memory access to data, thereby significantly improving data transmission efficiency.

[0024] In this invention, a target data channel is constructed using an AXI-DMA controller. This channel supports high-speed, stable data transmission, meeting the demands of large data throughput. Preferably, a First-In-First-Out (FIFO) queue is also configured along the data transmission path for cross-clock domain processing, ensuring smooth data transmission between different clock domains.

[0025] Step 102: Construct an AXI-Lite bus between the processing system and the programmable logic to obtain the target control channel.

[0026] In addition to the data channel, a control channel is also needed to transmit control commands and status information. Therefore, this invention constructs an AXI-Lite bus between the PS and PL ends. The AXI-Lite protocol is suitable for low-bandwidth, high-control-precision scenarios and is ideal for transmitting control information. Through the AXI-Lite bus, a target control channel is constructed, allowing the PS end to directly access multiple registers across multiple clock domains on the PL end, enabling effective control of various functional modules within the PL end. Similarly, this invention can also perform cross-clock domain processing via a FIFO queue to ensure accurate transmission of control signals between different clock domains.

[0027] Step 103: Perform drive initialization and parameter configuration on the target data channel and the target control channel respectively to construct the data control channel.

[0028] In this invention, after constructing the target data channel and the target control channel, these two channels need to undergo driver initialization and parameter configuration to ensure they function correctly and meet system requirements. Driver initialization includes setting the initial state of the channel and configuring its operating mode. Parameter configuration includes setting the data transmission rate and the transmission frequency of control commands. Through driver initialization and parameter configuration, the target data channel and the target control channel are integrated to construct a complete data control channel. This data control channel can simultaneously support efficient data transmission and precise control operations, meeting the needs of current complex data processing and communication systems.

[0029] The data control channel reconstruction method provided by this invention achieves efficient data transmission by constructing an AXI-DMA controller between the processing system and the programmable logic end to form a target data channel; at the same time, it constructs an AXI-Lite bus as a target control channel to ensure the accurate transmission of control commands, effectively avoids mutual interference between data transmission and control operations, and improves the system response speed and stability.

[0030] Based on the above embodiments, the method further includes: A data channel FIFO buffer is configured on the data transmission path between the processing system and the programmable logic. The data channel FIFO buffer is used to buffer the data received by the processing system. The write clock of the data channel FIFO buffer is synchronized with the system clock of the processing system. The read clock of the data channel FIFO buffer is synchronized with the system clock of the programmable logic.

[0031] In this invention, a data channel first-in-first-out (FIFO) buffer is set up on the data transmission path between the processing system and the programmable logic as a data buffer area to temporarily store the data received by the processing system.

[0032] When the processing system receives data, this data is first written into the data channel FIFO buffer, rather than being directly transmitted to the programmable logic. In this way, even if the clock frequencies of the processing system and the programmable logic are different, the data can be temporarily stored in the data channel FIFO buffer, waiting for the appropriate time to be transmitted.

[0033] In this invention, the write clock of the data channel FIFO buffer is synchronized with the system clock of the processing system. When the processing system receives data, it writes the data into the data channel FIFO buffer according to its own clock frequency. This synchronization mechanism ensures that data can be written to the data channel FIFO buffer stably and orderly, without data loss or corruption due to clock differences.

[0034] In this invention, the read clock of the data channel FIFO buffer is synchronized with the system clock of the programmable logic device. When the programmable logic device is ready to receive data, it reads the data from the data channel FIFO buffer according to its own clock frequency. This synchronization mechanism ensures that the data can be correctly read according to the clock frequency of the programmable logic device, thereby realizing data transmission across clock domains.

[0035] This invention achieves cross-clock domain data transmission by setting up a first-in-first-out (FIFO) buffer for the data channel and synchronizing its write and read clocks with the system clocks of the processing system and the programmable logic system, respectively. This solves the synchronization problem of data transmission between different clock domains and improves the stability and reliability of data transmission.

[0036] Based on the above embodiments, the processing system terminal is provided with a receiving channel and a sending channel. The data channel first-in-first-out (FIFO) buffer includes a first FIFO buffer and a second FIFO buffer. The first FIFO buffer is used to buffer data sent from the processing system terminal to the programmable logic terminal. The second FIFO buffer is used to buffer data sent from the programmable logic terminal to the processing system terminal.

[0037] Figure 2 A schematic diagram of the overall architecture of the data control channel decoupling and reconfiguration design provided by this invention can be referenced. Figure 2 As shown, in this invention, the processing system is provided with a receiving channel and a sending channel. These two channels are respectively responsible for receiving data from the programmable logic terminal and sending data to the programmable logic terminal.

[0038] The data channel FIFO buffer includes a first FIFO buffer (FIFO1) and a second FIFO buffer (FIFO2), which are used for data buffering in different directions. The first FIFO buffer buffers data sent from the processing system to the programmable logic device (PLD). When the processing system needs to send data to the PLD, this data is first sent to the transmit data queue in the processing system, and then written into the first FIFO buffer based on the transmit data queue through the target data channel (i.e., the AXI-DMA controller). As a data buffer, the first FIFO buffer can temporarily store this data and wait for the appropriate time to transmit it to the PLD. This design helps to smooth the data transmission rate and avoid data loss or corruption.

[0039] The second FIFO buffer is used to buffer data sent from the programmable logic unit (PLU) to the processing system. When the PLU sends data to the processing system, this data is first written into the second FIFO buffer. Similarly, as a data buffer, the second FIFO buffer can temporarily store this data and wait for the processing system to be ready to receive it before transmitting the data sequentially through the target data channel and the receive data queue to the processing system, ensuring the stability and reliability of data transmission.

[0040] In this invention, when the programmable logic device (PLD) completes data processing and is ready to send data to the processing system, it triggers an interrupt signal. Upon receiving this interrupt signal, the interrupt controller on the processing system pauses the currently executing task and jumps to an interrupt service routine or interrupt handler. In the interrupt handler, the processing system recognizes that the interrupt is from the PLD sending data and prepares to receive the data, including setting status flags and allocating a receive buffer. Within the interrupt handler, the processing system places the task of receiving data into a message queue. A message queue is a first-in, first-out (FIFO) data structure used to pass messages or tasks between different tasks or threads. Further, when the task of receiving data is scheduled for execution, the processing system prepares the receive buffer and configures the interface for communication with the PLD (i.e., the AXI-DMA controller). The PLD receives data from the processing system through the configured interface. This process involves DMA (Direct Memory Access), allowing data to be transferred directly between the memory of the processing system and the PLD without CPU intervention. The received data will be stored in a designated buffer on the processing system side, and can be further processed or stored as needed.

[0041] This invention achieves bidirectional data transmission between the processing system and the programmable logic device by setting up a first FIFO (First-In-First-Out) buffer and a second FIFO buffer. The first FIFO buffer is responsible for data transmission from the processing system to the programmable logic device, while the second FIFO buffer is responsible for data transmission from the programmable logic device to the processing system. This bidirectional data transmission mechanism enables the system to handle various data interaction needs more flexibly, improving the efficiency and stability of data transmission.

[0042] Based on the above embodiments, the method further includes: A control channel first-in-first-out (FIFO) buffer is set on the control instruction transmission path between the programmable logic terminal and the processing system terminal. The control channel FIFO buffer is used to buffer the control instructions sent from the processing system terminal to the programmable logic terminal, and send the control instructions to the corresponding register in the programmable logic terminal based on a preset clock domain.

[0043] In this invention, reference may be made to Figure 2 As shown, a control channel first-in-first-out (FIFO) buffer is set up on the control command transmission path. This control channel FIFO buffer serves as a buffer for control commands, used to temporarily store and process control commands sent from the system.

[0044] In this invention, when the processing system sends control instructions to the programmable logic unit, these instructions are first written into the control channel's first-in-first-out (FIFO) buffer, rather than being directly transmitted to the programmable logic unit's registers. This way, even if the clock frequencies or operating rhythms of the processing system and the programmable logic unit differ, the control instructions can be temporarily stored in the FIFO, waiting for the appropriate time to be transmitted.

[0045] Furthermore, the control channel FIFO buffer sends the buffered control instructions to the corresponding registers in the programmable logic terminal based on a preset clock domain. In this invention, the preset clock domain is the clock signal used internally by the programmable logic terminal to process control instructions. The control channel FIFO buffer ensures that control instructions are read out at the correct clock edge and transmitted to the target register, thereby achieving precise control of the internal functional modules of the programmable logic terminal.

[0046] This invention, by setting up a first-in-first-out (FIFO) buffer for the control channel and transmitting data based on a preset clock domain, ensures that control commands are accurately and promptly received and processed at the programmable logic (PLC) level. This solves the synchronization problem of control command transmission between different clock domains, improving the stability and reliability of the system control. Because the FIFO buffer can cache control commands and transmit them based on a preset clock domain, system control becomes more flexible. The processing system can send control commands as needed without worrying about them being lost or corrupted due to clock differences; simultaneously, the PLC can receive and process these commands according to its own operating rhythm.

[0047] Based on the above embodiments, the step of performing drive initialization processing and parameter configuration on the target data channel and the target control channel respectively to construct the data control channel includes: The driver initialization process is performed on the AXI-DMA controller in the target data channel, and the transmission mode, data width, and buffer address are configured; the driver initialization process is performed on the AXI-Lite bus in the target control channel, and the clock frequency and address mapping relationship are configured. After the driver initialization process and parameter configuration of the target data channel and the target control channel are determined, the data control channel is constructed.

[0048] In this invention, driver initialization is a crucial step in ensuring the proper functioning of the AXI-DMA controller. This includes setting the controller's initial state, configuring its operating mode, and interfacing with other hardware components. During initialization, the transfer mode, data width, and buffer address need to be configured. The transfer mode determines how data is transferred between memory and programmable logic (e.g., single transfer or continuous transfer). The data width specifies the amount of data transferred each time (e.g., 32 bits, 64 bits, etc.). The buffer address specifies the address of the memory region used to temporarily store data.

[0049] Similarly, the AXI-Lite bus undergoes driver initialization to ensure its proper functioning. This includes setting the bus's initial state, configuring its clock frequency, and address mapping. The clock frequency configuration ensures that data transmission on the bus occurs at the correct clock rhythm. The address mapping determines how control instructions are mapped to different registers in the programmable logic module, thereby enabling precise control of the internal functional modules within the programmable logic module.

[0050] Once the driver initialization and parameter configuration for both the target data channel and the target control channel are complete, the data control channel can be constructed. This data control channel integrates the functions of both the target data channel and the target control channel, enabling simultaneous support for efficient data transmission and precise control operations, thus meeting the needs of modern, complex data processing and communication systems.

[0051] This invention is based on a ZYNQ platform-based processing system—a programmable logic architecture—that utilizes the AXI bus for data and control information transmission. By separating the data and control channels and employing a first-in, first-out (FIFO) queue to achieve cross-clock domain processing, system performance is effectively improved. Specifically, the control channel uses the AXI-Lite protocol, while the data channel uses the AXI-DMA protocol, fully leveraging the advantages of both protocols to achieve efficient data control and transmission.

[0052] This invention enables direct memory access to data between the processing system and the programmable logic unit (PLU) via an AXI-DMA controller. AXI-DMA offers highly efficient data transfer capabilities, allowing for rapid data movement between the two systems. Furthermore, to address issues arising from different clock domains, a first-in-first-out (FIFO) queue is implemented along the data transfer path for cross-clock domain processing. This FIFO queue acts as a data buffer, enabling data buffering and synchronization across different clock domains. This ensures that data transfer between the processing system and PLU is unaffected by clock differences, thereby improving data transfer stability and speed.

[0053] Specifically, when the processing system needs to transmit data to the programmable logic unit (PLU), the data first enters the AXI-DMA's First-In-First-Out (FIFO) queue. The FIFO queue buffers data according to the FIFO principle. The write clock of the FIFO queue is synchronized with the clock of the processing system, while the read clock is synchronized with the clock of the PLU. This ensures smooth data transmission from the processing system to the PLU across different clock domains. Similarly, when the PLU transmits data to the processing system, the data is transmitted across clock domains via the receiving side's FIFO queue, ensuring efficient and accurate data transmission. In this way, AXI-DMA, combined with FIFO, achieves high-speed, stable data transmission between the processing system and the PLU, supporting large data throughput.

[0054] For the reconfiguration process of the control channel, this invention connects the processing system and the programmable logic unit via an AXI-Lite bus. The AXI-Lite protocol is suitable for low-bandwidth, high-control-precision scenarios and is well-suited for the transmission of control information. In the control channel, the processing system can directly access multiple registers in multiple clock domains of the programmable logic unit via addresses. Similarly, during the transmission of control signals, FIFOs are used for cross-clock domain processing to ensure accurate transmission of control signals between different clock domains.

[0055] In this invention, when the processing system sends control commands to the programmable logic unit via the AXI-Lite bus, the control commands first enter the control channel FIFO buffer. The control channel FIFO buffer then sends the control commands to the target register in the programmable logic unit at the appropriate time, based on different clock domain requirements. Due to the characteristics of the AXI-Lite protocol, the processing system can precisely specify the address of the target register, enabling flexible operation of multiple registers in the programmable logic unit. Simultaneously, the cross-clock domain processing capability of the control channel FIFO buffer ensures stable transmission of control commands at different clock frequencies, supports multi-clock domain control requirements, and enables the control channel to accurately and timely transmit control commands, achieving effective control of various functional modules in the programmable logic unit.

[0056] The data control channel reconstruction method based on the ZYNQ platform of this invention separates the data channel and the control channel, avoiding mutual interference between data transmission and control operations, and improving system stability and response speed. Specifically, the control channel uses the AXI-Lite protocol combined with FIFO cross-clock domain processing, supporting multi-clock domain and multi-register operations, enhancing control flexibility and accuracy, and meeting the diverse control needs of complex systems. The data channel utilizes the AXI-DMA protocol and FIFO cross-clock processing, resulting in faster data transmission rates, supporting large data throughput, effectively improving data processing efficiency, and meeting the needs of applications with high real-time requirements.

[0057] Figure 3 This is one of the flowcharts illustrating the data decoupling and transmission method provided by the present invention, such as... Figure 3 As shown, the present invention provides a data decoupling transmission method, comprising: Step 301: Based on the target data channel, send the data from the processing system end of the processing system-programmable logic architecture to the programmable logic end of the processing system-programmable logic architecture; or, send the data obtained by the programmable logic end to the processing system end; wherein, the target data channel is constructed based on the data control channel reconstruction method described in the above embodiments.

[0058] In this invention, the target data channel is built based on an AXI-DMA controller, utilizing the DMA (Direct Memory Access) function of the AXI bus to achieve high-speed data transmission between the processing system and the programmable logic. Furthermore, the target data channel uses a data channel FIFO buffer (FIFO queue) for cross-clock domain processing, solving the data transmission synchronization problem between different clock domains.

[0059] On the processing system side, the data to be transmitted is first prepared and stored in a designated memory buffer. Next, the AXI-DMA controller is configured, specifying the source address (i.e., the memory buffer address on the processing system side), the destination address (i.e., the receive address on the programmable logic side), and the length of the transmitted data. Based on the configuration information, the AXI-DMA controller writes the data from the processing system's memory buffer into the data channel's FIFO buffer. The data channel FIFO buffer receives data according to the processing system's clock frequency and buffers it.

[0060] In this invention, the data channel FIFO buffer outputs the buffered data to the programmable logic terminal according to the clock frequency of the programmable logic terminal. In this process, the data channel FIFO buffer plays a role in cross-clock domain buffering and synchronization, ensuring stable data transmission between different clock domains.

[0061] After receiving data from the processing system, the programmable logic controller (PLC) initiates the corresponding signal processing procedure to process the data. Once the PLC completes processing, it stores the result data in its designated buffer. Next, the AXI-DMA controller is reconfigured, specifying the source address (the PLC's buffer address), destination address (the processing system's receiving address), and the length of the transmitted data. The AXI-DMA controller writes the processing result data from the PLC's buffer into the data channel FIFO buffer. The data channel FIFO buffer receives and buffers data according to the PLC's clock frequency. Then, based on the processing system's clock frequency, the data channel FIFO buffer outputs the buffered data to the processing system. Upon receiving the processing result data, the bidirectional data transmission process is complete.

[0062] This invention's bidirectional data transmission mechanism enables efficient and stable data exchange between the programmable logic unit and the processing system, meeting the needs of complex data processing and communication systems. Through the target data channel, the system can fully utilize the processing power of the processing system and the hardware acceleration capabilities of the programmable logic unit to achieve high-performance data processing and applications.

[0063] Figure 4 This is a schematic diagram illustrating the workflow of the data channel for sending data provided by the present invention. Figure 5 This is a schematic diagram illustrating the workflow of the data channel receiving data provided by the present invention. Figure 4 and Figure 5 As shown, in this invention, the ZYNQ platform hardware is first initialized. Specifically, the processing system of the ZYNQ platform is initialized, configuring the processor's clock frequency and memory management unit (MMU), setting the interrupt controller, and ensuring stable processor operation. Simultaneously, the hardware logic resources of the programmable logic side are initialized, including the FPGA's logic units, routing resources, etc., and the hardware circuitry of the programmable logic side is configured and loaded according to design requirements.

[0064] Next, software driver initialization is performed. The AXI-DMA controller driver is initialized, setting parameters such as the DMA transfer mode (e.g., burst transfer, single transfer), data width, and buffer address to ensure correct data transfer. Simultaneously, the AXI-Lite bus driver is initialized, configuring the bus clock frequency and address mapping to enable communication between the processing system and the registers in the programmable logic unit via the AXI-Lite bus.

[0065] Further, the data transfer preparation from the processing system to the programmable logic unit is handled. In the application on the processing system side, the large amount of data to be transferred is prepared and stored in a designated memory buffer. The AXI-DMA controller is configured, specifying the source address (the memory buffer address on the processing system side), the destination address (the receiving address on the programmable logic unit), and the length of the data to be transferred.

[0066] Next, the data is written to the data channel FIFO buffer (i.e., the first FIFO buffer). The AXI-DMA controller, based on the configuration information, writes the data from the processing system's memory buffer into the first FIFO buffer. The first FIFO buffer receives and buffers the data according to the processing system's clock frequency.

[0067] Furthermore, the first-in-first-out (FIFO) queue handles cross-clock domain processing and data output. The first FIFO buffer outputs the buffered data to the programmable logic (PLL) terminal based on the PPL's ​​clock frequency. In this process, the first FIFO buffer acts as a cross-clock domain buffer and synchronizer, ensuring stable data transmission between different clock domains. Finally, after receiving data from the processing system, the first FIFO buffer initiates the signal processing flow.

[0068] During data transmission from the programmable logic controller (PLC) to the processing system, after processing the data, the PLC stores the processing result data in a designated buffer. The AXI-DMA controller is configured by specifying the source address (the PLC's buffer address), the destination address (the processing system's receiving address), and the length of the transmitted data. Then, the AXI-DMA controller writes the processing result data from the PLC's buffer into the data channel's FIFO buffer (i.e., the second FIFO buffer). The second FIFO buffer receives and buffers data according to the PLC's clock frequency. Finally, the second FIFO buffer outputs the buffered data to the processing system according to the processing system's clock frequency. Upon receiving the processing result data, the processing system completes the bidirectional data transmission process.

[0069] The data decoupling transmission method provided by this invention achieves efficient data transmission by constructing an AXI-DMA controller between the processing system and the programmable logic end to form a target data channel; at the same time, it constructs an AXI-Lite bus as a target control channel to ensure the accurate transmission of control commands, effectively avoiding mutual interference between data transmission and control operations, and improving system response speed and stability.

[0070] Based on the above embodiments, the method further includes: The data received by the processing system is buffered by a first-in-first-out (FIFO) buffer set on the data transmission path between the processing system and the programmable logic.

[0071] Figure 6 This is a second flowchart illustrating the data decoupling and transmission method provided by the present invention, as shown below. Figure 6 As shown, the present invention also provides a data decoupling transmission method, comprising: Step 601: Based on the target control channel, the control instructions generated by the processing system end of the processing system-programmable logic architecture are sent to the programmable logic end of the processing system-programmable logic architecture; wherein, the target control channel is constructed based on the data control channel reconstruction method described in the above embodiments.

[0072] In this invention, the target control channel is a channel used to transmit control instructions between the processing system and the programmable logic unit. This channel is built based on the AXI-Lite bus. After control instructions are generated at the processing system level, they are sent to the programmable logic unit via the target control channel. The target register in the programmable logic unit receives these control instructions and performs corresponding operations based on the control data in the instructions.

[0073] Figure 7 A schematic diagram of the working process of the control channel provided by the present invention can be referred to. Figure 7 As shown, the ZYNQ platform hardware is first initialized. Specifically, the processing system of the ZYNQ platform is initialized, configuring the processor's clock frequency and memory management unit (MMU), setting the interrupt controller, and ensuring stable processor operation. Simultaneously, the hardware logic resources of the programmable logic side are initialized, including the FPGA's logic units and routing resources, and the hardware circuitry of the programmable logic side is configured and loaded according to design requirements. Then, software driver initialization is performed. The AXI-DMA controller driver is initialized, setting parameters such as the DMA transfer mode (e.g., burst transfer, single transfer), data width, and buffer address to ensure correct data transfer. Simultaneously, the AXI-Lite bus driver is initialized, configuring the bus clock frequency and address mapping, enabling the processing system to communicate with the registers in the programmable logic side via the AXI-Lite bus.

[0074] Furthermore, the processing system generates control instructions. During system operation, when the processing system needs to perform control operations on multiple registers in the programmable logic, the application program on the processing system generates control instructions based on the control requirements. These control instructions contain the address of the target register and control data.

[0075] Furthermore, control instructions are written to the control channel FIFO buffer. The processing system writes the generated control instructions to the control channel FIFO buffer via the AXI-Lite bus. The control channel FIFO buffer receives and buffers the control instructions according to the clock frequency of the processing system.

[0076] Next, the control channel FIFO buffer processes and sends instructions across clock domains. Specifically, the control channel FIFO buffer sends the buffered control instructions to the target register in the programmable logic controller (PLC) based on the PLC's clock frequency. During this process, the control channel FIFO buffer ensures that control instructions can be accurately transmitted between different clock domains.

[0077] Finally, the control channel FIFO buffer register responds. After receiving the control instruction, the target register in the control channel FIFO buffer performs corresponding operations based on the control data in the instruction, such as adjusting the parameters of the processing algorithm, changing the operating mode of the hardware module, or reading certain results from the physical layer.

[0078] The data decoupling transmission method provided by this invention achieves efficient data transmission by constructing an AXI-DMA controller between the processing system and the programmable logic end to form a target data channel; at the same time, it constructs an AXI-Lite bus as a target control channel to ensure the accurate transmission of control commands, effectively avoiding mutual interference between data transmission and control operations, and improving system response speed and stability.

[0079] Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 8 As shown, the electronic device may include: a processor 801, a communications interface 802, a memory 803, and a communication bus 804, wherein the processor 801, the communications interface 802, and the memory 803 communicate with each other through the communication bus 804. The processor 801 can call logic instructions in the memory 803 to execute a data control channel reconfiguration method. This method includes: constructing an AXI-DMA controller between the processing system end and the programmable logic end of the processing system-programmable logic architecture to obtain a target data channel; constructing an AXI-Lite bus between the processing system end and the programmable logic end to obtain a target control channel; and performing driver initialization processing and parameter configuration on the target data channel and the target control channel respectively to construct the data control channel.

[0080] Furthermore, the logical instructions in the aforementioned memory 803 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0081] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute the data control channel reconstruction method provided by the above methods, the method comprising: constructing an AXI-DMA controller between the processing system end and the programmable logic end of a processing system-programmable logic architecture to obtain a target data channel; constructing an AXI-Lite bus between the processing system end and the programmable logic end to obtain a target control channel; and performing driver initialization processing and parameter configuration on the target data channel and the target control channel respectively to construct a data control channel.

[0082] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the data control channel reconstruction method provided in the above embodiments. The method includes: constructing an AXI-DMA controller between the processing system end and the programmable logic end of a processing system-programmable logic architecture to obtain a target data channel; constructing an AXI-Lite bus between the processing system end and the programmable logic end to obtain a target control channel; and performing driver initialization processing and parameter configuration on the target data channel and the target control channel respectively to construct the data control channel.

[0083] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0084] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data control channel reconstruction method, characterized in that, include: An AXI-DMA controller is built between the processing system end and the programmable logic end of the processing system-programmable logic architecture to obtain the target data channel; An AXI-Lite bus is constructed between the processing system and the programmable logic to obtain the target control channel; The target data channel and the target control channel are respectively driven and initialized and their parameters are configured to construct the data control channel. The method further includes: A data channel FIFO buffer is configured on the data transmission path between the processing system and the programmable logic. The data channel FIFO buffer is used to buffer the data received by the processing system. The write clock of the data channel FIFO buffer is synchronized with the system clock of the processing system. The read clock of the data channel FIFO buffer is synchronized with the system clock of the programmable logic.

2. The data control channel reconstruction method according to claim 1, characterized in that, The processing system terminal is provided with a receiving channel and a sending channel. The data channel first-in-first-out (FIFO) buffer includes a first FIFO buffer and a second FIFO buffer. The first FIFO buffer is used to buffer data sent from the processing system terminal to the programmable logic terminal. The second FIFO buffer is used to buffer data sent from the programmable logic terminal to the processing system terminal.

3. The data control channel reconstruction method according to claim 1, characterized in that, The method further includes: A control channel first-in-first-out (FIFO) buffer is set on the control instruction transmission path between the programmable logic terminal and the processing system terminal. The control channel FIFO buffer is used to buffer the control instructions sent from the processing system terminal to the programmable logic terminal, and send the control instructions to the corresponding register in the programmable logic terminal based on a preset clock domain.

4. The data control channel reconstruction method according to claim 1, characterized in that, The process of performing drive initialization and parameter configuration on the target data channel and the target control channel respectively to construct the data control channel includes: The driver initialization process is performed on the AXI-DMA controller in the target data channel, and the transmission mode, data width, and buffer address are configured; the driver initialization process is performed on the AXI-Lite bus in the target control channel, and the clock frequency and address mapping relationship are configured. After the driver initialization process and parameter configuration of the target data channel and the target control channel are determined, the data control channel is constructed.

5. A data decoupling transmission method, characterized in that, include: Based on the target data channel, data in the processing system end of the processing system-programmable logic architecture is sent to the programmable logic end of the processing system-programmable logic architecture; or, data obtained by the programmable logic end is sent to the processing system end; wherein, the target data channel is constructed based on the data control channel reconstruction method according to any one of claims 1 to 4.

6. The data decoupling transmission method according to claim 5, characterized in that, The method further includes: The data received by the processing system is buffered by a first-in-first-out (FIFO) buffer set on the data transmission path between the processing system and the programmable logic.

7. A data decoupling transmission method, characterized in that, include: Based on the target control channel, control instructions generated by the processing system end of the processing system-programmable logic architecture are sent to the programmable logic end of the processing system-programmable logic architecture; wherein, the target control channel is constructed based on the data control channel reconstruction method according to any one of claims 1 to 4.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the data decoupling transmission method as described in any one of claims 5 to 7.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data decoupling transmission method as described in any one of claims 5 to 7.

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