Memory and operating method thereof, memory system

Abstract

The embodiments of the present disclosure provide a memory and an operating method thereof, and a memory system. The memory comprises at least one memory cell array block and control logic. The memory cell array block comprises a plurality of layers of memory cells and word lines corresponding to each layer of memory cells. The memory cell array block is divided into at least two memory cell array sub-blocks. Each memory cell array sub-block comprises a plurality of layers of memory cells and word lines corresponding to each layer of memory cells. The control logic is coupled to the memory cell array block. The control logic is configured to perform erase, read or program operations on the memory cell array block in a block mode or a sub-block mode. When the erase, read or program operations are performed on the memory cell array block in the sub-block mode, the operation strategy of one of the two memory cell array sub-blocks is determined according to the state of the other memory cell array sub-block.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0002] With the continuous development of 3D NAND flash memory technology, the number of stacked layers in 3D NAND flash memory is increasing, from 24 layers to 48, 96, 128, 176, and even higher, resulting in a continuous increase in the capacity of a single memory array block. However, given the current mainstream focus on high-layer counts, there is still a demand for small-capacity memory cell array blocks. Therefore, there is an urgent need to provide a memory and its operating method that can accommodate the needs of small-capacity memory cell array blocks with minimal firmware updates. Summary of the Invention

[0003] To address one or more existing technical problems, this disclosure provides a memory, its operation method, and a memory system.

[0004] This disclosure provides a memory, including:

[0005] At least one memory cell array block and control logic; wherein...

[0006] The storage cell array block includes multiple layers of storage cells and word line layers corresponding to each layer of storage cells; the storage cell array block is divided into at least two storage cell array sub-blocks, and each storage cell array sub-block includes several layers of storage cells and word line layers corresponding to each layer of storage cells.

[0007] The control logic is coupled to the storage cell array block, and the control logic is configured to: perform erase, read, or program operations on the storage cell array block using block mode or sub-block mode; wherein, when performing erase, read, or program operations on the storage cell array block using sub-block mode, the operation strategy of the other storage cell array sub-block is determined based on the state of at least one of the two storage cell array sub-blocks.

[0008] In the above scheme, the memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

[0009] In the above scheme, the first memory cell array sub-block contains a first number of word line layers, and the second memory cell array sub-block contains a second number of word line layers, wherein the first number and the second number are the same or different.

[0010] In the above scheme, the storage cell array block further includes a virtual storage cell layer and a corresponding virtual word line layer disposed between the first storage cell array sub-block and the second storage cell array sub-block.

[0011] In the above scheme, the control logic is configured as follows:

[0012] For both the first and second storage cell array sub-blocks, the same programming order is used as when performing write programming operations on the storage cell array blocks in block mode.

[0013] In the above scheme, the control logic is configured to: program the first storage cell array sub-block and the second storage cell array sub-block in reverse programming order; wherein, the first storage cell array sub-block is programmed sequentially from the storage cell layer closest to the dummy storage cell layer to the storage cell layer closest to the bottom selection gate; the second storage cell array sub-block is programmed sequentially from the storage cell layer closest to the top selection gate to the storage cell layer closest to the dummy storage cell layer.

[0014] In the above scheme, the control logic is configured to: determine the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks.

[0015] In the above scheme, the control logic is configured to: when the first storage cell array sub-block is in the erase state, determine that the second storage cell array sub-block can be used to perform programming and erase operations.

[0016] In the above scheme, the control logic is configured to: when the first memory cell array sub-block is in a programming state, determine that the second memory cell array sub-block can be used to perform an erase operation but cannot be used to perform a programming operation.

[0017] In the above scheme, the control logic is configured to: when the second storage cell array sub-block is in an erase state or a programming state, determine that the first storage cell array sub-block can be used to perform programming and erase operations.

[0018] In the above scheme, the control logic is configured to: when the first storage cell array sub-block is in the programming state and needs to be erased, and the second storage cell array sub-block is in the programming state, the first storage cell array sub-block is erased.

[0019] In the above scheme, the control logic is configured to: when the first storage cell array sub-block is in a programming state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, the first storage cell array sub-block and the second storage cell array sub-block are erased together.

[0020] In the above scheme, the control logic is configured such that when the second memory cell array sub-block is in the programming state, the number of programming / erasing cycles of the first memory cell array sub-block is less than or equal to a first preset value.

[0021] In the above scheme, the control logic is configured to: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, programming / erasing operations on the first storage cell array sub-block are prohibited until the data stored in the second storage cell array sub-block is erased.

[0022] In the above scheme, the control logic is configured such that when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, the data stored in the second storage cell array sub-block is erased and programmed, and then the first storage cell array sub-block can still be used to perform programming and erasing operations.

[0023] In the above scheme, the range of the first preset value is 10-100.

[0024] In the above scheme, the control logic is configured to use a wear leveling algorithm to process the first memory cell array sub-block and the second memory cell array sub-block, so that the difference between the number of programming / erasing cycles of the first memory cell array sub-block and the number of programming / erasing cycles of the second memory cell array sub-block is less than a second preset value.

[0025] In the above scheme, the control logic is configured to: when performing a read operation on the memory cell array block in sub-block mode, determine the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing the read operation based on the state of each memory cell array sub-block in the two memory cell array sub-blocks.

[0026] In the above scheme, the control logic is configured as follows: when performing a read operation on the memory cell array block in sub-block mode, the memory cell array sub-block to be read is in a programming state; when another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read; when another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read, wherein the first read voltage is less than the second read voltage.

[0027] In the above scheme, the first reading voltage and the second reading voltage are obtained by superimposing the reference reading voltage and the compensation voltage.

[0028] In the above scheme, the control logic is configured as follows:

[0029] When another memory cell array sub-block is in an erase state, the read voltage offset flag of the memory cell array block is stored as a first state; the first state indicates that the compensation voltage is less than zero.

[0030] When another memory cell array sub-block is in a programming state, the read voltage offset flag of the memory cell array block is stored as a second state; the second state indicates that the compensation voltage is zero.

[0031] In the above scheme, the memory further includes a register corresponding to the memory cell array block; the register is configured to store the read voltage offset flag corresponding to the memory cell array block;

[0032] The control logic is configured to update the state of the register when the programming state of any sub-block of the memory cell array changes.

[0033] This disclosure also provides a memory system, including:

[0034] One or more memories as described in the foregoing embodiments; and

[0035] A storage controller that is coupled to and controls the memory.

[0036] In the above scheme, for each memory, the corresponding control logic in each memory is configured to: when any storage cell array sub-block in the corresponding memory performs the corresponding operation, send the status of the storage cell array sub-block to the storage controller;

[0037] The storage controller is configured to: store the state of any sub-block of the storage cell array in each memory, and send the state of all sub-blocks contained in the storage cell array block to the corresponding control logic before the corresponding control logic performs a read operation on the storage cell array block of the memory in sub-block mode.

[0038] This disclosure further provides a method for operating a memory, wherein the memory includes at least one memory cell array block and control logic; wherein...

[0039] The storage cell array block includes multiple layers of storage cells and word line layers corresponding to each layer of storage cells; the storage cell array block is divided into at least two storage cell array sub-blocks, and each storage cell array sub-block includes several layers of storage cells and word line layers corresponding to each layer of storage cells.

[0040] The method includes:

[0041] The memory cell array blocks are erased, read, or programmed using either block mode or sub-block mode. When the memory cell array blocks are erased, read, or programmed using sub-block mode, the operation strategy of the other memory cell array sub-block is determined based on the state of at least one of the two memory cell array sub-blocks.

[0042] In the above scheme, the memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

[0043] In the above scheme, the storage cell array block further includes a virtual storage cell layer and a corresponding virtual word line layer disposed between the first storage cell array sub-block and the second storage cell array sub-block.

[0044] In the above scheme, the method further includes: for both the first storage cell array sub-block and the second storage cell array sub-block, the same programming order is used as when performing write programming operations on the storage cell array block in block mode.

[0045] In the above scheme, the programming order for both the first and second memory cell array sub-blocks is the same as the programming order when performing write programming operations on the memory cell array blocks in block mode, including:

[0046] Both the first and second memory cell array sub-blocks are programmed in reverse programming order. Specifically, the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom selection gate. The second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the top selection gate to the memory cell layer closest to the dummy memory cell layer.

[0047] In the above scheme, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks includes:

[0048] Based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks, the operation strategy of the other storage cell array sub-block is determined.

[0049] In the above scheme, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0050] When the first storage cell array sub-block is in the erase state, it is determined that the second storage cell array sub-block can be used to perform programming and erasure operations.

[0051] In the above scheme, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0052] When the first storage cell array sub-block is in the programming state, it is determined that the second storage cell array sub-block can be used to perform an erase operation but cannot be used to perform a programming operation.

[0053] In the above scheme, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0054] When the second storage cell array sub-block is in an erase state or a programming state, it is determined that the first storage cell array sub-block can be used to perform programming and erase operations.

[0055] The method in the above scheme further includes:

[0056] When the first storage cell array sub-block is in the programming state and needs to be erased, and the second storage cell array sub-block is in the programming state, the first storage cell array sub-block will be erased.

[0057] In the above scheme, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0058] When the first storage cell array sub-block is in the programming state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, the first storage cell array sub-block and the second storage cell array sub-block are erased together.

[0059] The method in the above scheme further includes:

[0060] When the second storage cell array sub-block is in the programming state, the number of programming / erasing cycles of the first storage cell array sub-block is less than or equal to a first preset value.

[0061] In the above scheme, the method further includes: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, programming / erasing operations on the first storage cell array sub-block are prohibited until the data stored in the second storage cell array sub-block is erased.

[0062] In the above scheme, the method further includes: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, erasing and programming operations are performed on the data stored in the second storage cell array sub-block, and then the first storage cell array sub-block can still be used to perform programming and erasing operations.

[0063] The method in the above scheme further includes:

[0064] A wear leveling algorithm is used to process the first and second memory cell array sub-blocks so that the difference between the number of programming / erase cycles of the first and second memory cell array sub-blocks is less than a second preset value.

[0065] In the above scheme, when performing erase, read, or program operations on the storage cell array block using the sub-block mode, the operation strategy of the other storage cell array sub-block is determined based on the state of at least one of the two storage cell array sub-blocks, including:

[0066] When performing a read operation on the memory cell array block in sub-block mode, the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing the read operation is determined according to the state of each memory cell array sub-block in the two memory cell array sub-blocks.

[0067] In the above scheme, determining the voltage control strategy used when a memory cell array sub-block in the programming state performs a read operation based on the state of each of the two memory cell array sub-blocks includes:

[0068] When performing a read operation on the memory cell array block using the sub-block mode, the memory cell array sub-block to be read is in a programming state. When another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. When another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. The first read voltage is less than the second read voltage.

[0069] In the above scheme, the first reading voltage and the second reading voltage are obtained by superimposing the reference reading voltage and the compensation voltage.

[0070] In the above scheme, the method further includes: when another memory cell array sub-block is in an erase state, storing the read voltage offset flag of the memory cell array block as a first state; the first state indicates that the compensation voltage is less than zero;

[0071] When another memory cell array sub-block is in a programming state, the read voltage offset flag of the memory cell array block is stored as a second state; the second state indicates that the compensation voltage is zero.

[0072] The method in the above scheme further includes:

[0073] When the programming state of any sub-block of the memory cell array changes, the read voltage offset flag corresponding to the memory cell array block is updated. Attached Figure Description

[0074] Figure 1 A block diagram of an exemplary system with memory according to some aspects of this disclosure is shown.

[0075] Figure 2A An illustration of an exemplary memory card having memory according to some aspects of this disclosure is shown.

[0076] Figure 2BAn illustration of an exemplary solid-state drive (SSD) having memory according to some aspects of this disclosure is shown.

[0077] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry according to some aspects of this disclosure is shown.

[0078] Figure 4 A side view of a cross section of an exemplary memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0079] Figure 5 A block diagram of an exemplary memory including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0080] Figure 6 A schematic diagram of an exemplary memory cell array block provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0081] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0082] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0083] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0085] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0086] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0087] In order to gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0088] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0089] Memory 104 can be any memory disclosed in this disclosure. As disclosed in detail below, memory 104 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0090] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as Solid State Disks (SSDs) or embedded Multi Media Cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correcting codes (ECCs) relating to data read from or programmed into the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0091] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0092] Figure 3A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array device 301 and peripheral circuitry 302 coupled to the memory cell array device 301. The memory cell array device 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a semiconductor layer (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0093] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by programming one of the three possible nominal storage values ​​into the cell. A fourth nominal storage value can be used for the erase state.

[0094] like Figure 3As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 can be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0095] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some implementations, each block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304a, a source line 314 biased to the selected block 304a and an unselected block 304b on the same face as the selected block 304a can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of a memory cell 306, which is a basic unit of data used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0096] Figure 4 A cross-sectional side view of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure is shown. The NAND memory string 308 may include a stack structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stack structure 410 determines the number of memory cells included in the memory array 401.

[0097] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0098] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0099] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0100] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver / column driver 506, a row decoder / word line driver / row driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 5 Additional peripheral circuitry not shown.

[0101] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver / column driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0102] The row decoder / word line driver / row driver 508 can be configured to be controlled by control logic 512 and to select / deselect block 304 of memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / word line driver / row driver 508 can also be configured to drive word line 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver / row driver 508 can also select / deselect and drive SSG line 315 and DSG line 313. As described in detail below, the row decoder / word line driver / row driver 508 is configured to perform an erase operation on memory cell 306 coupled to one or more selected word lines 318. Voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0103] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver / column driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0104] As mentioned earlier, with the continuous development of memory technology, the number of memory cell layers has also been increasing, from 24 layers to 48, 96, 128, 176 and even higher. Due to process limitations, memories containing 48 or more memory cell layers need to be formed using a technique of stacking multiple sub-stack structures (Decks). In the memory cell array block, the channel holes (CHs) corresponding to each sub-stack structure are connected and together form the CH of the memory.

[0105] In some embodiments, erase, program, and read-program operations of the memory can all be based on a single memory cell array block. Considering that for a memory with multiple sub-stack structures, a dummy word line layer can be used as a control switch to divide a single memory cell array block into multiple memory cell array sub-blocks, if each sub-stack structure can be processed independently as a different memory cell array sub-block (or partial block), the memory can simultaneously meet both high-capacity and low-capacity requirements under current hardware conditions. Current memory firmware is generally designed for individual operation of a single memory cell array block; therefore, it is of practical significance to adapt to the individual operation of memory cell array sub-blocks while minimizing firmware updates.

[0106] This disclosure provides an operation method for a memory, the memory including at least one memory cell array block and control logic; wherein, the memory cell array block includes multiple layers of memory cells and word line layers corresponding to each layer of memory cells; the memory cell array block is divided into at least two memory cell array sub-blocks, each memory cell array sub-block including several layers of memory cells and word line layers corresponding to each layer of memory cells; the method includes:

[0107] The memory cell array blocks are erased, read, or programmed using either block mode or sub-block mode. When the memory cell array blocks are erased, read, or programmed using sub-block mode, the operation strategy of the other memory cell array sub-block is determined based on the state of at least one of the two memory cell array sub-blocks.

[0108] Here, the block mode represents selecting a memory cell array block as the target block and performing corresponding operations on the target block; the sub-block mode represents selecting a memory cell array sub-block as the target block and performing corresponding operations on the target block. The operation strategy may include a state or a voltage control strategy adopted when performing the corresponding operation. The state may be an erase state or a programming state.

[0109] Here, a storage cell array block includes at least two storage cell array sub-blocks. In some specific examples, a storage cell array block may include two, three, or four storage cell array sub-blocks, etc.

[0110] For ease of understanding, the following explanation uses an example of a memory cell array block comprising two memory cell array sub-blocks.

[0111] In some embodiments, the memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

[0112] Here, a memory cell array block includes two memory cell array sub-blocks. The memory includes two sub-stacked structures; wherein, the sub-stacked structure located closer to the bottom of the semiconductor layer is the first memory cell array sub-block, and the sub-stacked structure located at a higher position above the bottom sub-stacked structure is the second memory cell array sub-block.

[0113] In some embodiments, the first memory cell array subblock includes a first number of word line layers, and the second memory cell array subblock includes a second number of word line layers, wherein the first number and the second number may be the same or different.

[0114] In some embodiments, considering that the sub-stack structure at the bottom position is more stable than the sub-stack structure at the top position, the sub-stack structure at the bottom position contains more memory cell layers than the sub-stack structure at the top position. That is, there is an asymmetric structure between the sub-stack structures, and the number of word line layers contained in the sub-stack structures is different.

[0115] In some embodiments, the sub-stack structures can also be symmetrical, that is, the number of storage cell layers contained in the bottom sub-stack structure is the same as the number of storage cell layers contained in the higher sub-stack structure.

[0116] To meet manufacturing requirements, in addition to the conventional word line layer, a dummy word line layer also exists in the sub-stack structure. In the embodiments of this application, the dummy word line layer can be used as a switch control for implementing the sub-block partitioning of the memory cell array.

[0117] Based on this, in some embodiments, the storage cell array block further includes a dummy storage cell layer and a corresponding dummy word line layer disposed between the first storage cell array sub-block and the second storage cell array sub-block.

[0118] Here, the storage cell layer coupled to the dummy word line layer is not used to store data.

[0119] For example, with Figure 6 The single memory cell array block shown is illustrated. Figure 6 In this configuration, a single memory cell array block includes: a bottom select transistor layer, for example, four bottom dummy word line layers located on the bottom select transistor, for example, an M-layer word line layer located on the bottom dummy word line layer, for example, four middle dummy word line layers located on the M-layer word line layer, for example, an N-layer word line layer located on the middle dummy word line layer, for example, three top dummy word line layers located on the N-layer word line layer, and a top select transistor located on the top dummy word line layer.

[0120] At this time, when the memory cell array block operates in sub-block mode, the M-layer word line layer located on the bottom dummy word line layer can be understood as the first memory cell array sub-block, and the N-layer word line layer located on the middle dummy word line layer can be understood as the second memory cell array sub-block. For example, M = N = 88. Furthermore, the middle dummy word line layer can be used as a switch control between the first and second memory cell array sub-blocks. For example, the two middle dummy word line layers closest to the M-layer word line layer (first memory cell array sub-block) among the four middle dummy word line layers can serve as the top selection transistor of the first memory cell array sub-block; the two middle dummy word line layers closest to the N-layer word line layer (second memory cell array sub-block) among the four middle dummy word line layers can serve as the bottom selection transistor of the second memory cell array sub-block. At this time, when the memory cell array blocks are operated in block mode, the middle dummy word line layer has the same function as the M-layer word line layer and the N-layer word line layer, but the memory cell layer coupled with the dummy word line layer is not used to store data.

[0121] It should be noted that the examples of the number of layers in each layer of the storage cell array block are for illustrative purposes only and are not intended to limit the number of layers in each layer of the storage cell array block in the embodiments of this application.

[0122] In some embodiments, the method further includes:

[0123] For both the first and second storage cell array sub-blocks, the same programming order is used as when programming the storage cell array blocks in block mode.

[0124] In some specific examples, when the memory performs the corresponding operation using the block mode, it is programmed in reverse programming order, still using... Figure 6 For example, the programming order of a single memory cell array block is from the memory cell layer corresponding to the word line layer 0 downwards, until the memory cell layer corresponding to the word line layer 175.

[0125] In some embodiments, the method further includes:

[0126] Both the first and second memory cell array sub-blocks are programmed in reverse programming order. Specifically, the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom selection gate. The second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the top selection gate to the memory cell layer closest to the dummy memory cell layer.

[0127] For example, still using Figure 6Let's take an example to illustrate. Figure 6 In the configuration, the programming order of the 88th word line layer (first memory cell array sub-block) located on the bottom dummy word line layer is sequentially downwards from the memory cell layer corresponding to the 88th word line layer to the memory cell layer corresponding to the 175th word line layer. The programming order of the 88th word line layer (second memory cell array sub-block) located on the middle dummy word line layer is sequentially downwards from the memory cell layer corresponding to the 0th word line layer to the memory cell layer corresponding to the 87th word line layer. The programming order of the first and second memory cell array sub-blocks can be referenced... Figure 6 The direction indicated by the middle arrow.

[0128] In some embodiments, the method further includes:

[0129] Both the first and second memory cell array sub-blocks are programmed in a forward programming order. Specifically, the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the bottom select gate to the memory cell layer closest to the dummy memory cell layer; the second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the top select gate. It can be understood that when the memory cell array blocks are not programmed in block mode, the programming order is sequentially from the memory cell layer closest to the bottom select gate to the memory cell layer closest to the top select gate.

[0130] In other embodiments, the method further includes:

[0131] The first and second memory cell array sub-blocks are programmed in different programming orders; the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom selection gate; the second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the top selection gate.

[0132] For example, still using Figure 6 The single memory cell array block shown is illustrated. ​ In the above, the programming order of the 88th word line layer (first memory cell array sub-block) located on the bottom dummy word line layer is from the memory cell layer corresponding to the 88th word line layer downwards, up to the memory cell layer corresponding to the 176th word line layer. The programming order of the 88th word line layer (second memory cell array sub-block) located on the middle dummy word line layer is from the memory cell layer corresponding to the 87th word line layer downwards, up to the memory cell layer corresponding to the 0th word line layer.

[0133] It is understandable that when both the first and second sub-blocks of the memory cell array adopt the same programming order as when programming the memory cell array block in block mode, both block mode and sub-block mode can be supported simultaneously. This is because the programming order of the two modes is the same, and the same page maps can also be used, thus saving the design cost caused by their difference.

[0134] In some embodiments, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks includes:

[0135] Based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks, the operation strategy of the other storage cell array sub-block is determined.

[0136] Here, when determining the operation strategy of one of the two memory cell array sub-blocks (the memory cell array sub-block to be determined), it is necessary to consider the state of the other memory cell array sub-block (the memory cell array sub-block not to be determined) and their relative positional relationship.

[0137] Here, the need to consider the relative positional relationship between the two memory cell array sub-blocks can be understood as follows: in this description and the following text, the first memory cell array sub-block is the one located closer to the semiconductor layer, and the second memory cell array sub-block is the one located on top of the first memory cell array sub-block. When referring to the first and second memory cell array sub-blocks, their positional relationship is always that the first memory cell array sub-block is closer to the semiconductor layer, and the second memory cell array sub-block is farther from the semiconductor layer; this positional relationship cannot be interchanged. In some specific examples, the memory can receive the state of the non-determinable memory cell array sub-block and the relative positional relationship between the determinable and non-determinable memory cell array sub-blocks provided by the memory system or host, thereby determining the operations that the determinable memory cell array sub-block can perform. In some embodiments, determining the operation strategy of the other memory cell array sub-block based on the state of one of the two memory cell array sub-blocks, combined with the relative positional relationship between the two memory cell array sub-blocks, includes:

[0138] When the first storage cell array sub-block is in the erase state, it is determined that the second storage cell array sub-block can be used to perform programming and erasure operations.

[0139] Here, if the first memory cell array sub-block is in an erased state, the second memory cell array sub-block can be used freely. In some specific examples, when the memory obtains from the memory system or the memory's registers that the first memory cell array sub-block is in an erased state, if it then receives an instruction to perform a programming or erasing operation on the second memory cell array sub-block, the memory responds to the programming and erasing operation instructions and performs the programming or erasing operation on the second memory cell array sub-block.

[0140] It is understandable that when programming the memory cell array block using block mode or sub-block mode, if each sub-block and the block are programmed in reverse order, and if the first memory cell array sub-block located near the semiconductor layer is in an erase state and programming is performed on the second memory cell array sub-block located on the first memory cell array sub-block, the programming conditions are the same as when programming the memory cell array block using block mode. In this case, block mode and sub-block mode are compatible. If the first memory cell array sub-block is in an erase state and an erase operation is performed on the second memory cell array sub-block, the word line layer in the first memory cell array sub-block needs to be subjected to a higher hold and release voltage to ensure that it is not erased along with the second memory cell array sub-block. However, since the first memory cell array sub-block itself is in an erase state, there is no erase interference problem.

[0141] In some embodiments, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0142] When the first storage cell array sub-block is in the programming state, it is determined that the second storage cell array sub-block can be used to perform an erase operation but cannot be used to perform a programming operation.

[0143] Here, if the first memory cell array sub-block is in a programmed state, the second memory cell array sub-block cannot be programmed. In some specific examples, when the memory obtains from the memory system or the memory's registers that the first memory cell array sub-block is in a programmed state, if it then receives an instruction to perform a programming or erasing operation on the second memory cell array sub-block, the memory responds to the erasing operation instruction but not the programming operation instruction.

[0144] It is understandable that when programming the memory cell array block using block mode or sub-block mode, if each sub-block and the block are programmed in reverse order, and if the first memory cell array sub-block located near the semiconductor layer is in a programming state and a programming operation is performed on the second memory cell array sub-block located on the first memory cell array sub-block, the programming conditions are incompatible with those under block mode programming conditions. However, if the first memory cell array sub-block is in a programming state and an erase operation is performed on the second memory cell array sub-block, there is no incompatibility with partial erase operations under block mode, therefore, erasing the second memory cell array sub-block is permitted in this case.

[0145] In some embodiments, determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes:

[0146] When the second storage cell array sub-block is in an erase state or a programming state, it is determined that the first storage cell array sub-block can be used to perform programming and erase operations.

[0147] Here, if the second memory cell array sub-block is in a programmed state, programming and erasing operations are allowed on the first memory cell array sub-block. In some specific examples, when the memory obtains from the memory system or memory registers that the second memory cell array sub-block is in a programmed state, if it then receives an instruction to perform a programming or erasing operation on the first memory cell array sub-block, the memory responds with the erase instruction and the programming operation instruction.

[0148] It is understandable that when programming the memory cell array block using block mode or sub-block mode, if each sub-block and the block are programmed in reverse order, and if the second memory cell array sub-block is in a programming state and programming the first memory cell array sub-block, the programming conditions are compatible with those of programming the bottom sub-stack structure in the memory cell array block using block mode. Similarly, if the second memory cell array sub-block is in a programming state and erasing the first memory cell array sub-block, there will be no incompatibility with partially erasing the memory cell array block using block mode; therefore, erasing the first memory cell array sub-block is also permitted in this case.

[0149] Here, if the second memory cell array sub-block is in an erase state, programming and erasing operations are allowed on the first memory cell array sub-block. In some specific examples, when the memory obtains from the memory system or memory registers that the second memory cell array sub-block is in a programming state, if it then receives an instruction to perform a programming or erasing operation on the first memory cell array sub-block, the memory responds to the erase instruction and the programming operation instruction.

[0150] It is understandable that when programming the memory cell array block using block mode or sub-block mode, if each sub-block and the block are programmed in reverse order, and if the second memory cell array sub-block is in an erase state while programming the first memory cell array sub-block, the programming conditions are compatible with those of programming the bottom sub-stack structure in the memory cell array block using block mode. Similarly, if the second memory cell array sub-block is in an erase state while erasing the first memory cell array sub-block, this will not cause incompatibility with partially erasing the memory cell array block using block mode; therefore, erasing the first memory cell array sub-block is also permitted in this case.

[0151] In some embodiments, the method further includes:

[0152] When the first storage cell array sub-block is in the programming state and needs to be erased, and the second storage cell array sub-block is in the programming state, the first storage cell array sub-block will be erased.

[0153] Here, if both the first and second sub-blocks of the storage cell array have stored data, then the first sub-block can be erased if only the first sub-block needs to be erased.

[0154] It is understandable that when programming the memory cell array block using block mode or sub-block mode, if all sub-blocks and blocks are programmed in reverse order, and both the first and second memory cell array sub-blocks have already stored data, then erasing only the first memory cell array sub-block is compatible with erasing the bottom sub-stack structure (the first memory cell array sub-block) in the memory cell array block using block mode. Therefore, erasing the first memory cell array sub-block is also permitted in this case.

[0155] In some embodiments, the method further includes:

[0156] When the first storage cell array sub-block is in the programming state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, the first storage cell array sub-block and the second storage cell array sub-block are erased together.

[0157] Here, if the first storage cell array sub-block has already been programmed and contains data, the system cannot perform a programming operation on the second storage cell array sub-block. Therefore, it is unnecessary for the system to perform an erase operation on the second storage cell array sub-block separately in this state. A better approach is to mark the second storage cell array sub-block as invalid, and then perform the erase operation on both the first and second storage cell array sub-blocks together when an erase operation is needed on the corresponding first storage cell array sub-block. Here, when the data stored in the second storage cell array sub-block no longer needs to be read and used, the data stored in the second storage cell array sub-block can be determined to be invalid. In some specific embodiments, when the data stored in the second storage cell array sub-block is about to be replaced by other updated data, the memory can determine that the current data in the second storage cell array sub-block is invalid based on instructions sent by the memory system or the host.

[0158] In some embodiments, the method further includes:

[0159] When the second storage cell array sub-block is in the programming state, the number of programming / erasing cycles of the first storage cell array sub-block is less than or equal to a first preset value. Here, when the second storage cell array sub-block is in the programming state, the number of programming / erasing cycles of the first storage cell array sub-block needs to be counted. If the second storage cell array sub-block is in the programming state and the data has not been erased, the number of programming / erasing cycles (PE cycles) of the first storage cell array sub-block cannot exceed the first preset value. If it exceeds the first preset value, the data stored in the first storage cell array sub-block must be erased and reprogrammed (i.e., refreshed), because multiple programming / erasing operations of the first storage cell array sub-block will interfere with the data stored in the second storage cell array sub-block. Here, the first preset value can be determined based on the actual interference situation. In some specific embodiments, the range of the first preset value is 10-100.

[0160] To improve the aforementioned data interference issues, the following two methods can be adopted:

[0161] Method 1: When the number of programming / erasing cycles of the first storage cell array sub-block exceeds the first preset value, programming / erasing operations on the first storage cell array sub-block are prohibited until the data stored in the second storage cell array sub-block is erased.

[0162] Here, when the number of programming / erasing cycles for the first storage cell array sub-block exceeds the first preset value, one solution is to restrict the first storage cell array sub-block from continuing to perform programming and erasing operations, thus limiting the interference to a certain range. After the data stored in the second storage cell array sub-block is erased, the count of the programming / erasing cycles for the first storage cell array sub-block can be reset to zero. At this point, the first storage cell array sub-block can continue to perform programming and erasing operations until a new count exceeds the first preset value.

[0163] Method 2: When the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, the data stored in the second storage cell array sub-block is erased and programmed. Subsequently, the first storage cell array sub-block can still be used to perform programming and erasing operations.

[0164] Here, when the number of programming / erase cycles for the first storage cell array sub-block exceeds the first preset value, another solution is to actively rewrite the data stored in the second storage cell array sub-block. This can mitigate the interference caused by multiple programming / erase operations on the first storage cell array sub-block on the data stored in the second storage cell array sub-block. After the data stored in the second storage cell array sub-block is rewritten, the count of the number of programming / erase cycles for the first storage cell array sub-block can be reset to zero. At this time, the first storage cell array sub-block can continue to perform programming and erasing operations until the new count exceeds the first preset value. In some embodiments, the method further includes:

[0165] A wear leveling algorithm is used to process the first and second memory cell array sub-blocks so that the difference between the number of programming / erase cycles of the first and second memory cell array sub-blocks is less than a second preset value.

[0166] Here, the second preset value can be adjusted according to the actual situation of the storage unit, such as its erase / write lifespan. In some specific embodiments, the second preset value can be set to 1%-10% of the erase / write lifespan of the storage unit. Here, the wear leveling algorithm can include both dynamic and static wear leveling algorithms. The basic idea of ​​the dynamic wear leveling algorithm is to write hot data to younger sub-blocks, that is, when using a new sub-block for writing, select those with fewer erase / write cycles. The basic idea of ​​the static wear leveling algorithm is to write cold data to older sub-blocks, that is, move cold data to sub-blocks with more erase / write cycles. Cold data refers to data that users do not frequently update; conversely, hot data refers to data that users update frequently. Older sub-blocks are those with more erase / write cycles; conversely, younger sub-blocks are those with fewer erase / write cycles. The memory can distinguish between older and younger sub-blocks by the number of erase cycles.

[0167] It should be noted that when operating on the determined memory cell array sub-block using the operation strategy provided in this embodiment, a core principle is that there cannot be any already programmed word lines or sub-blocks in the programming direction. Based on this, restrictions are set for programming / erasing operations. In this embodiment, both the first and second memory cell array sub-blocks are programmed using the same programming order as when performing write programming operations on the memory cell array blocks in block mode. The restrictions mentioned above regarding reverse programming are also the same in sequential programming, but the first memory cell array sub-blocks need to be swapped.

[0168] It is understood that when operating on a specific sub-block of the memory cell array using the operation strategy provided in this embodiment, some degrees of freedom in memory usage may be sacrificed. However, the compatibility between block mode and sub-block mode is relatively good, and there is no need to develop a program to implement two prohibition algorithms, which greatly saves the design work of new firmware to be compatible with block mode and sub-block mode.

[0169] The back pattern effect is particularly pronounced when using a sub-block pattern for read operations. Here, the back pattern effect mainly arises because the programming states of memory cells above the selected word line layer differ during programming verification and read operations. For example, when performing a word line layer WL... n During programming verification operations, the word line layer (WL) n+1 The memory cells corresponding to word line layers and above are in the erase state, while the memory cells corresponding to word line layers WL are in the erase state. n During a read operation, the word line layer (WL) n+1The memory units corresponding to word lines 1 and above are already in a programmed state of random data (randompattern), causing read operations to be performed at the word line level (WL). n+1 The series resistance of the memory cells corresponding to word line layers and above increases significantly, which leads to an increase in the threshold voltage during reading and a widening of the threshold voltage distribution. This increases the probability of reading retries.

[0170] Similarly, when performing read operations on the memory cell array block using the sub-block mode, a similar back model effect exists between the memory cell array sub-blocks. Based on the back model effect, the applied read voltage can be compensated during the first read operation based on the state of each memory cell array sub-block in the memory cell array block, thereby reducing the probability of read retry.

[0171] It should be noted that the back model effect is particularly pronounced in four-level cell QLCs. Compensating for the read voltage can reduce the probability of read retries caused by the back model effect.

[0172] In some embodiments, when performing erase, read, or program operations on the memory cell array block using a sub-block mode, the operation strategy of the other memory cell array sub-block is determined based on at least the state of one of the two memory cell array sub-blocks, including:

[0173] When performing a read operation on the memory cell array block in sub-block mode, the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing the read operation is determined according to the state of each memory cell array sub-block in the two memory cell array sub-blocks.

[0174] Here, the voltage control strategy includes whether to perform read voltage compensation on the memory cell array sub-block to be read. In some specific examples, a reference read voltage is applied to the word line layer of the memory cell array sub-block that does not require read voltage compensation, and a compensated read voltage is applied to the word line layer of the memory cell array sub-block that requires read voltage compensation. In some embodiments, determining the voltage control strategy used when the memory cell array sub-block in the programming state performs a read operation based on the state of each of the two memory cell array sub-blocks includes:

[0175] When the memory cell array sub-block to be read is in a programming state, and another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. When another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. The first read voltage is less than the second read voltage.

[0176] In some embodiments, the first read voltage and the second read voltage are obtained by superimposing a reference read voltage and a compensation voltage.

[0177] In some embodiments, the method further includes:

[0178] When another memory cell array sub-block is in an erase state, the read voltage offset flag of the memory cell array block is stored as a first state; the first state indicates that the compensation voltage is less than zero.

[0179] When another memory cell array sub-block is in a programming state, the read voltage offset flag of the memory cell array block is stored as a second state; the second state indicates that the compensation voltage is zero.

[0180] Here, the first state indicates that read voltage compensation needs to be performed on the memory cell array sub-block to be read; the second state indicates that read voltage compensation does not need to be performed on the memory cell array sub-block to be read; correspondingly, the second read voltage is the read voltage normally applied to the selected word line of the memory cell array sub-block to be read; the first read voltage is a smaller read voltage than the read voltage normally applied to the memory cell array sub-block to be read.

[0181] It should be noted that, under normal circumstances, the compensated read voltage (i.e., the first read voltage) is smaller than the normal uncompensated read voltage (i.e., the second read voltage). Of course, the embodiments of this disclosure can also support the case where the compensated read voltage is larger than the normal uncompensated read voltage.

[0182] In some specific examples, how to determine the read voltage offset flag of a memory cell array block based on the state of each memory cell array sub-block in two memory cell array sub-blocks can be found in Table 1. As shown in Table 1, when one memory cell array sub-block is in a programmed state and the other is not in a programmed state, the read voltage offset flag is YES (first state). In this case, when performing a read operation on the memory cell array sub-block in the programmed state, it is necessary to perform read voltage compensation on the memory cell array sub-block to be read. When both memory cell array sub-blocks are in a programmed state or neither is in a programmed state, the read voltage offset flag is NO (second state). In this case, when performing a read operation on the memory cell array sub-block in the programmed state, it is not necessary to perform read voltage compensation on the memory cell array sub-block to be read, i.e., the normal read voltage is used.

[0183] Table 1

[0184]

[0185] The memory can rely on its own resources to track the read voltage offset marker. Based on this, in some embodiments, the method further includes:

[0186] When the programming state of any sub-block of the memory cell array changes, the read voltage offset flag corresponding to the memory cell array block is updated.

[0187] In some specific examples, a corresponding register / latch can be added to the memory specifically for the read voltage offset flag, such as in Static Random-Access Memory (SRAM). Each cell array block requires at least one bit (two states) to indicate whether read voltage compensation should be performed on the cell array sub-block to be read, i.e., whether a Vrd offset is required during the read. At the start of a read, the memory checks this read voltage offset flag information to determine whether a Vrd offset needs to be applied; specifically, the application of the Vrd offset can be determined based on the states of the cell array sub-blocks shown in Table 1 above. Simultaneously, the register / latch needs to be updated during programming or erasing operations; that is, after any cell array sub-block in the cell array block performs the corresponding operation, the value of the read voltage offset flag corresponding to that cell array block is updated. Since SRAM and other registers are volatile when power is off, instructions for performing page erase checks can be defined in the memory. These instructions can be based on sub-blocks of the memory cell array. The memory system can perform a page erase check on each sub-block of the memory cell array after power-on, and thus obtain information about the read voltage offset mark based on the check results after power-on.

[0188] In other specific examples, the memory can also rely on the resources of the memory system to track the read voltage offset marker. This method will be described in more detail later in the section on memory systems.

[0189] It is understood that the voltage control strategy provided in the embodiments of this disclosure is used to determine whether to perform read voltage compensation on the memory cell array sub-block to be read. Specifically, based on the state of each memory cell array sub-block in the memory cell array block, the applied read voltage can be supplemented during the first read operation, thereby reducing the probability of read retry.

[0190] This disclosure also provides a memory, including: at least one memory cell array block and control logic; wherein...

[0191] The storage cell array block includes multiple layers of storage cells and word line layers corresponding to each layer of storage cells; the storage cell array block is divided into at least two storage cell array sub-blocks, and each storage cell array sub-block includes several layers of storage cells and word line layers corresponding to each layer of storage cells.

[0192] The control logic is coupled to the storage cell array block, and the control logic is configured to: perform erase, read, or program operations on the storage cell array block using block mode or sub-block mode; wherein, when performing erase, read, or program operations on the storage cell array block using sub-block mode, the operation strategy of the other storage cell array sub-block is determined based on the state of at least one of the two storage cell array sub-blocks.

[0193] Here, the memory may include the aforementioned memory cell array device and its peripheral circuitry. The memory cell array device includes at least one memory cell array block, and the peripheral circuitry includes control logic and the aforementioned row drivers, column drivers, voltage generators, and page buffers, etc.

[0194] In some embodiments, the memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

[0195] In some embodiments, the first memory cell array subblock includes a first number of word line layers, and the second memory cell array subblock includes a second number of word line layers, wherein the first number is different from the second number.

[0196] In some embodiments, the memory cell array block further includes a dummy memory cell layer and a corresponding dummy word line layer disposed between the first memory cell array sub-block and the second memory cell array sub-block.

[0197] In some embodiments, the control logic is configured to use the same programming order for both the first and second memory cell array sub-blocks as when performing write programming operations on the memory cell array blocks in block mode.

[0198] In some embodiments, the control logic is configured to program both the first and second memory cell array sub-blocks in reverse programming order; wherein the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom select gate; and the second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the top select gate to the memory cell layer closest to the dummy memory cell layer.

[0199] In some embodiments, the control logic is configured to: determine the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks.

[0200] In some embodiments, the control logic is configured to determine that the second memory cell array sub-block can be used to perform programming and erasing operations when the first memory cell array sub-block is in an erase state.

[0201] In some embodiments, the control logic is configured to: when the first memory cell array sub-block is in a programming state, determine that the second memory cell array sub-block is capable of performing an erase operation but not capable of performing a programming operation.

[0202] In some embodiments, the control logic is configured to determine that the first memory cell array sub-block can be used to perform programming and erasing operations when the second memory cell array sub-block is in an erase state or a programming state.

[0203] In some embodiments, the control logic is configured to: when the first storage cell array sub-block is in a programmed state and needs to be erased, and the second storage cell array sub-block is in a programmed state, to perform an erase operation on the first storage cell array sub-block.

[0204] In some embodiments, the control logic is configured to: when the first storage cell array sub-block is in a programmed state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, to perform an erase operation on both the first storage cell array sub-block and the second storage cell array sub-block together.

[0205] In some embodiments, the control logic is configured such that when the second memory cell array sub-block is in a programming state, the number of programming / erase cycles of the first memory cell array sub-block is less than or equal to a first preset value.

[0206] In some embodiments, the control logic is configured to: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, prohibit programming / erasing operations on the first storage cell array sub-block until the data stored in the second storage cell array sub-block is erased.

[0207] In some embodiments, the control logic is configured to: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, to perform erasing and programming operations on the data stored in the second storage cell array sub-block, and then the first storage cell array sub-block can still be used to perform programming and erasing operations.

[0208] In some embodiments, the range of the first preset value is 10-100.

[0209] In some embodiments, the control logic is configured to: process the first memory cell array sub-block and the second memory cell array sub-block using a wear leveling algorithm, such that the difference between the number of programming / erasing cycles of the first memory cell array sub-block and the number of programming / erasing cycles of the second memory cell array sub-block is less than a second preset value. In some embodiments, the control logic is configured to: when performing a read operation on the memory cell array block in sub-block mode, determine the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing a read operation based on the state of each memory cell array sub-block in the two memory cell array sub-blocks.

[0210] In some embodiments, the control logic is configured such that: when performing a read operation on the memory cell array block in sub-block mode, the memory cell array sub-block to be read is in a programming state; when another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read; and when another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read, wherein the first read voltage is less than the second read voltage.

[0211] In some embodiments, the control logic is configured such that the first read voltage and the second read voltage are obtained by superimposing a reference read voltage and a compensation voltage.

[0212] In some embodiments, the control logic is configured to: when another memory cell array sub-block is in an erase state, store the read voltage offset flag of the memory cell array block as a first state; the first state indicates that the compensation voltage is less than zero;

[0213] When another memory cell array sub-block is in a programming state, the read voltage offset flag of the memory cell array block is stored as a second state; the second state indicates that the compensation voltage is zero.

[0214] In some embodiments, the memory further includes registers corresponding to the memory cell array block; the register is configured to store read voltage offset flags corresponding to the memory cell array block;

[0215] The control logic is configured to update the state of the register when the programming state of any sub-block of the memory cell array changes.

[0216] Here, the register may include static random access memory, etc.

[0217] In some embodiments, the memory includes a three-dimensional NAND-type memory.

[0218] In some embodiments, the storage bits of each storage cell in the multi-layer storage cell include one or more bits.

[0219] In some embodiments, the storage bits of each storage unit include four bits.

[0220] This disclosure also provides a memory system, characterized in that it includes:

[0221] One or more memories as provided in embodiments of this disclosure; and

[0222] A storage controller that is coupled to and controls the memory.

[0223] Here, the memory system may refer to the aforementioned memory system 102. In some specific examples, the memory system may include a solid-state drive or a memory card.

[0224] In some embodiments, for each memory, the corresponding control logic in each memory is configured to: when any memory cell array sub-block in the corresponding memory performs a corresponding operation, send the state of the memory cell array sub-block to the memory controller;

[0225] The storage controller is configured to: store the state of any sub-block of the storage cell array in each memory, and send the state of all sub-blocks contained in the storage cell array block to the corresponding control logic before the corresponding control logic performs a read operation on the storage cell array block of the memory in sub-block mode.

[0226] Here, the memory can rely on the resources of the memory system to track the read voltage offset marker. Specifically, the memory system can store the status information of all memory cell array sub-blocks contained in all memory cell array blocks through registers, etc., and form the read voltage offset marker for the corresponding memory cell array block based on the status information of all these memory cell array sub-blocks. Before the corresponding control logic performs a read operation on the memory cell array block in sub-block mode, the memory system will pass this read voltage offset marker information to the memory during each read. Of course, in this scheme of tracking the read voltage offset marker, it is also necessary to update the value of the read voltage offset marker corresponding to the memory cell array block after any memory cell array sub-block in the memory cell array block performs a programming or erasing operation.

[0227] It should be noted that terms such as "first" and "second" are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0228] Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0229] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: At least one memory cell array block and control logic; wherein... The storage cell array block includes multiple layers of storage cells and word line layers corresponding to each layer of storage cells; the storage cell array block is divided into at least two storage cell array sub-blocks, and each storage cell array sub-block includes several layers of storage cells and word line layers corresponding to each layer of storage cells. The control logic is coupled to the storage cell array block, and the control logic is configured to: perform erase, read, or program operations on the storage cell array block using block mode or sub-block mode; wherein, when performing erase, read, or program operations on the storage cell array block using sub-block mode, the operation strategy of the other storage cell array sub-block is determined based on the state of at least one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks.

2. The memory according to claim 1, characterized in that, The memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

3. The memory according to claim 2, characterized in that, The first memory cell array subblock contains a first number of word line layers, and the second memory cell array subblock contains a second number of word line layers, wherein the first number and the second number may be the same or different.

4. The memory according to claim 2, characterized in that, The storage cell array block further includes a virtual storage cell layer and a corresponding virtual word line layer disposed between the first storage cell array sub-block and the second storage cell array sub-block.

5. The memory according to claim 4, characterized in that, The control logic is configured as follows: For both the first and second storage cell array sub-blocks, the same programming order is used as when performing write programming operations on the storage cell array blocks in block mode.

6. The memory according to claim 5, characterized in that, The control logic is configured to program both the first and second memory cell array sub-blocks in reverse programming order; wherein the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom selection gate; and the second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the top selection gate to the memory cell layer closest to the dummy memory cell layer.

7. The memory according to claim 6, characterized in that, The control logic is configured to determine that when the first memory cell array sub-block is in an erase state, the second memory cell array sub-block can be used to perform programming and erase operations.

8. The memory according to claim 6, characterized in that, The control logic is configured to determine that when the first memory cell array sub-block is in a programming state, the second memory cell array sub-block is capable of performing an erase operation but not of performing a programming operation.

9. The memory according to claim 6, characterized in that, The control logic is configured to determine that the first storage cell array sub-block can be used to perform programming and erasing operations when the second storage cell array sub-block is in an erase state or a programming state.

10. The memory according to claim 6, characterized in that, The control logic is configured to perform an erase operation on the first storage cell array sub-block when the first storage cell array sub-block is in a programming state and needs to be erased, and the second storage cell array sub-block is in a programming state at the same time.

11. The memory according to claim 10, characterized in that, The control logic is configured such that when the first storage cell array sub-block is in a programming state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, the first storage cell array sub-block and the second storage cell array sub-block are erased together.

12. The memory according to claim 6, characterized in that, The control logic is configured such that when the second memory cell array sub-block is in a programming state, the number of programming / erasing cycles of the first memory cell array sub-block is less than or equal to a first preset value.

13. The memory according to claim 12, characterized in that, The control logic is configured such that when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, programming / erasing operations on the first storage cell array sub-block are prohibited until the data stored in the second storage cell array sub-block is erased.

14. The memory according to claim 12, characterized in that, The control logic is configured such that when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, the data stored in the second storage cell array sub-block is erased and programmed, and then the first storage cell array sub-block can still be used to perform programming and erasing operations.

15. The memory according to claim 12, characterized in that, The range of the first preset value is 10-100.

16. The memory according to claim 2, characterized in that, The control logic is configured to use a wear leveling algorithm to process the first memory cell array sub-block and the second memory cell array sub-block, so that the difference between the number of programming / erasing cycles of the first memory cell array sub-block and the number of programming / erasing cycles of the second memory cell array sub-block is less than a second preset value.

17. The memory according to claim 1, characterized in that, The control logic is configured to: when performing a read operation on the memory cell array block in sub-block mode, determine the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing the read operation based on the state of each memory cell array sub-block in the two memory cell array sub-blocks.

18. The memory according to claim 17, characterized in that, The control logic is configured such that: when performing a read operation on the memory cell array block in sub-block mode, the memory cell array sub-block to be read is in a programming state; when another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read; when another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read, wherein the first read voltage is less than the second read voltage.

19. The memory according to claim 18, characterized in that, The first read voltage and the second read voltage are obtained by superimposing the reference read voltage and the compensation voltage.

20. The memory according to claim 19, characterized in that, The control logic is configured as follows: When another memory cell array sub-block is in an erase state, the read voltage offset flag of the memory cell array block is stored as a first state; the first state indicates that the compensation voltage is less than zero. When another memory cell array sub-block is in the programming state, the read voltage offset flag of the memory cell array block is stored as the second state; The second state indicates that the compensation voltage is zero.

21. The memory according to claim 20, characterized in that, The memory also includes a register corresponding to the memory cell array block; the register is configured to store a read voltage offset flag corresponding to the memory cell array block; The control logic is configured to update the state of the register when the programming state of any sub-block of the memory cell array changes.

22. A memory system, characterized in that, include: One or more memories as described in any one of claims 1 to 21; as well as A storage controller that is coupled to and controls the memory.

23. The memory system as claimed in claim 22, characterized in that, For each memory, the corresponding control logic in each memory is configured such that when any storage cell array sub-block in the corresponding memory performs a corresponding operation, the state of the storage cell array sub-block is sent to the memory controller; The storage controller is configured to: store the state of any sub-block of the storage cell array in each memory, and send the state of all sub-blocks contained in the storage cell array block to the corresponding control logic before the corresponding control logic performs a read operation on the storage cell array block of the memory in sub-block mode.

24. A method for operating a memory, characterized in that, The memory includes at least one memory cell array block and control logic; wherein... The storage cell array block includes multiple layers of storage cells and word line layers corresponding to each layer of storage cells; the storage cell array block is divided into at least two storage cell array sub-blocks, and each storage cell array sub-block includes several layers of storage cells and word line layers corresponding to each layer of storage cells. The method includes: The memory cell array blocks are erased, read, or programmed using either block mode or sub-block mode. When the memory cell array blocks are erased, read, or programmed using sub-block mode, the operation strategy for the other memory cell array sub-block is determined based on the state of at least one of the two memory cell array sub-blocks and the relative positional relationship between the two memory cell array sub-blocks.

25. The method of operating the memory according to claim 24, characterized in that, The memory cell array block includes at least: a first memory cell array sub-block disposed near the semiconductor layer and a second memory cell array sub-block located on the first memory cell array sub-block.

26. The method of operating the memory according to claim 25, characterized in that, The storage cell array block further includes a virtual storage cell layer and a corresponding virtual word line layer disposed between the first storage cell array sub-block and the second storage cell array sub-block.

27. The method of operating the memory according to claim 26, characterized in that, The method further includes: for both the first and second storage cell array sub-blocks, the same programming order is used as when performing write programming operations on the storage cell array blocks in block mode.

28. The method of operating the memory according to claim 27, characterized in that, The programming order for both the first and second sub-blocks of the memory cell array is the same as the programming order used when performing write programming operations on the memory cell array blocks in block mode, including: Both the first and second memory cell array sub-blocks are programmed in reverse programming order. Specifically, the first memory cell array sub-block is programmed sequentially from the memory cell layer closest to the dummy memory cell layer to the memory cell layer closest to the bottom selection gate. The second memory cell array sub-block is programmed sequentially from the memory cell layer closest to the top selection gate to the memory cell layer closest to the dummy memory cell layer.

29. The method of operating the memory according to claim 28, characterized in that, The step of determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes: When the first storage cell array sub-block is in the erase state, it is determined that the second storage cell array sub-block can be used to perform programming and erasure operations.

30. The method of operating the memory according to claim 28, characterized in that, The step of determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes: When the first storage cell array sub-block is in the programming state, it is determined that the second storage cell array sub-block can be used to perform an erase operation but cannot be used to perform a programming operation.

31. The method of operating the memory according to claim 28, characterized in that, The step of determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes: When the second storage cell array sub-block is in an erase state or a programming state, it is determined that the first storage cell array sub-block can be used to perform programming and erase operations.

32. The method of operating the memory according to claim 28, characterized in that, The method further includes: When the first storage cell array sub-block is in the programming state and needs to be erased, and the second storage cell array sub-block is in the programming state, the first storage cell array sub-block will be erased.

33. The method of operating the memory according to claim 32, characterized in that, The step of determining the operation strategy of the other storage cell array sub-block based on the state of one of the two storage cell array sub-blocks and the relative positional relationship between the two storage cell array sub-blocks includes: When the first storage cell array sub-block is in the programming state and needs to be erased, and the data stored in the second storage cell array sub-block is invalid, the first storage cell array sub-block and the second storage cell array sub-block are erased together.

34. The method of operating the memory according to claim 28, characterized in that, The method further includes: When the second storage cell array sub-block is in the programming state, the number of programming / erasing cycles of the first storage cell array sub-block is less than or equal to a first preset value.

35. The method of operating the memory according to claim 34, characterized in that, The method further includes: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, prohibiting programming / erasing operations on the first storage cell array sub-block until the data stored in the second storage cell array sub-block is erased.

36. The method of operating the memory according to claim 34, characterized in that, The method further includes: when the number of programming / erasing cycles of the first storage cell array sub-block is greater than the first preset value, erasing and programming operations are performed on the data stored in the second storage cell array sub-block, and then the first storage cell array sub-block can still be used to perform programming and erasing operations.

37. The method of operating the memory according to claim 25, characterized in that, The method further includes: A wear leveling algorithm is used to process the first and second memory cell array sub-blocks so that the difference between the number of programming / erase cycles of the first and second memory cell array sub-blocks is less than a second preset value.

38. The method of operating the memory according to claim 24, characterized in that, When performing erase, read, or program operations on the storage cell array block using the sub-block mode, the operation strategy for the other storage cell array sub-block is determined based on the state of at least one of the two storage cell array sub-blocks, including: When performing a read operation on the memory cell array block in sub-block mode, the voltage control strategy adopted by the memory cell array sub-block in the programming state when performing the read operation is determined according to the state of each memory cell array sub-block in the two memory cell array sub-blocks.

39. The method of operating the memory according to claim 38, characterized in that, The step of determining the voltage control strategy used when a memory cell array sub-block in the programming state performs a read operation based on the state of each memory cell array sub-block in the two memory cell array sub-blocks includes: When performing a read operation on the memory cell array block using the sub-block mode, the memory cell array sub-block to be read is in a programming state. When another memory cell array sub-block is in an erasure state, a first read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. When another memory cell array sub-block is in a programming state, a second read voltage is applied to the selected word line layer in the memory cell array sub-block to be read. The first read voltage is less than the second read voltage.

40. The method of operating the memory according to claim 39, characterized in that, The first read voltage and the second read voltage are obtained by superimposing the reference read voltage and the compensation voltage.

41. The method of operating the memory according to claim 40, characterized in that, The method further includes: When another memory cell array sub-block is in an erase state, the read voltage offset flag of the memory cell array block is stored as a first state; the first state indicates that the compensation voltage is less than zero. When another memory cell array sub-block is in a programming state, the read voltage offset flag of the memory cell array block is stored as a second state; the second state indicates that the compensation voltage is zero.

42. The method of operating the memory according to claim 40, characterized in that, The method further includes: When the programming state of any sub-block of the memory cell array changes, the read voltage offset flag corresponding to the memory cell array block is updated.

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