Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending in a second direction on the fin, a sealing layer on sidewalls of the gate structure, a first carbon peak concentration in the sealing layer, a first spacer layer on the sealing layer, a second carbon peak concentration in the first spacer layer, and a second spacer layer on the first spacer layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and particularly, to a fin field effect transistor (FinFET) semiconductor device and a method of fabricating the same. BACKGROUND

[0002] A fin field effect transistor (FinFET) is a non-planar multi-gate transistor having "fins" that extend vertically from a gate and form a source and a drain of the transistor. Multiple FinFETs can be coupled to one another to provide integrated circuit elements. Conductive layers can be formed over the fins to provide local interconnects between adjacent FinFETs.

[0003] The use of local interconnects enables higher packing density and lower resistance RSD. However, the formation of the slot contacts of the local interconnects increases the parasitic fringe capacitance (Cof), which significantly reduces the circuit speed. Therefore, there is a need to provide an improved semiconductor device that can suppress the capacitive coupling between the gate and the slot contact. SUMMARY

[0004] The main purpose of the present application is to provide an improved semiconductor device and a method of fabricating the same to solve the problems and shortcomings of the prior art.

[0005] In one aspect, the present application provides a semiconductor device, comprising a fin protruding from a substrate and extending along a first direction; a gate structure extending along a second direction over the fin; a sealing layer on sidewalls of the gate structure; a first carbon peak concentration in the sealing layer; a first spacer layer on the sealing layer; a second carbon peak concentration in the first spacer layer; and a second spacer layer on the first spacer layer.

[0006] According to an embodiment of the present application, the sealing layer comprises SiOCN and has a thickness of 40 angstroms, and the first spacer layer comprises SiOCN and has a thickness of 70 angstroms.

[0007] According to an embodiment of the present application, the first carbon peak concentration is located 80-84 angstroms below an interface between the first spacer layer and the second spacer layer.

[0008] According to an embodiment of the present application, the second spacer layer is a silicon-rich silicon nitride layer and has a thickness of 55 angstroms.

[0009] According to an embodiment of the present application, the second carbon peak concentration is located 80-84 angstroms below a top surface of the second spacer layer.

[0010] According to an embodiment of the present application, the gate structure comprises a gate dielectric layer and a metal gate on the gate dielectric layer.

[0011] According to an embodiment of the present disclosure, the semiconductor element further includes a source / drain region adjacent to the second spacer layer.

[0012] According to an embodiment of the present disclosure, the semiconductor element further includes an epitaxial layer in the source / drain region.

[0013] According to an embodiment of the present disclosure, the epitaxial layer includes SiP, SiC or SiGe.

[0014] According to an embodiment of the present disclosure, the dielectric constant of the sealing layer is less than 4.

[0015] Another aspect of the present disclosure provides a method for forming a semiconductor element, comprising: forming a fin protruding from a substrate and extending along a first direction; forming a gate structure extending along a second direction on the fin; forming a sealing layer on a sidewall of the gate structure; forming a first spacer layer on the sealing layer; performing a first carbon implantation fabrication process to implant carbon into the sealing layer such that the sealing layer has a first carbon peak concentration; forming a second spacer layer on the first spacer layer; and performing a second carbon implantation fabrication process to implant carbon into the first spacer layer such that the first spacer layer has a second carbon peak concentration.

[0016] According to an embodiment of the present disclosure, the sealing layer includes SiOCN and has a thickness of 40 angstroms, and the first spacer layer includes SiOCN and has a thickness of 70 angstroms.

[0017] According to an embodiment of the present disclosure, the first carbon peak concentration is located 80-84 angstroms below an interface between the first spacer layer and the second spacer layer.

[0018] According to an embodiment of the present disclosure, the second spacer layer is a silicon-rich silicon nitride layer and has a thickness of 55 angstroms.

[0019] According to an embodiment of the present disclosure, the second carbon peak concentration is located 80-84 angstroms below a top surface of the second spacer layer.

[0020] According to an embodiment of the present disclosure, the first carbon implantation fabrication process and the second carbon implantation fabrication process are performed at an implantation angle of 30 degrees, an implantation energy of 2 KeV and an implantation dose of 5E15 atoms / cm 2 .

[0021] According to an embodiment of the present disclosure, the method further includes forming a source / drain region adjacent to the second spacer layer.

[0022] According to an embodiment of the present disclosure, the method further includes forming an epitaxial layer in the source / drain region.

[0023] According to an embodiment of the present application, the epitaxial layer comprises SiP, SiC or SiGe.

[0024] According to an embodiment of the present application, the dielectric constant of the sealing layer is less than 4.

[0025] The main advantage of the present application is that a first carbon peak concentration is formed in the sealing layer and a second carbon peak concentration is formed in the first spacer layer, so that the dielectric constant of the sealing layer and the first spacer layer can be significantly reduced, thereby reducing the parasitic fringe capacitance. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1 to 6 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0027] MAIN ELEMENT SYMBOL EXPLANATION

[0028] 1 semiconductor device

[0029] 100 substrate

[0030] 102, 104 lightly doped drain region

[0031] 110 sealing layer

[0032] 110a first carbon peak concentration

[0033] 120 first spacer layer

[0034] 120a second carbon peak concentration

[0035] 130 second spacer layer

[0036] 200 gate structure

[0037] 210 gate dielectric layer

[0038] 220 conductive layer

[0039] 230 hard mask layer

[0040] 302, 304 recessed region

[0041] 302P, 304P epitaxial layer

[0042] 400 gate structure

[0043] 410 gate dielectric layer

[0044] 420 metal gate

[0045] 502, 504 source / drain region

[0046] F fin

[0047] ILD Insulating layer

[0048] IM Ion implantation process

[0049] CIM-1, CIM-2 Carbon implantation process

[0050] θ Tilt angle

[0051] R P1 , R P2 Carbon implantation projection range DETAILED DESCRIPTION

[0052] Hereinafter, details will be described with reference to the accompanying drawings, which constitute a part of the detailed description and are shown in a manner that can implement specific examples of the embodiments. The embodiments are described in sufficient details to enable one of ordinary skill in the art to practice.

[0053] Of course, other embodiments can be implemented, or any structural, logical, and electrical changes can be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting, but rather, the embodiments contained therein will be defined by the appended claims.

[0054] Referring to Figures 1 to 6 , which is a schematic diagram of a method for manufacturing a semiconductor device 1 according to an embodiment of the present application. As shown in Figure 1 , a substrate 100, such as a silicon substrate or other suitable semiconductor substrate, is first provided. Then, a fin F protruding from the substrate 100 and extending in a first direction is formed, and then a gate structure 200 extending in a second direction is formed on the fin F, where the first direction can be perpendicular to the second direction. Since the formation of the fin F and the gate structure 200 on the substrate 100 is a prior art, details thereof are not described.

[0055] According to an embodiment of the present application, the gate structure 200 can include a gate insulating layer 210, a conductive layer 220, and a hard mask layer 230, but is not limited thereto. For example, the gate insulating layer 210 can be a silicon oxide layer, the conductive layer 220 can be a polysilicon layer, and the hard mask layer 230 can be a silicon nitride layer.

[0056] Then, a sealing layer 110 is formed on the gate structure 200 and the fin F. According to an embodiment of the present application, the sealing layer 110 includes SiOCN and has a thickness of 35 to 45 angstroms, for example, 40 angstroms. According to an embodiment of the present application, the dielectric constant of the sealing layer 110 is less than 4.

[0057] According to embodiments of the present disclosure, the sealing layer 110 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. According to embodiments of the present disclosure, the sealing layer 110 is uniformly deposited on the sidewalls of the gate structure 200 and on the surface of the fin F.

[0058] As shown in FIG. 1C, next, an ion implantation fabrication process IM is performed to implant N-type or P-type dopants into the fin F to form lightly doped drain (LDD) regions 102 and 104. The LDD regions 102 and 104 are on both sides of the gate structure 200. Figure 2

[0059] As shown in FIG. 1D, next, a first spacer layer 120 is formed on the sealing layer 110. According to embodiments of the present disclosure, the first spacer layer 120 comprises SiOCN. According to embodiments of the present disclosure, the thickness of the first spacer layer 120 is between 65 to 75 angstroms, for example, 70 angstroms. The first spacer layer 120 can be formed by chemical vapor deposition or atomic layer deposition, or the like. Figure 3 After the first spacer layer 120 is deposited, a first carbon implant fabrication process CIM-1 is performed to implant carbon into the sealing layer 110 so that the sealing layer 110 has a first carbon peak concentration 110a. According to embodiments of the present disclosure, the first carbon implant fabrication process CIM-1 is performed at an angle of 30 degrees, an implant energy of 2 KeV, and an implant dose of 5E15 atoms / cm 2 Under the above conditions, the carbon implant projected range R P1 is 80-84 angstroms, for example, 82 angstroms.

[0060] According to embodiments of the present disclosure, as shown in the enlarged view shown in the circle in FIG. 1E, the first carbon peak concentration 110a is located 80-84 angstroms, for example, 82 angstroms, below the surface of the first spacer layer 120.

[0061] Figure 3 As shown in FIG. 1F, next, a second spacer layer 130 is formed on the first spacer layer 120. According to embodiments of the present disclosure, the second spacer layer 130 is a silicon-rich silicon nitride layer. According to embodiments of the present disclosure, the thickness of the second spacer layer 130 is about 55 angstroms. The second spacer layer 130 can be formed by chemical vapor deposition or atomic layer deposition, or the like.

[0062] As shown in FIG. 1G, next, a second carbon implant fabrication process CIM-2 is performed to implant carbon into the second spacer layer 130 so that the second spacer layer 130 has a second carbon peak concentration 130a. According to embodiments of the present disclosure, the second carbon implant fabrication process CIM-2 is performed at an angle of 30 degrees, an implant energy of 2 KeV, and an implant dose of 5E15 atoms / cm Figure 4 According to embodiments of the present disclosure, as shown in the enlarged view shown in the circle in FIG. 1H, the second carbon peak concentration 130a is located 80-84 angstroms, for example, 82 angstroms, below the surface of the second spacer layer 130.

[0063] ​​After depositing the second interstitial layer 130, a second carbon implantation process, CIM-2, is performed to implant carbon into the first interstitial layer 120 and the second interstitial layer 130, resulting in a second carbon peak concentration 120a in the first interstitial layer 120. According to an embodiment of the present invention, the second carbon implantation process, CIM-2, can also be performed at a tilt angle of 30 degrees θ, an implantation energy of 2 keV, and 5E15 atoms / cm². 2 The injection dose is determined. Under the above conditions, the carbon injection projection range R... P2 It is 80–84 angstroms, for example, 82 angstroms.

[0064] Next, as Figure 5 As shown, an anisotropic dry etching process is performed to etch the second spacer layer 130, the first spacer layer 120 and the sealing layer 110, forming recessed regions 302 and 304 in the fins F in the source / drain regions 502 and 504 on both sides of the gate structure 200, respectively.

[0065] According to embodiments of the present invention, such as Figure 5 As shown in the enlarged schematic diagram at the center circle, the second carbon peak concentration 120a is located 80 to 84 angstroms below the top surface of the second spacer layer 130, for example, 82 angstroms. The first carbon peak concentration 110a is located 80 to 84 angstroms below the interface between the first spacer layer 120 and the second spacer layer 130.

[0066] like Figure 6 As shown, an epitaxial fabrication process is then performed to grow epitaxial layers 302P and 304P from the recessed regions 302 and 304 within the source / drain regions 502 and 504 on both sides of the gate structure 200. According to embodiments of the present invention, epitaxial layers 302P and 304P may comprise SiP, SiC, or SiGe, but are not limited thereto. Next, a dielectric layer ILD is deposited, followed by a replacement metal gate (RMG) fabrication process to form the gate structure 400.

[0067] According to an embodiment of the present invention, the gate structure 400 includes a gate dielectric layer 410 and a metal gate 420 located on the gate dielectric layer 410. The gate dielectric layer 410 can be any suitable high dielectric constant material, and the metal gate 420 can include titanium, titanium nitride, copper, tungsten, aluminum, their alloys or any combination thereof.

[0068] The main advantage of this invention is that the sealing layer 110 has a first carbon peak concentration 110a and the first spacer wall layer 120 has a second carbon peak concentration 120a, which makes the dielectric constant (k) of the sealing layer 110 and the first spacer wall layer 120, which are composed of SiOCN, significantly reduced, thereby reducing the parasitic edge capacitance (Cof).

[0069] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. A semiconductor device, comprising: a fin protruding from a base and extending in a first direction; a gate structure extending in a second direction over the fin; a seal layer on sidewalls of the gate structure, the seal layer comprising SiOCN and having a thickness of 40 Angstroms; a first carbon peak concentration in the seal layer; a first spacer layer on the seal layer, the first spacer layer comprising SiOCN and having a thickness of 70 Angstroms; a second carbon peak concentration in the first spacer layer; and a second spacer layer on the first spacer layer, wherein the first carbon peak concentration is located 80-84 Angstroms below an interface between the first spacer layer and the second spacer layer. the second spacer layer is a silicon rich silicon nitride layer having a thickness of 55 Angstroms.

2. The semiconductor element according to claim 1, wherein the second carbon peak concentration is located 80-84 Angstroms below a top surface of the second spacer layer.

3. The semiconductor element according to claim 2, wherein the gate structure comprises a gate dielectric layer and a metal gate on the gate dielectric layer.

4. The semiconductor element according to claim 1, wherein further comprising a source / drain region adjacent to the second spacer layer.

5. The semiconductor element according to claim 1, wherein further comprising an epitaxial layer in the source / drain region.

6. The semiconductor element according to claim 5, wherein the epitaxial layer comprises SiP, SiC, or SiGe.

7. The semiconductor element according to claim 6, wherein a dielectric constant of the seal layer is less than 4.

8. The semiconductor element according to claim 1, wherein 9. A method of forming a semiconductor device, comprising: forming a fin protruding from a base and extending in a first direction; forming a gate structure extending in a second direction over the fin; forming a seal layer on sidewalls of the gate structure, the seal layer comprising SiOCN and having a thickness of 40 Angstroms; forming a first spacer layer on the seal layer, the first spacer layer comprising SiOCN and having a thickness of 70 Angstroms; performing a first carbon implantation fabrication process to implant carbon into the seal layer such that the seal layer has a first carbon peak concentration therein; forming a second spacer layer on the first spacer layer; and performing a second carbon implantation fabrication process to implant carbon into the first spacer layer such that the first spacer layer has a second carbon peak concentration, wherein the first carbon peak concentration is located 80-84 Angstroms below an interface between the first spacer layer and the second spacer layer. the second spacer layer is a silicon rich silicon nitride layer having a thickness of 55 Angstroms. the second carbon peak concentration is located 80-84 Angstroms below a top surface of the second spacer layer.

10. The method of claim 9, wherein, further comprising:

11. The method of claim 10, wherein, forming a source / drain region adjacent to the second spacer layer.

12. The method of claim 9, wherein, The first carbon implant fabrication process and the second carbon implant fabrication process are performed with a 30 degree tilt angle, a 2 KeV implant energy, and a 5E15 atoms / cm 2 implant dose.

13. The method of claim 9, wherein, further comprising: forming an epitaxial layer in the source / drain region.

14. The method of claim 13, wherein, the epitaxial layer comprises SiP, SiC, or SiGe. a dielectric constant of the seal layer is less than 4.

15. The method of claim 14, wherein, ​ 16. The method of claim 9, wherein, ​

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