Bulk-Gate Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor and Fabrication Method Thereof

Abstract

The present invention provides a bulk-gate laterally diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof, including: a substrate; a drift region of a first conductivity type; a body region of a second conductivity type; a source region of the first conductivity type, formed in the body region; a body lead-out region of the second conductivity type, formed in the body region; a drain region of the first conductivity type, formed in the drift region and arranged at intervals with the body region; an auxiliary depletion region of the second conductivity type, formed on the surface layer of the drift region between the body region and the drain region; a gate structure, spanning over the source region and the drift region; a bulk-gate structure, including a plurality of bulk trench gates distributed in the auxiliary depletion region and a lead-out structure of the bulk trench gates. When the field effect transistor conducts forward, the bulk trench gates are applied with a first voltage having the same polarity as the gate structure to reduce the on-resistance of the field effect transistor. When the field effect transistor is turned off, the bulk trench gates are applied with a second voltage having a polarity opposite to that of the first voltage to increase the reverse breakdown voltage of the field effect transistor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device design and manufacturing, and particularly relates to a manufacturing method of a bulk-gate laterally-diffused metal-oxide semiconductor field effect transistor. Background Art

[0002] A laterally-diffused metal-oxide semiconductor field effect transistor (LDMOS) is often used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance and power control. It is commonly used in radio frequency power circuits. LDMOS is a power device with a double-diffusion structure. In this technology, two injections are performed in the same source and drain regions. One injection is of a relatively high concentration of arsenic (As), and the other injection is of a relatively low concentration of boron (B). After the injections, a high-temperature drive-in process is carried out. Since boron diffuses faster than arsenic, it will diffuse further laterally under the gate boundary, forming a channel with a concentration gradient. Its channel length is determined by the difference in the distances of these two lateral diffusions. To increase the breakdown voltage, there is a drift region between the active region and the drain region. The drift region in LDMOS is the key to the design of this type of device. The impurity concentration in the drift region is relatively low. Therefore, when LDMOS is connected to a high voltage, the drift region, being a high-resistance region, can withstand a higher voltage.

[0003] With the development of high-voltage power devices, the performance of the core device LDMOS in a monolithic integrated power IC is particularly important. The optimization of the on-resistance is one of the key factors for improving the performance of LDMOS. In current LDMOS devices, there are more and more methods for optimizing the drift region structure to reduce the on-resistance. The most common ones are: the reduced surface field technology (RESURF) and surface superjunction, etc. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method of a bulk-gate laterally-diffused metal-oxide semiconductor field effect transistor, which is used to solve the problem of the relatively high on-resistance of LDMOS devices in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a bulk-gate lateral double-diffused metal oxide semiconductor field effect transistor, which includes: a substrate; a drift region of a first conductivity type formed on the substrate; a body region of a second conductivity type formed in the drift region; a source region of the first conductivity type formed on the surface layer of the body region; a body lead-out region of the second conductivity type formed on the surface layer of the body region; a drain region of the first conductivity type formed on the surface layer of the drift region and arranged at intervals with the body region; an auxiliary depletion region of the second conductivity type formed on the surface layer of the drift region between the body region and the drain region; a gate structure spanning over the source region and the drift region; and a bulk-gate structure including a plurality of bulk trench gates distributed in the auxiliary depletion region and lead-out structures of the bulk trench gates.

[0006] Optionally, the bulk trench gate includes a trench located in the auxiliary depletion region, an in-trench dielectric layer located on the sidewall of the trench, and a conductive medium filled in the in-trench dielectric layer, and the depth of the trench is less than the depth of the auxiliary depletion region.

[0007] Optionally, the plurality of bulk trench gates are arranged at intervals in a first direction to form a plurality of bulk trench gate columns, and are arranged at intervals in a second direction to form a plurality of bulk trench gate rows. The first direction is the direction from the source region towards the drain region, and the second direction intersects with the first direction. Among them, each bulk trench gate row is led out by a gate line, and any one of the gate lines is led out to an independent control terminal, or a plurality of the gate lines are led out to a common control terminal.

[0008] Optionally, the bulk trench gates between any two adjacent bulk trench gate columns are arranged in a staggered manner in the second direction.

[0009] Optionally, when the field effect transistor conducts forward, the bulk trench gate is applied with a first voltage having the same polarity as the gate structure to reduce the on-resistance of the field effect transistor. When the field effect transistor is turned off, the bulk trench gate is applied with a second voltage having a polarity opposite to that of the first voltage to increase the reverse breakdown voltage of the field effect transistor.

[0010] Optionally, the depth range of the auxiliary depletion region is 2 micrometers to 4 micrometers, the width of the bulk trench gate is 1 micrometer to 2 micrometers, and the distance between two adjacent bulk trench gates is 2 micrometers to 3 micrometers.

[0011] Optionally, an insulating layer is further formed on the bulk-gate structure, a through hole exposing the bulk trench gate is formed in the insulating layer, and a lead-out structure of the bulk trench gate is formed on the through hole and the insulating layer.

[0012] The present invention also provides a manufacturing method for a bulk-gate laterally diffused metal oxide semiconductor field effect transistor, comprising the steps of: providing a substrate, and forming a drift region of a first conductivity type on the substrate; forming an auxiliary depletion region of a second conductivity type on the surface layer of the drift region; forming a plurality of bulk trench gates in the auxiliary depletion region; forming a body region of a second conductivity type in the drift region; forming a source region of a first conductivity type and a body lead-out region of a second conductivity type on the surface layer of the body region, and forming a drain region of a first conductivity type on the surface layer of the drift region, wherein the auxiliary depletion region is located between the drain region and the body region; forming a gate structure between the source region and the drift region; and forming a lead-out structure on the bulk trench gates.

[0013] Optionally, forming a plurality of bulk trench gates in the auxiliary depletion region includes: etching a plurality of trenches in the auxiliary depletion region through a photolithography process and an etching process, the depth of the trenches being less than the depth of the auxiliary depletion region; forming an in-trench dielectric layer on the side walls of the trenches through a thermal oxidation process; and filling a conductive medium in the in-trench dielectric layer through a deposition process.

[0014] Optionally, the plurality of bulk trench gates formed in the auxiliary depletion region are arranged at intervals in a first direction to form a plurality of bulk trench gate columns, and are arranged at intervals in a second direction to form a plurality of bulk trench gate rows. The first direction is the direction from the source region towards the drain region, and the second direction intersects with the first direction. Among them, the bulk trench gates between any two adjacent bulk trench gate columns are arranged in a staggered manner in the second direction; forming the lead-out structure of the bulk trench gates based on the through holes includes a plurality of gate lines. Each bulk trench gate row is led out by one gate line, and any one of the gate lines is led out to an independent control terminal, or a plurality of the gate lines are led out to a common control terminal.

[0015] Optionally, the drift region is formed through an ion implantation process and a high-temperature drive-in process.

[0016] Optionally, the depth range of the auxiliary depletion region is 2 micrometers to 4 micrometers, the width of the bulk trench gate is 1 micrometer to 2 micrometers, and the spacing between two adjacent bulk trench gates is 2 micrometers to 3 micrometers.

[0017] Optionally, forming a lead-out structure on the bulk trench gates includes the steps of: forming an insulating layer on the surface of the drift region; forming a through hole exposing the bulk trench gates in the insulating layer, and forming the lead-out structure of the bulk trench gates based on the through hole.

[0018] As described above, the manufacturing method for the bulk-gate laterally diffused metal oxide semiconductor field effect transistor of the present invention has the following beneficial effects:

[0019] The present invention forms body trench gates with a certain depth and arranged in an array in the drift region. The depth of the body trench gates is not greater than the depth of the auxiliary depletion region. When the field effect transistor conducts forward, the body trench gates can be applied with a first voltage of the same polarity as the gate structure, for example, voltage is applied together with the gate structure, attracting carriers near the body trench gates, realizing the inversion of the conduction type of the auxiliary depletion region, increasing the concentration of majority carriers in the drift region, thereby greatly reducing the on-resistance of the device. When the field effect transistor is turned off, the body trench gates are applied with a voltage of the opposite polarity to the gate structure to increase the reverse breakdown voltage of the field effect transistor.

[0020] The body trench gates of the present invention are arranged at intervals in a plurality of body trench gate columns in a first direction and at intervals in a plurality of body trench gate rows in a second direction. The first direction is the direction from the source region to the drain region. Each body trench gate row is led out by a gate line, and any gate line is led out to an independent control terminal, or a plurality of gate lines are led out to a common control terminal. By adjusting the voltage applied to the independent control terminal or the common control terminal, the resistance or depletion situation of the drift region can be effectively adjusted, expanding the application scope or application field of the field effect transistor. Description of the Drawings

[0021] Figure 1 It shows a three-dimensional schematic structural diagram of a body-gate laterally diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

[0022] Figure 2 It shows a cross-sectional structural diagram of a body-gate laterally diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

[0023] Figure 3 It shows a schematic diagram of the principle of reducing the on-voltage when the body-gate laterally diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention conducts.

[0024] Figures 4 to 11 It shows a schematic structural diagram presented by each step of the manufacturing method of a body-gate laterally diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

[0025] Element Number Description

[0026] 100 Body trench gate

[0027] 101 Substrate

[0028] 102 Drift region

[0029] 103 Buffer region

[0030] 104 Body region

[0031] 105 Body lead-out region

[0032] 106 Source region

[0033] 107 Gate structure

[0034] 108 Drain region

[0035] 109 Dielectric layer in the groove

[0036] 110 Conductive medium

[0037] 111 Auxiliary depletion region

[0038] 112 Gate line

[0039] 113 Insulating layer

[0040] 114 Majority carriers Detailed implementation manners

[0041] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be locally enlarged out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0043] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation besides the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0044] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0046] As Figures 1 to 3 shown, where Figure 1 it shows a three-dimensional schematic structure diagram of the bulk-gate laterally double-diffused metal oxide semiconductor field-effect transistor of this embodiment. In order to fully display all the characteristic morphologies of the bulk-gate laterally double-diffused metal oxide semiconductor field-effect transistor of this embodiment, Figure 1 part of the insulating layer and the lead-out structure above the bulk trench gate are schematically removed, which does not represent the final morphology of the bulk-gate laterally double-diffused metal oxide semiconductor field-effect transistor of this embodiment. Figure 2 It shows a cross-sectional structure diagram of the bulk-gate laterally double-diffused metal oxide semiconductor field-effect transistor of this embodiment. This embodiment provides a bulk-gate laterally double-diffused metal oxide semiconductor field-effect transistor (bulk-gate LDMOS). The field-effect transistor includes a substrate 101, a drift region 102 of the first conductivity type, a body region 104 of the second conductivity type, a source region 106 of the first conductivity type, a body lead-out region 105 of the second conductivity type, a drain region 108 of the first conductivity type, an auxiliary depletion region 111 of the second conductivity type, a gate structure 107, and a bulk-gate structure.

[0047] As an example, the substrate can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon-on-insulator) or a GOI (germanium-on-insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (germanium-silicon-on-insulator), etc. In this embodiment, the substrate is a high-resistivity Si substrate, and the resistivity of the substrate is preferably 60 ohm·cm to 140 ohm·cm. The bulk-gate LDMOS of this embodiment can achieve substrate depletion through a high-resistivity Si substrate, thereby increasing the breakdown voltage of the bulk-gate LDMOS.

[0048] As Figure 2As shown, the drift region 102 of the first conductivity type is formed on the substrate 101. The material of the drift region 102 may be the same as or different from that of the substrate 101, and the conductivity type of the drift region 102 is opposite to that of the substrate 101. In this embodiment, the drift region 102 is selected to be the same silicon material as the substrate 101, and the substrate 101 is of the second conductivity type. The depth range of the drift region 102 is 10 μm to 20 μm, and the doping concentration range of the drift region 102 is 3.5E12 cm -3 ~6.5E12 cm -3 , so as to ensure both the depletion of the substrate 101 of the bulk-gate LDMOS and the current conduction path during conduction.

[0049] As Figure 2 shown, the body region 104 of the second conductivity type is formed in the drift region 102. In this embodiment, the body region 104 penetrates from the upper surface to the lower surface of the drift region 102 and contacts the substrate 101. The doping concentration of the body region 104 is 2E12 cm -3 ~4E12 cm -3 . In this embodiment, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. Of course, in other embodiments, the first conductivity type may also be P-type conductivity, and the second conductivity type may also be N-type conductivity.

[0050] As Figure 2 shown, the source region 106 of the first conductivity type and the body lead-out region 105 of the second conductivity type are formed on the surface layer of the body region 104. The doping concentration of the body lead-out region 105 is 1E15 cm -3 ~5E15 cm -3 , and the doping concentration of the source region 106 is 2E15 cm -3 ~4E15 cm -3 . In this embodiment, the source region 106 of the first conductivity type and the body lead-out region 105 of the second conductivity type are arranged adjacent to each other to make the device more compact and reduce the device area.

[0051] As Figure 2As shown, the drain region 108 of the first conduction type is formed on the surface layer of the drift region 102 and is arranged at intervals with the body region 104. In this embodiment, the field effect transistor further includes a buffer region 103 of the first conduction type located between the drain region 108 and the drift region 102. The doping concentration of the buffer region 103 is preferably less than that of the drain region 108 and greater than that of the drift region 102. The junction depth of the buffer region 103 is greater than that of the drain region 108 and less than that of the drift region 102. Preferably, the doping concentration range of the buffer region 103 is 1E12cm -3 ~4E12cm -3 , and the buffer region 103 can effectively improve the on-state breakdown voltage of the field effect transistor during forward conduction.

[0052] As Figure 2 shown, the auxiliary depletion region 111 of the second conduction type is formed on the surface layer of the drift region 102 between the body region 104 and the drain region 108. In this embodiment, the depth range of the auxiliary depletion region 111 is 2 microns to 4 microns, that is, the junction depth range of the auxiliary depletion region 111 is 2 microns to 4 microns. The auxiliary depletion region 111 can assist the drift region 102 to deplete and improve the reverse voltage withstand performance of the device.

[0053] As Figure 2 shown, the gate structure 107 straddles the source region 106 and the drift region 102. It can also be understood that the gate structure is formed on the upper surface of the body region. One side of the gate structure is adjacent to the drain region or covers part of the drain region, and the other side of the gate structure covers part of the drift region. The gate structure 107 is used to control the conduction and cut-off of the channel below it.

[0054] As Figure 2 shown, the body gate structure includes a plurality of body trench gates 100 distributed in the auxiliary depletion region 111 and the lead-out structure of the body trench gates 100. In this embodiment, an insulating layer 113 is further formed on the body gate structure. Through holes exposing the body trench gates are formed in the insulating layer 113, and the lead-out structure of the body trench gates is formed on the through holes and the insulating layer.

[0055] As an example, the body trench gate 100 includes a trench located in the auxiliary depletion region 111, an in-trench dielectric layer 109 on the sidewall of the trench, and a conductive dielectric 110 filled in the in-trench dielectric layer 109. The depth of the trench is less than the depth of the auxiliary depletion region 111. The width of the body trench gate 100 is 1 to 2 micrometers, and the spacing between two adjacent body trench gates 100 is 2 to 3 micrometers. The body trench gate 100 is used to control the inversion of the region around the trench in the auxiliary depletion region 111, which can greatly reduce the on-resistance of the device. The function of the body trench gate 100 in the device is different from that of the gate structure 107 in the device. The potential externally connected to the body trench gate 100 is the same as or different from the potential externally connected to the gate structure 107. That is, the gate structure 107 directly controls the conduction and cutoff of the device channel and is the gate in the general sense of the device, while the body trench gate 100 controls the inversion of the region around the trench in the auxiliary depletion region 111 and belongs to the control structure for inverting the auxiliary depletion region 111.

[0056] In this embodiment, a plurality of the body trench gates 100 are arranged at intervals in a first direction to form a plurality of columns of body trench gates 100, and are arranged at intervals in a second direction to form a plurality of rows of body trench gates 100. The first direction is the direction from the source region 106 towards the drain region 108, and the second direction intersects the first direction. Among them, the body trench gates 100 between any two adjacent columns of body trench gates 100 are arranged in a staggered manner in the second direction. Each row of body trench gates 100 is led out by a gate line 112, and any one of the gate lines 112 is led out to an independent control terminal IO1, IO2, IO3... IOn, as Figure 3 shown, or a plurality of the gate lines 112 are led out to a common control terminal. Of course, in other embodiments, a plurality of the body trench gates 100 may also be arranged in a matrix array or other ways, and are not limited to the examples listed here. In this embodiment, by adjusting the voltage applied to the independent control terminal or the common control terminal, the resistance or depletion condition of the drift region 102 can be effectively adjusted, and the application range or application field of the field effect transistor can be expanded. In other embodiments, the first direction is the direction from the source region 106 towards the drain region 108 (that is, the first direction is the direction of the conductive channel length of the device), and the second direction is the direction of the conductive channel width of the device.

[0057] As Figure 3As shown, for the bulk trench gate lateral double-diffused metal oxide semiconductor field effect transistor of the present application, when the field effect transistor conducts forward, a first voltage with the same polarity as the gate structure 107 is applied to the bulk trench gate 100, attracting carriers near the bulk trench gate 100, realizing the inversion of the conduction type of the auxiliary depletion region 111, and increasing the concentration of majority carriers 114 in the drift region 102 to reduce the on-resistance of the field effect transistor. In other embodiments, when the field effect transistor conducts forward, the potentials applied to the bulk trench gate 100 and the gate structure 107 are both high potentials relative to the source region 106. The magnitudes of the potentials applied to the bulk trench gate 100 and the gate structure 107 may be different or the same. That is, the voltages applied to the independent control terminals IO1, IO2, IO3... IOn are different from or the same as the gate structure 107, and the voltages applied to the independent control terminals IO1, IO2, IO3... IOn may also be the same or different.

[0058] When the field effect transistor is turned off, a second voltage with the opposite polarity to the first voltage is applied to the bulk trench gate 100 to increase the reverse voltage withstand of the field effect transistor. In other embodiments, when the field effect transistor is turned off, the voltage applied to the bulk trench gate 100 is different from the gate structure 107. That is, the voltages applied to the independent control terminals IO1, IO2, IO3... IOn are different from the gate structure 107, and the voltages applied to the independent control terminals IO1, IO2, IO3... IOn decrease in sequence.

[0059] As Figures 4 to 11 shown, the present embodiment also provides a manufacturing method for a bulk trench gate lateral double-diffused metal oxide semiconductor field effect transistor, including the steps:

[0060] As Figure 4 shown, perform step 1), provide a substrate 101, and form a drift region 102 of a first conduction type on the substrate 101.

[0061] As an example, the substrate 101 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator) or a GOI (germanium on insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate is a high-resistivity Si substrate, and the resistivity of the substrate is preferably 60 ohm·cm to 140 ohm·cm. The bulk-gate LDMOS of this embodiment can achieve substrate depletion through a high-resistivity Si substrate, thereby improving the breakdown voltage of the bulk-gate LDMOS. The substrate in this embodiment is of the second conductive type.

[0062] For example, a drift region 102 of the first conductive type can be formed on the substrate by a vapor phase epitaxy process or by high-temperature annealing after ion implantation. The material of the drift region 102 can be the same as or different from that of the substrate 101. In this embodiment, the drift region 102 is selected to be the same silicon material as the substrate 101. The depth range of the drift region 102 is 10 microns to 20 microns, and the doping concentration range of the drift region 102 is 3.5E12 cm -3 ~6.5E12 cm -3 , so as to ensure both substrate depletion of the bulk-gate LDMOS and the current conduction path during conduction.

[0063] As Figure 5 shown, perform step 2), and form an auxiliary depletion region 111 of the second conductive type on the surface layer of the drift region 102.

[0064] In this embodiment, the auxiliary depletion region 111 can be formed by high-temperature annealing after ion implantation, and the depth range of the auxiliary depletion region 111 is 2 microns to 4 microns. The auxiliary depletion region 111 can assist the drift region 102 in depletion and improve the reverse breakdown voltage performance of the device.

[0065] As Figure 6 shown, perform step 3), and form a plurality of bulk trench gates 100 in the auxiliary depletion region 111.

[0066] Specifically, forming a plurality of bulk trench gates 100 in the auxiliary depletion region 111 includes:

[0067] Step 3-1) Etch a plurality of trenches in the auxiliary depletion region 111 through a photolithography process and an etching process, and the depth of the trenches is less than the depth of the auxiliary depletion region 111.

[0068] In this embodiment, a plurality of bulk trench gates 100 formed in the auxiliary depletion region 111 are arranged at intervals in a first direction to form a plurality of columns of bulk trench gates 100, and are arranged at intervals in a second direction to form a plurality of rows of bulk trench gates 100. The first direction is the direction from the source region 106 towards the drain region 108, and the second direction intersects the first direction. Among them, the bulk trench gates 100 between any two adjacent columns of bulk trench gates 100 are arranged in a staggered manner in the second direction. Of course, in other embodiments, the plurality of bulk trench gates 100 may also be arranged in a matrix or other ways, and are not limited to the examples listed here.

[0069] In this embodiment, the width of the bulk trench gate 100 is 1 to 2 micrometers, and the distance between two adjacent bulk trench gates 100 is 2 to 3 micrometers.

[0070] Step 3-2) Form an in-trench dielectric layer 109 on the sidewalls of the trench through a thermal oxidation process.

[0071] Step 3-3), fill a conductive medium 110 in the in-trench dielectric layer 109 through a deposition process. The conductive medium 110 may be, for example, a polysilicon layer.

[0072] In this embodiment, a plurality of bulk trench gates 100 are arranged at intervals in a first direction to form a plurality of columns of bulk trench gates 100, and are arranged at intervals in a second direction to form a plurality of rows of bulk trench gates 100. The first direction is the direction from the source region 106 towards the drain region 108, and the second direction intersects the first direction. Among them, the bulk trench gates 100 between any two adjacent columns of bulk trench gates 100 are arranged in a staggered manner in the second direction, and each row of bulk trench gates 100 is led out by a gate line 112. Any one of the gate lines 112 is led out to an independent control terminal IO1, IO2, IO3... IOn, as Figure 3 shown, or a plurality of the gate lines 112 are led out to a common control terminal. In this embodiment, by adjusting the voltage applied to the independent control terminal or the common control terminal, the resistance or depletion condition of the drift region 102 can be effectively adjusted, and the application range or application field of the field effect transistor can be expanded. In other embodiments, the first direction is the direction from the source region 106 towards the drain region 108 (that is, the first direction is the direction of the conductive channel length of the device), and the second direction is the direction of the conductive channel width of the device.

[0073] As Figure 7 shown, perform step 4), and form a body region 104 of the second conductivity type in the drift region 102.

[0074] In this embodiment, the body region 104 penetrates from the upper surface of the drift region 102 to the lower surface of the drift region 102 and contacts the substrate 101. The doping concentration of the body region 104 is 2E12cm -3~4E12 cm -3 In this embodiment, the first conduction type is N-type conduction, and the second conduction type is P-type conduction. Of course, in other embodiments, the first conduction type can also be P-type conduction, and the second conduction type can also be N-type conduction.

[0075] As Figure 8 shown, step 5) is performed to form a source region 106 of the first conduction type and a body lead-out region 105 of the second conduction type on the surface layer of the body region 104, and a drain region 108 of the first conduction type is formed on the surface layer of the drift region 102, wherein the auxiliary depletion region 111 is located between the drain region 108 and the body region 104.

[0076] The doping concentration of the body lead-out region 105 is 1E15 cm -3 ~5E15 cm -3 The doping concentration of the source region 106 is 2E15 cm -3 ~4E15 cm -3 In this embodiment, the source region 106 of the first conduction type and the body lead-out region 105 of the second conduction type are arranged adjacent to each other, so that the device is more compact and the device area is reduced.

[0077] In this embodiment, a buffer region 103 of the first conduction type is further formed between the drain region 108 and the drift region 102. The doping concentration of the buffer region 103 is preferably less than the doping concentration of the drain region 108 and greater than the doping concentration of the drift region 102. The junction depth of the buffer region 103 is greater than the junction depth of the drain region 108 and less than the junction depth of the drift region 102. Preferably, the doping concentration range of the buffer region 103 is 1E12 cm -3 ~4E12 cm -3 The buffer region 103 can effectively improve the on-state breakdown voltage of the field effect transistor during forward conduction.

[0078] As Figure 9 shown, step 6) is performed to form an insulating layer 113 on the surface of the drift region 102. For example, the insulating layer 113 can be formed on the surface of the drift region 102 by using processes such as thermal oxidation process or plasma enhanced chemical vapor deposition process. The insulating layer 113 can be silicon dioxide.

[0079] As Figure 10 shown, step 7) is performed to form a gate structure 107 between the source region 106 and the drift region 102. The gate structure 107 is used to control the conduction and cutoff of the channel below it.

[0080] As Figure 11As shown, step 8) is performed to form a through hole in the insulating layer 113 to expose the body trench gate 100, and a lead-out structure of the body trench gate 100 is formed based on the through hole.

[0081] In this embodiment, forming the lead-out structure of the body trench gate 100 based on the through hole includes a plurality of gate lines 112. Each row of the body trench gates 100 is led out by a gate line 112. Any one of the gate lines 112 is led out to an independent control terminal IO1, IO2, IO3... IOn, or a plurality of the gate lines 112 are led out to a common control terminal. In this embodiment, by adjusting the voltage applied to the independent control terminal or the common control terminal, the resistance or depletion condition of the drift region 102 can be effectively adjusted, expanding the application range or application field of the field effect transistor.

[0082] As Figure 3 shown, for the body-gate laterally diffused metal oxide semiconductor field effect transistor of the present application, when the field effect transistor conducts forward, a first voltage with the same polarity as the gate structure 107 is applied to the body trench gate 100 to attract carriers near the body trench gate 100, realizing the inversion of the conductivity type of the auxiliary depletion region 111, increasing the concentration of majority carriers 114 in the drift region 102, so as to reduce the on-resistance of the field effect transistor. When the field effect transistor is turned off, a second voltage with the opposite polarity to the first voltage is applied to the body trench gate 100 to adjust the depletion ability, so as to increase the reverse breakdown voltage of the field effect transistor.

[0083] As described above, the manufacturing method of the body-gate laterally diffused metal oxide semiconductor field effect transistor of the present invention has the following beneficial effects:

[0084] The present invention forms body trench gates 100 with a certain depth and arranged in an array in the drift region 102. The depth of the body trench gates 100 is not greater than the depth of the auxiliary depletion region 111. When the field effect transistor conducts forward, a first voltage with the same polarity as the gate structure 107, such as applying voltage together with the gate structure 107, can be applied to the body trench gate 100 to attract carriers near the body trench gate 100, realizing the inversion of the conductivity type of the auxiliary depletion region 111, increasing the concentration of majority carriers 114 in the drift region 102, thereby greatly reducing the on-resistance of the device. When the field effect transistor is turned off, a voltage with the opposite polarity to the gate structure 107 is applied to the body trench gate 100 to increase the reverse breakdown voltage of the field effect transistor.

[0085] The body trench gates 100 of the present invention are arranged at intervals in multiple columns of body trench gates 100 along a first direction, and are arranged at intervals in multiple rows of body trench gates 100 along a second direction. The first direction is the direction from the source region 106 towards the drain region 108. The body trench gates 100 between any two adjacent columns of body trench gates 100 are arranged in a staggered manner in the second direction. Each row of body trench gates 100 is led out by a gate line 112. Any one gate line 112 is led out to an independent control terminal, or multiple gate lines 112 are led out to a common control terminal. By adjusting the voltage applied to the independent control terminal or the common control terminal, the resistance or depletion condition of the drift region 102 can be effectively adjusted, and the application range or application field of the field effect transistor can be expanded.

[0086] Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0087] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A bulk-gate laterally double-diffused metal oxide semiconductor field effect transistor, characterized in that, The field effect transistor includes: A substrate; A drift region of a first conductivity type, formed on the substrate; A body region of a second conductivity type, formed within the drift region; A source region of a first conductivity type, formed on the surface layer of the body region; A body lead-out region of a second conductivity type, formed on the surface layer of the body region; A drain region of a first conductivity type, formed on the surface layer of the drift region and arranged at intervals with the body region; An auxiliary depletion region of a second conductivity type, formed on the surface layer of the drift region between the body region and the drain region; A gate structure, spanning over the source region and the drift region; A body gate structure, including a plurality of body trench gates distributed within the auxiliary depletion region and lead-out structures of the body trench gates; the body trench gates include trenches located in the auxiliary depletion region, in-slot dielectric layers located on the sidewalls of the trenches, and conductive dielectrics filled within the in-slot dielectric layers, and the depth of the trenches is less than the depth of the auxiliary depletion region.

2. The bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: The plurality of body trench gates are arranged at intervals in a first direction to form a plurality of body trench gate columns, and are arranged at intervals in a second direction to form a plurality of body trench gate rows. The first direction is the direction from the source region towards the drain region, and the second direction intersects with the first direction. Among them, each body trench gate row is led out by a gate line, and any one of the gate lines is led out to an independent control terminal, or a plurality of the gate lines are led out to a common control terminal.

3. The bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The body trench gates between any two adjacent body trench gate columns are arranged in a staggered manner in the second direction.

4. The bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: When the field effect transistor conducts forward, the body trench gates are applied with a first voltage having the same polarity as the gate structure to reduce the on-resistance of the field effect transistor. When the field effect transistor is turned off, the body trench gates are applied with a second voltage having a polarity opposite to that of the first voltage to increase the reverse breakdown voltage of the field effect transistor.

5. The bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: The depth range of the auxiliary depletion region is 2 micrometers to 4 micrometers, the width of the body trench gates is 1 micrometer to 2 micrometers, and the spacing between two adjacent body trench gates is 2 micrometers to 3 micrometers.

6. The bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: An insulating layer is further formed on the body gate structure, through holes exposing the body trench gates are formed in the insulating layer, and lead-out structures of the body trench gates are formed on the through holes and the insulating layer.

7. A manufacturing method of a bulk-gate laterally double-diffused metal oxide semiconductor field effect transistor, characterized in that, Including the steps of: Providing a substrate, and forming a drift region of a first conductivity type on the substrate; Forming an auxiliary depletion region of a second conductivity type on the surface layer of the drift region; Forming a plurality of body trench gates in the auxiliary depletion region; Forming a body region of a second conductivity type in the drift region; Forming a source region of a first conductivity type and a body lead-out region of a second conductivity type on the surface layer of the body region, and forming a drain region of a first conductivity type on the surface layer of the drift region, wherein the auxiliary depletion region is located between the drain region and the body region; Forming a gate structure between the source region and the drift region; Forming a lead-out structure on the body trench gates; Forming a plurality of body trench gates in the auxiliary depletion region includes: Etching a plurality of trenches in the auxiliary depletion region through a photolithography process and an etching process, and the depth of the trenches is less than the depth of the auxiliary depletion region; Forming in-slot dielectric layers on the sidewalls of the trenches through a thermal oxidation process; Filling conductive dielectrics within the in-slot dielectric layers through a deposition process.

8. The manufacturing method of the bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 7, wherein: A plurality of body trench gates formed in the auxiliary depletion region are arranged at intervals along a first direction to form a plurality of body trench gate columns, and are arranged at intervals along a second direction to form a plurality of body trench gate rows. The first direction is the direction from the source region towards the drain region, and the second direction intersects with the first direction. Among them, the body trench gates between any two adjacent body trench gate columns are arranged in a staggered manner in the second direction.

9. The manufacturing method of the bulk-gate laterally-diffused metal oxide semiconductor field effect transistor according to claim 8, wherein: The drift region is formed by an ion implantation process and a high-temperature push-junction process.

10. The manufacturing method of the bulk-gate laterally diffused metal oxide semiconductor field effect transistor according to claim 8, wherein: The depth range of the auxiliary depletion region is 2 micrometers to 4 micrometers, the width of the body trench gate is 1 micrometer to 2 micrometers, and the spacing between two adjacent body trench gates is 2 micrometers to 3 micrometers.

11. The manufacturing method of the bulk-gate laterally-diffused metal oxide semiconductor field effect transistor according to claim 8, wherein Forming a lead-out structure on the body trench gate includes the steps of: Forming an insulating layer on the surface of the drift region; Forming a through hole exposing the body trench gate in the insulating layer, and forming a lead-out structure of the body trench gate based on the through hole; Forming a lead-out structure of the body trench gate based on the through hole includes a plurality of gate lines. Each body trench gate row is led out by a gate line, and any one of the gate lines is led out to an independent control terminal, or a plurality of the gate lines are led out to a common control terminal.

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