An adaptive charge pump circuit

Abstract

The application relates to a self-adaptive charge pump circuit, which comprises a voltage-boosting switch group circuit, a current sampling circuit connected with the voltage-boosting switch group circuit, an under-voltage judging circuit, the current sampling circuit and the under-voltage judging circuit are connected with a logic circuit, the logic circuit is connected with a current-limiting circuit, the current-limiting circuit is connected with the voltage-boosting switch group circuit, the voltage-boosting switch group circuit is externally connected with a flying capacitor, and the voltage-boosting switch group circuit and the under-voltage judging circuit are connected with an output capacitor. The application can reduce the overshoot current during the charge pump mode switching, effectively solves the problem of the excessively large charging current peak value in the fast charging process, and is beneficial to improving the service life of the battery.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of charge pump, more particularly to an adaptive charge pump circuit for powering an audio amplifier. BACKGROUND

[0002] Charge pump circuit is a commonly used power management circuit, which can realize the function of voltage boosting compared with linear voltage regulator, and has high efficiency and load current. Compared with switching power management circuit, charge pump circuit has small output voltage ripple, and can not use inductor, which has certain advantages. In the starting process of the conventional power management circuit, soft start circuit is often used, for example, by slowly increasing the reference voltage or current limiting method, the charging speed of the output capacitor is controlled to avoid the output current out of control and cause voltage or thermal damage to the chip.

[0003] For the charge pump circuit for powering the audio amplifier, the output power supply needs to be able to switch quickly with the input signal to avoid the voltage peak clipping distortion caused by the power supply failing to follow the input signal. Fast switching requires fast current injection, and while ensuring sufficient power input, the current and power for charging the output capacitor need to be controlled so that the power of each switch is not too large to avoid large current glitches on the parasitic inductance, which will damage the chip when the voltage peak exceeds the voltage withstanding of the device.

[0004] However, the existing charge pump circuit is difficult to realize the fast switching of the output power supply with the input signal while ensuring that the current peak value during charging of the output capacitor is not too large. SUMMARY

[0005] To solve the above problems in the prior art, the present application provides an adaptive charge pump circuit, which can effectively solve the problem of excessive charging current peak value in the fast charging process by limiting the current on the output capacitor through a current mirror.

[0006] The adaptive charge pump circuit provided by the present application comprises a boost switch group circuit, a current sampling circuit and an under-voltage judgment circuit connected with the boost switch group circuit, the current sampling circuit and the under-voltage judgment circuit are connected with a logic circuit, the logic circuit is connected with a current limiting circuit, the current limiting circuit is connected with the boost switch group circuit, the boost switch group circuit is connected with a flying capacitor, and the boost switch group circuit and the under-voltage judgment circuit are connected with an output capacitor.

[0007] Further, the boost switch group circuit comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube connected with each other, a source electrode of the first switch tube is connected with a power supply voltage, a drain electrode is connected with a CP end of the flying capacitor, and a gate electrode inputs a first switch signal; a source electrode of the second switch tube is connected with the CP end, a drain electrode is connected with one end of an output capacitor, the other end of the output capacitor is grounded, and a gate electrode inputs a second switch signal; a source electrode of the third switch tube is connected with the power supply voltage, a drain electrode is connected with a CN end of the flying capacitor, and a gate electrode inputs a third switch signal; and a drain electrode of the fourth switch tube is connected with the CN end, a source electrode is grounded, and a gate electrode inputs a fourth switch signal.

[0008] Further, the current sampling circuit comprises a first power switch tube, a gate electrode of the first power switch tube inputs the fourth switch signal, a drain electrode is connected with the CN end and a reverse input end of a first operational amplifier, and a source electrode is connected with a source electrode of the fourth switch tube; a positive input end of the first operational amplifier is connected with a drain electrode of the fourth switch tube, and output ends are connected with gate electrodes of a first transistor and a second transistor; a drain electrode of the first transistor is connected with the positive input end of the first operational amplifier, and a source electrode is connected with a source electrode of the second transistor; a drain electrode of the second transistor is connected with a drain electrode of a third transistor and a gate electrode of a fourth transistor, and a source electrode is connected with a power supply; a gate electrode and a drain electrode of the third transistor are short-circuited, and a source electrode is grounded; a gate electrode of the fourth transistor is connected with the gate electrode of the third transistor, a source electrode is grounded, and a drain electrode is connected with a drain electrode of a fifth transistor; a source electrode of the fifth transistor is connected with the power supply voltage, a drain electrode and a gate electrode are short-circuited, and the gate electrode is connected with a gate electrode of a sixth transistor; a source electrode of the sixth transistor is connected with the power supply voltage, a drain electrode is connected with a reverse input end of a first comparator and one end of a first resistor respectively, and the other end of the first resistor is grounded; a positive input end of the first comparator is connected with a preset reference voltage, and an output end is connected with a first inverter.

[0009] Further, the current sampling circuit further comprises a second power switch tube, a gate electrode of the second power switch tube inputs the third switch signal, a drain electrode is connected with a reverse input end of a second operational amplifier, and a source electrode is connected with a source electrode of the third switch tube; a drain electrode of the third switch tube is connected with a positive input end of the second operational amplifier OP2, and output ends of the second operational amplifier are connected with gate electrodes of a seventh transistor and an eighth transistor respectively; a drain electrode of the seventh transistor is connected with the positive input end of the second operational amplifier and the drain electrode of the third switch tube respectively, and a source electrode is grounded; a drain electrode of the eighth transistor is connected with the drain electrode of the fourth transistor, and a source electrode is grounded.

[0010] Further, the under-voltage judging circuit comprises a second comparator, a positive input terminal of the second comparator is connected to the power supply voltage, and a negative input terminal of the second comparator is connected to a second resistor and a third resistor in parallel connection, the third resistor R3 is grounded.

[0011] Further, the logic circuit comprises a current-limiting signal control circuit and a switch signal control circuit.

[0012] Further, the over-current signal control circuit comprises an NOR gate and a second inverter connected to each other.

[0013] Further, the switch signal control circuit comprises an oscillator, an input terminal of a third inverter is connected to the oscillator, an input terminal of the third inverter is connected to a first input terminal of a first NAND gate, and a first input terminal of a second NAND gate is connected to the oscillator; an output terminal of the first NAND gate is connected to an input terminal of a fourth inverter, an output terminal of the fourth inverter is connected to an input terminal of a fifth inverter, an output terminal of the fifth inverter is connected to a second input terminal of the second NAND gate, an input terminal of a sixth inverter is connected to an output terminal of the second NAND gate, an input terminal of a seventh inverter is connected to an output terminal of the sixth inverter, and an output terminal of the seventh inverter is connected to a second input terminal of the first NAND gate; and the fourth inverter is connected to an eighth inverter, the eighth inverter is connected to a ninth inverter and a tenth inverter, and the sixth inverter is connected to an eleventh inverter and a twelfth inverter.

[0014] Further, the current-limiting circuit comprises a first current mirror composed of the third switch tube and a ninth transistor, and a second current mirror composed of the fourth switch tube and a tenth transistor.

[0015] Further, a gate of the third switch tube is connected to a gate of the ninth transistor; a source of the ninth transistor is connected to the power supply voltage, a gate and a drain of the ninth transistor are short-circuited and input the third switch signal, and a drain of the ninth transistor is connected to a source of an eleventh transistor; a gate of the eleventh transistor inputs the reverse over-current signal, a drain of the eleventh transistor is connected to an input terminal of a first current source, and an output terminal of the first current source is grounded; a gate of the fourth switch tube is connected to a gate of the tenth transistor, and a source of the fourth switch tube is grounded; a source of the tenth transistor is grounded, a gate and a drain of the tenth transistor are short-circuited and input the fourth switch signal, and a drain of the tenth transistor is connected to a source of a twelfth transistor; a gate of the twelfth transistor inputs the over-current signal, a drain of the twelfth transistor is connected to an output terminal of a second current source, and an input terminal of the second current source is connected to a source of the third switch tube.

[0016] This invention achieves the switching of charge pump mode through boost switch circuit and logic circuit, and controls the current limiting circuit through current sampling circuit and undervoltage judgment circuit, thereby reducing the overshoot current when switching charge pump mode. This effectively solves the problem of excessive charging current peak during fast charging and helps to improve battery life. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the adaptive charge pump circuit according to the present invention.

[0018] Figure 2 yes Figure 1 A schematic diagram of the medium-voltage boost switch circuit and the phase of the switching signal.

[0019] Figure 3 yes Figure 1 A schematic diagram of a medium current sampling circuit.

[0020] Figure 4 yes Figure 1 A schematic diagram of the undervoltage detection circuit.

[0021] Figure 5(a) is Figure 1 A schematic diagram of the current limiting signal control circuit of the logic circuit; Figure 5(b) is Figure 1 A schematic diagram of the switching signal control circuit of the logic circuit.

[0022] Figure 6 yes Figure 1 A schematic diagram of a current-limiting circuit.

[0023] Figure 7 This is a waveform diagram of the adaptive charge pump circuit operating according to the present invention. Detailed Implementation

[0024] The preferred embodiments of the present invention are given below with reference to the accompanying drawings and described in detail.

[0025] like Figure 1 As shown, the present invention provides an adaptive charge pump circuit, including a boost switch group circuit 1, a current sampling circuit 2, and an undervoltage judgment circuit 3 connected to the boost switch group circuit 1. Both the current sampling circuit 2 and the undervoltage judgment circuit 3 are connected to a logic circuit 4, which is connected to a current limiting circuit 5. The current limiting circuit 5 is also connected to the boost switch group circuit 1. Furthermore, the boost switch group circuit 1 is externally connected to a flying capacitor Cfly for rapid voltage rise and fall, and both the boost switch group circuit 1 and the undervoltage judgment circuit 3 are connected to an output capacitor Cout.

[0026] The current sampling circuit 2 samples the current Isense generated by the boost switch group circuit 1, converts the sampled current into a voltage, compares the voltage with a preset reference voltage Vref1, and outputs an inverse overcurrent signal OCZ through an inverter. The under-voltage judgment circuit 3 samples the output voltage PVDD generated by the boost switch group circuit 1, compares the sampled voltage with the power supply voltage VDD, and outputs a low voltage signal UV. The inverse overcurrent signal OCZ and the low voltage signal UV are input into the logic circuit 4, which converts them into a current limiting signal CL and an inverse current limiting signal CLZ. The current limiting signal CL and the inverse current limiting signal CLZ are input into the current limiting circuit 5, and at the same time, the first switch signal S1, the second switch signal S2, the third switch signal S3, and the fourth switch signal S4 generated by the logic circuit 4 are input into the boost switch group circuit 1. The current limiting circuit 5 outputs a control current Ilimit to the boost switch group circuit 1 to control the current flowing through the flying capacitor Cfly in the boost switch group circuit 1.

[0027] The above-mentioned circuit modules will be described in detail below.

[0028] As shown in Figure 2 , the boost switch group circuit 1 includes a first switch tube MP1, a second switch tube MP2, a third switch tube MP3, and a fourth switch tube MN4 connected to each other. Specifically, the source of the first switch tube MP1 is connected to the power supply voltage VDD, the drain is connected to the CP end of the flying capacitor Cfly, and the gate is input with the first switch signal S1; the source of the second switch tube MP2 is connected to the CP end of the flying capacitor Cfly, the drain is connected to one end of the output capacitor Cout, the other end of the output capacitor Cout is grounded, and the gate of the second switch tube MP2 is input with the second switch signal S2; the source of the third switch tube MP3 is connected to the power supply voltage VDD, the drain is connected to the CN end of the flying capacitor Cfly, and the gate is input with the third switch signal S3; the drain of the fourth switch tube MN4 is connected to the CN end of the flying capacitor Cfly, the source is grounded, and the gate is input with the fourth switch signal S4. The boost switch group circuit 1 generates an output voltage PVDD, which is used to power the output capacitor Cout.

[0029] As shown in Figure 3As shown, the current sampling circuit 2 includes a first power switch MNN4 and a second power switch MPP3. The aforementioned current Isense is the current flowing through MNN4 and MPP3. The gate of the first power switch MNN4 receives the fourth switching signal S4. Its drain is connected to the CN terminal of the flying capacitor Cfly and then to the inverting input of the first operational amplifier OP1. Its source is connected to the source of the fourth switch MN4 in the boost switching circuit 1. The non-inverting input of the first operational amplifier OP1 is connected to the drain of the fourth switch MN4, and its output is connected to the gate of the first transistor MP5 and the gate of the second transistor MP6. The drain of the first transistor MP5 is connected to the non-inverting input of the first operational amplifier OP1, and its source is connected to the source of the second transistor MP6. The drain of the second transistor MP6 is connected to the drain of the third transistor MN9 and the gate of the fourth transistor MN10. The source of the second transistor MP6 is connected to the power supply voltage VDD. The gate and drain of the third transistor MP9 are shorted, and its source is grounded. The gate of the fourth transistor MN10 is connected to the gate of the third transistor MP9, its source is grounded, and its drain is connected to the drain of the fifth transistor MP11. The source of the fifth transistor MP11 is connected to the power supply voltage VDD, its drain and gate are shorted, and its gate is connected to the gate of the sixth transistor MP12. The source of the sixth transistor MP12 is connected to the power supply voltage VDD, and its drain is connected to the inverting input of the first comparator Comp1 and one end of the first resistor R1, the other end of which is grounded. The non-inverting input of the first comparator Comp1 is connected to a preset reference voltage Vref1, and its output is connected to the first inverter Inv1. The first comparator Comp1 outputs an overcurrent signal OC, which is then inverted by Inv2 to output its reverse overcurrent signal OCZ.

[0030] The gate of the second power switch MPP3 receives the third switching signal S3, its drain is connected to the inverting input of the second operational amplifier OP2, and its source is connected to the source of the third switch MP3 in the voltage switching circuit 1. The drain of the third switch MP3 is connected to the non-inverting input of the second operational amplifier OP2. The output of the second operational amplifier OP2 is connected to the gates of the seventh transistor MN7 and the eighth transistor MN8. The drain of the seventh transistor MN7 is connected to both the non-inverting input of the second operational amplifier OP2 and the drain of the third switch MP3, and its source is grounded. The drain of the eighth transistor MN8 is connected to the drain of the aforementioned fourth transistor MN10, and its source is grounded.

[0031] like Figure 4As shown, the under-voltage judging circuit 3 includes a second comparator Comp2, the positive input terminal of the second comparator Comp2 is connected to the power supply voltage VDD, the negative input terminal is connected to the second resistor R2 and the third resistor R3 in parallel, the third resistor R3 is grounded. The output voltage PVDD is input to the negative input terminal of the second comparator Comp2 after being divided by the second resistor R2 and the third resistor R3, and the lowest voltage signal UV is output.

[0032] The logic circuit 4 includes a current-limiting signal control circuit 41 and a switching signal control circuit 42. As shown in Fig. 5(a), the current-limiting signal control circuit includes an OR gate OR1 and a second inverter Inv2 connected to each other. The two input terminals of the OR gate OR1 input the reverse over-current signal OCZ and the low voltage signal UV, and the output terminal outputs the reverse current-limiting signal CLZ, which is output as the current-limiting signal CL after passing through the second inverter Inv2.

[0033] As shown in Fig. 5(b), the switching signal control circuit 42 includes an oscillator OSC, the clock signal generated by the oscillator OSC is input to the first input terminal of the first NAND gate nand1, and the clock signal is input to the first input terminal of the second NAND gate nand2. The output terminal of the first NAND gate nand1 is connected to the input terminal of the fourth inverter inv4, the output terminal of the fourth inverter inv4 is connected to the input terminal of the fifth inverter inv5, and the output terminal of the fifth inverter inv5 is connected to the second input terminal of the second NAND gate nand2. The output terminal of the second NAND gate nand2 is connected to the input terminal of the sixth inverter inv6, the output terminal of the sixth inverter inv6 is connected to the input terminal of the seventh inverter inv7, and the output terminal of the seventh inverter inv7 is connected to the second input terminal of the first NAND gate nand1. Among them, the fourth inverter inv4 outputs the first phase signal phase1, the first phase signal phase1 is input to the input terminal of the ninth inverter inv9 through the eighth inverter inv8, and the ninth inverter inv9 outputs the first switching signal S1; and the first phase signal phase1 is input to the input terminal of the tenth inverter inv10 through the eighth inverter inv8, and the tenth inverter inv10 outputs the fourth switching signal S4. The sixth inverter inv6 outputs the second phase signal phase2, the second phase signal phase2 is output as the second switching signal S2 through the eleventh inverter inv11, and is output as the third switching signal S3 through the twelfth inverter inv12.

[0034] As Figure 6As shown, the current limiting current 5 includes a first current mirror composed of the third switch tube MP3 and the ninth transistor MCLP of the boost switch group circuit 1, and a second current mirror composed of the fourth switch tube MN4 and the tenth transistor MCLN of the boost switch group circuit 1. The gate of the third switch tube MP3 is connected to the gate of the ninth transistor MCLP. The source of the ninth transistor MCLP is connected to the power supply voltage VDD, the gate and the drain are shorted and input the third switch signal S3, and the drain is also connected to the source of the eleventh transistor MP13. The gate of the eleventh transistor MP13 inputs the reverse overcurrent signal CLZ, the drain is connected to the input of the first current source ICLP, and the output of the first current source ICLP is grounded. The gate of the fourth switch tube MN4 is connected to the gate of the tenth transistor MCLN, and the source is grounded. The source of the tenth transistor MCLN is grounded, the gate and the drain are shorted and input the fourth switch signal S4, and the drain is also connected to the source of the twelfth transistor MN14. The gate of the twelfth transistor MN14 inputs the overcurrent signal CL, the drain is connected to the output of the second current source ICLN, and the input of the second current source ICLN is connected to the source of the third switch tube MP3.

[0035] For better understanding, the following will be combined with Figures 1-6 The working principle of the adaptive charge pump circuit of the present application is described.

[0036] When the charge pump is in 1 times mode, the first switch signal S1 input to the gate of the first switch tube MP1, the second switch signal S2 input to the gate of the second switch tube MP2, and the fourth switch signal S4 input to the gate of the fourth switch tube MN4 are connected to low potential, and the third switch signal S3 input to the gate of the third switch tube MP3 is connected to high potential. At this time, the first switch tube MP1 and the second switch tube MP2 are both turned on, and the power supply voltage is connected to PVDD, so the voltage value of the output voltage PVDD is VDD.

[0037] When the charge pump is in 2 times mode, the switch tube has two switch phases: charging phase ph1 (i.e. the first phase signal phase1 described above) and discharging phase ph2 (i.e. the second phase signal phase2 described above). When in the charging phase ph1, the first switch signal S1 input to the gate of the first switch tube MP1 is at low potential, the second switch signal S2 input to the gate of the second switch tube MP2, the third switch signal S3 input to the gate of the third switch tube MP3 and the fourth switch signal S4 input to the gate of the fourth switch tube MN4 are at high potential, the power supply voltage VDD charges the flying capacitor Cfly through the first switch tube MP1 and the fourth switch tube MN4, and at this time the output capacitor Cout discharges the load. When in the discharging phase ph2, the first switch signal S1 input to the gate of the first switch tube MP1 is at high potential, the second switch signal S2 input to the gate of the second switch tube MP2, the third switch signal S3 input to the gate of the third switch tube MP3 and the fourth switch signal S4 input to the gate of the fourth switch tube MN4 are at low potential, and at this time the flying capacitor Cfly supplies power to the load and the output capacitor Cout simultaneously.

[0038] In 1 times mode, the voltage of the flying capacitor Cfly and the voltage of the output capacitor Cout are both equal to VDD. When switching from 1 times mode to 2 times mode, the charge pump is in the discharging phase ph2, the second switch tube MP2 and the third switch tube MP3 are open, and since the voltage of the flying capacitor Cfly does not change abruptly, the voltage at the CN end of the output capacitor Cout is 0, at this time the Vds (drain-source voltage) of the third switch tube MP3 is VDD and the Vgs (gate-source voltage) is VDD. According to the transfer characteristic curve of the MOS tube, at this time the Id (drain current) of the third switch tube MP3 is very large, and the current in this working state needs to be limited to prevent damage to the device.

[0039] When the charge pump is in the ph1 state of 2 times mode, the fourth switch signal S4 is at high potential, the fourth switch tube MN4 and the first power switch tube MNN4 are turned on, the power tube current information is sampled to the sixth transistor MP12 through the first operational amplifier OP1 and a certain proportion of the current mirror, converted into voltage on the first resistor R1 and input to the reverse input end of the first comparator Comp1. When the sampled current is greater than a certain threshold value, the voltage at the positive end of the first resistor R1 is greater than the reference voltage Vref1, at this time the reverse overcurrent signal OCZ output by the first comparator Comp1 is low, and the current limiting signal CL output by the logic circuit 4 is high.

[0040] When the charge pump is in the ph2 state of 2 times mode, the third switch signal S3 is low, the third switch tube MP3 and the first power switch tube MPP3 are turned on, the power tube current information is sampled to the sixth transistor MP12 through the second operational amplifier OP2 and a certain proportion of the current mirror, is converted into voltage on the first resistor R1 and is input to the reverse input end of the first comparator Comp1. When the sampled current is greater than a certain threshold, the voltage at the positive end of the first resistor R1 is greater than the reference voltage Vref1, at this time, the reverse overcurrent signal OCZ output by the first comparator Comp1 is low, and the current limiting signal CL output by the logic circuit 4 is high.

[0041] When the charge pump is in 2 times mode, if the output voltage PVDD is lower than 1.5 times of VDD, UV is high, at this time, no matter whether the reverse overcurrent signal OCZ is high or low, the output CL of the logic circuit 4 is high; if PVDD is greater than 1.5 times of VDD, UV is low, at this time, when OCZ is low, CL is high, and when OCZ is high, CL is low.

[0042] When CL is high, CLZ is low, the twelfth transistor MN14 and the eleventh transistor MP13 are turned on. Since the third switch tube MP3 and the ninth transistor MCLP constitute the first current mirror, the fourth switch tube MN4 and the tenth transistor MCLN constitute the first current mirror, therefore the currents of the switch tubes MN4 and MP3 are respectively affected by the limiting currents flowing through the transistors MN14 and MP13, and the current sources ICLN and ICLP are used to replace the limiting currents.

[0043] Figure 7 The waveform diagram of the charge pump circuit of the application is shown in the figure, when the charge pump is switched from 1 times mode to 2 times mode, in the initial charging period, when the PVDD voltage sampled by the under-voltage judgment circuit 3 is less than VDD, UV is high, the CL output by the logic circuit 4 is high, the current limiting circuit 5 limits the current at the end of the flying capacitor Cfly and the capacitor CN, the charge pump does not need to wait for the sampling result of the overcurrent sampling, and is directly in the current limiting working state. When the PVDD voltage sampled by the under-voltage judgment circuit 3 is greater than 1.5 times of VDD, UV is low, the current sampling circuit 2 and the under-voltage judgment circuit 3 detect that the current exceeds the overcurrent threshold, OCZ is low, at this time, the CL output by the logic is high, and the charge pump is in the current limiting working state. If PVDD is higher than 1.5 times of VDD and the output load is small, CL is low, the charge pump works normally, the gate voltage of MP3 can be as low as 0, and the gate voltage of MN4 can be as high as VDD.

[0044] The application can transform the working mode according to the size of the audio input signal: when the amplitude of the input audio signal is small, the required output power is small, a high output voltage is not needed, the output and input voltages of the charge pump are equal, and the switch group of the charge pump is configured in 1 times mode. When the amplitude of the input audio signal is large, the required output power is large, the output of the charge pump is twice the input voltage, and the switch group of the charge pump is configured in 2 times mode. In this way, the voltage can be fully utilized in the entire input signal range, and the balance between the output power dynamic range and the efficiency is achieved.

[0045] The above description is only the preferred embodiment of the application, and is not intended to limit the scope of the application. The above embodiment of the application can be variously changed. Any simple, equivalent changes and modifications made according to the content of the application claims and the description fall within the scope of the application. The application is not described in detail, and is of conventional technical content.

Claims

1. An adaptive charge pump circuit, characterized in that, The device includes a boost switch group circuit, a current sampling circuit and an undervoltage judgment circuit connected to the boost switch group circuit. The current sampling circuit and the undervoltage judgment circuit are both connected to a logic circuit. The logic circuit is connected to a current limiting circuit. The current limiting circuit is connected to the boost switch group circuit. The boost switch group circuit is externally connected to a flying capacitor. Both the boost switch group circuit and the undervoltage judgment circuit are connected to an output capacitor. The boost switching circuit includes a first switch, a second switch, a third switch, and a fourth switch connected to each other. The source of the first switch is connected to the power supply voltage, the drain is connected to the CP terminal of the flying capacitor, and the gate receives a first switching signal. The source of the second switch is connected to the CP terminal, the drain is connected to one end of the output capacitor, the other end of the output capacitor is grounded, and the gate receives a second switching signal. The source of the third switch is connected to the power supply voltage, the drain is connected to the CN terminal of the flying capacitor, and the gate receives a third switching signal. The drain of the fourth switch is connected to the CN terminal, the source is grounded, and the gate receives a fourth switching signal. The current sampling circuit includes a first power switch transistor. The gate of the first power switch transistor receives the fourth switching signal, its drain is connected to the CN terminal and then to the inverting input terminal of the first operational amplifier, and its source is connected to the source of the fourth switch transistor. The non-inverting input terminal of the first operational amplifier is connected to the drain of the fourth switch transistor, and its output terminal is connected to the gate of the first transistor and the gate of the second transistor. The drain of the first transistor is connected to the non-inverting input terminal of the first operational amplifier, and its source is connected to the source of the second transistor. The drain of the second transistor is connected to the drain of the third transistor and the gate of the fourth transistor. The source of the second transistor is connected to the power supply; the gate and drain of the third transistor are shorted, and the source is grounded; the gate of the fourth transistor is connected to the gate of the third transistor, the source is grounded, and the drain is connected to the drain of the fifth transistor; the source of the fifth transistor is connected to the power supply voltage, the drain and gate are shorted, and the gate is connected to the gate of the sixth transistor; the source of the sixth transistor is connected to the power supply voltage, and the drain is connected to the inverting input of the first comparator and one end of the first resistor, the other end of the first resistor is grounded; the non-inverting input of the first comparator is connected to a preset reference voltage, and the output is connected to the first inverter.

2. The adaptive charge pump circuit according to claim 1, characterized in that, The current sampling circuit further includes a second power switch, the gate of which receives the third switching signal, the drain of which is connected to the inverting input of the second operational amplifier, and the source of which is connected to the source of the third switch; the drain of the third switch is connected to the non-inverting input of the second operational amplifier OP2, the output of the second operational amplifier is connected to the gate of the seventh transistor and the gate of the eighth transistor respectively; the drain of the seventh transistor is connected to the non-inverting input of the second operational amplifier and the drain of the third switch respectively, and the source of the seventh transistor is grounded; the drain of the eighth transistor is connected to the drain of the fourth transistor, and the source is grounded.

3. The adaptive charge pump circuit according to claim 1, characterized in that, The undervoltage detection circuit includes a second comparator. The positive input terminal of the second comparator is connected to the power supply voltage, and the negative input terminal is connected to a second resistor and a third resistor in parallel. The third resistor R3 is grounded.

4. The adaptive charge pump circuit according to claim 1, characterized in that, The logic circuit includes a current limiting signal control circuit and a switching signal control circuit.

5. The adaptive charge pump circuit according to claim 4, characterized in that, The current limiting signal control circuit includes an NOR gate and a second inverter connected to each other.

6. The adaptive charge pump circuit according to claim 4, characterized in that, The switching signal control circuit includes an oscillator connected to the input of a third inverter, the input of which is connected to the first input of a first NAND gate, and the oscillator is also connected to the first input of a second NAND gate. The output of the first NAND gate is connected to the input of a fourth inverter, the output of the fourth inverter is connected to the input of a fifth inverter, the output of the fifth inverter is connected to the second input of the second NAND gate, the output of the second NAND gate is connected to the input of a sixth inverter, the output of the sixth inverter is connected to the input of a seventh inverter, and the output of the seventh inverter is connected to the second input of the first NAND gate. Furthermore, the fourth inverter is connected to an eighth inverter, the eighth inverter is connected to a ninth and tenth inverter, and the sixth inverter is connected to an eleventh and twelfth inverter.

7. The adaptive charge pump circuit according to claim 1, characterized in that, The current limiting circuit includes a first current mirror composed of the third switch and the ninth transistor, and a second current mirror composed of the fourth switch and the tenth transistor.

8. The adaptive charge pump circuit according to claim 7, characterized in that, The gate of the third switch is connected to the gate of the ninth transistor; the source of the ninth transistor is connected to the power supply voltage, its gate and drain are shorted and input with the third switch signal, and its drain is connected to the source of the eleventh transistor; the gate of the eleventh transistor inputs a reverse overcurrent signal, its drain is connected to the input terminal of the first current source, and the output terminal of the first current source is grounded; the gate of the fourth switch is connected to the gate of the tenth transistor, and its source is grounded; the source of the tenth transistor is grounded, its gate and drain are shorted and input with the fourth switch signal, and its drain is connected to the source of the twelfth transistor; The gate of the twelfth transistor receives an overcurrent signal, and its drain is connected to the output of the second current source. The input of the second current source is connected to the source of the third switching transistor.

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