Power supply and method with integrated voltage regulator and current limiter

Abstract

The present invention relates to power supplies and methods having an integrated voltage regulator and current limiter, and discloses a power supply that automatically switches between a voltage regulation mode and an overcurrent protection mode as needed. The power supply includes a voltage regulator that generates a first control voltage for application to a control terminal of a pass transistor during the voltage regulation mode to maintain an output voltage at a desired voltage level. The power supply includes a current limiter that generates a second control voltage for application to the control terminal of the pass transistor during the overcurrent protection mode to prevent the output current from rising above a maximum output current limit. The power supply includes additional circuitry for detecting when overcurrent protection is needed and automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage as needed, and vice versa. A related method of supplying power is also disclosed in the present invention.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to power supplies, and more particularly, to power supplies having integrated voltage regulators and current limiters and related methods. BACKGROUND

[0002] A power supply is a device that supplies power to an electrical load, and a voltage regulated power supply automatically maintains the output voltage at a desired voltage level as long as the maximum output current limit is not exceeded. A current limiter (also referred to herein as a current limiting circuit or an over current protection circuit) can be employed to avoid exceeding the maximum output current limit. Typically, such current limiters are configured to create a copy of the actual output current, compare the copied current to a reference current, and then limit the output current based on the difference between the copied current and the reference current. Unfortunately, current limiters having such a configuration are not ideal because, for example, as the load current increases, they tend to exhibit higher quiescent current and higher losses, and they often require fast loop correction to produce the copied current. SUMMARY

[0003] An embodiment of a power supply configured to automatically switch between a voltage regulation mode and an over current protection mode as needed can include an input voltage node and an output voltage node. A pass transistor can have an input connected to the input voltage node for receiving an input voltage, an output connected to the output voltage node for outputting an output voltage, and a control terminal. The power supply can also include a voltage regulator configured to generate and output a first control voltage for application to the control terminal of the pass transistor during the voltage regulation mode to maintain the output voltage at the output voltage node at a desired voltage level. The first control voltage can be variable and specifically generated based on the output voltage at the output voltage node. The power supply can also include a current limiter configured to generate and output a second control voltage for application to the control terminal of the pass transistor during the over current protection mode to prevent the output current from rising above a maximum output current limit of the pass transistor.

[0004] As needed, the power supply can also include additional circuitry for detecting when over-current protection is needed (e.g., due to an overload) and for automatically switching operation between the voltage regulation mode and the over-current protection mode (i.e., for automatically switching the control voltage applied to the control terminal of the pass transistor from the first control voltage to the second control voltage, and vice versa). More specifically, the power supply can also include a comparator configured to compare the first control voltage and the second control voltage and output a select signal having a logic value dependent on the difference between the first control voltage and the second control voltage. The power supply can also include a switching circuit configured to selectively and automatically apply either the first control voltage or the second control voltage to the control terminal of the pass transistor dependent on the logic value of the select signal. For example, the comparator can output a select signal having a first logic value indicating that over-current protection is not needed, in which case the switching circuit can apply the first control voltage from the voltage regulator to the control terminal of the pass transistor, either keeping the power supply in the voltage regulation mode or switching the power supply to the voltage regulation mode. Alternatively, the comparator can output a select signal having a second logic value indicating that over-current protection is needed, in which case the switching circuit can apply the second control voltage from the current limiter to the control terminal of the pass transistor, either keeping the power supply in the over-current protection mode or switching the power supply to the over-current protection mode.

[0005] As further discussed in the detailed description section below, optionally, the current limiter can also be configured to automatically regulate the second control voltage so that it is at a first voltage level during the voltage regulation mode and so that it is at a slightly different second voltage level during the over-current protection mode to prevent continuous oscillation between the two modes.

[0006] An embodiment of a power supply method is also disclosed in the present invention, the method can include supplying power to an electrical load through a pass transistor of a power supply. The pass transistor can have an input terminal connected to an input voltage node; an output terminal connected to an output voltage node; and a control terminal. The method can also include generating and outputting, by a voltage regulator of the power supply, a first control voltage for application to the control terminal of the pass transistor during a voltage regulation mode to maintain an output voltage at the output voltage node at a desired voltage level, the first control voltage can be variable and specifically generated based on the output voltage at the output voltage node. The method can also include generating and outputting, by a current limiter of the power supply, a second control voltage for application to the control terminal of the pass transistor during an over-current protection mode to prevent an output current from rising above a maximum output current limit of the pass transistor.

[0007] As desired, the method can also include detecting when overcurrent protection is needed (e.g., due to an overload) and automatically switching operation between the voltage regulation mode and the overcurrent protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage, and vice versa). More specifically, the method can include comparing the first control voltage and the second control voltage by a comparator of the power supply and outputting, by the comparator, a selection signal having a logic value dependent on the difference between the first control voltage and the second control voltage. The method can also include selectively and automatically applying, by a switching circuit of the power supply, either the first control voltage or the second control voltage to the control terminal of the pass transistor, dependent on the logic value of the selection signal. For example, if the selection signal has a first logic value indicating that overcurrent protection is not needed, the method can include applying the first control voltage from the voltage regulator to the control terminal of the pass transistor, or maintaining the power supply in the voltage regulation mode or switching the power supply to the voltage regulation mode. Alternatively, if the selection signal has a second logic value indicating that overcurrent protection is needed, the method can include applying the second control voltage from the current limiter to the control terminal of the pass transistor, maintaining the power supply in the overcurrent protection mode or switching the power supply to the overcurrent protection mode.

[0008] As further discussed below in the detailed description section, optionally, the method can include automatically regulating the second control voltage so that it is at a first voltage level during the voltage regulation mode and so that it is at a slightly different second voltage level during the overcurrent protection mode to prevent continuous oscillation between the two modes. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present application can be better understood with reference to the following detailed description together with the drawings, in which:

[0010] Figure 1 is a schematic diagram generally illustrating an embodiment of a power supply having both an integrated voltage regulator and an integrated current limiter as disclosed herein;

[0011] Figure 2 is a schematic diagram more specifically illustrating an exemplary embodiment of the disclosed power supply;

[0012] Figure 3 is a schematic diagram more specifically illustrating another exemplary embodiment of the disclosed power supply;

[0013] Figure 4 is a schematic diagram illustrating an exemplary reference voltage generation circuit for generating a second reference voltage (Vref2) used in the disclosed power supply;

[0014] Figure 5 and Figure 6 is a schematic diagram illustrating an exemplary switch that can be incorporated into the disclosed power supply; and

[0015] Figure 7 is a flowchart illustrating an embodiment of the disclosed power supply method. DETAILED DESCRIPTION

[0016] As noted above, a power supply is a device that supplies power to an electrical load, and a voltage regulating power supply automatically maintains the output voltage at a desired voltage level as long as the maximum output current limit is not exceeded. A current limiter (also referred to in this disclosure as a current limiting circuit or an over current protection circuit) can be employed to avoid exceeding the maximum output current limit. Typically, such current limiters are configured to create a copy of the actual output current, compare the copied current to a reference current, and then limit the output current based on the difference between the copied current and the reference current. Unfortunately, current limiters having this configuration are not ideal because, for example, as the load current increases, they tend to exhibit higher quiescent current and higher losses, and they often require fast loop correction to produce the copied current.

[0017] In view of the foregoing, an embodiment of a power supply having an integrated voltage regulator and an integrated current limiter is disclosed in this disclosure, and it is configured to automatically switch between a voltage regulation mode and an over current protection mode as needed. Specifically, the power supply includes a voltage regulator that generates a first control voltage for application to a control terminal of a pass transistor during the voltage regulation mode to maintain an output voltage at an output voltage node at a desired voltage level. The power supply also includes a current limiter that generates a second control voltage for application to the control terminal of the pass transistor during the over current protection mode to prevent the output current from rising above a maximum output current limit of the pass transistor. Finally, as needed, the power supply includes additional circuitry for detecting when over current protection is needed (e.g., due to an overload) and for automatically switching between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage, and vice versa). Related embodiments of a power supply method are also disclosed in this disclosure.

[0018] As Figure 1As shown, each of the disclosed embodiments of the power supply 100 can include an input voltage node 115; an output voltage node 116; and a pass transistor 110 connected between the input voltage node 115 and the output voltage node 116. Specifically, the pass transistor 110 can have an input terminal 111 connected to the input voltage node 115 for receiving a fixed input voltage (Vin); an output terminal 112 connected to the output voltage node 116 for outputting an output voltage (Vout); and a control terminal 113 for receiving a control voltage for controlling the current through the pass transistor 110.

[0019] The power supply 100 can also include a voltage regulator 120 that generates and outputs (i.e., is configured to generate and output) a first control voltage (Vc1) for application to the control terminal 113 of the pass transistor 110 during a voltage regulation mode, thereby controlling the current flow through the pass transistor 110 such that Vout at the output voltage node 116 is maintained at a desired voltage level, given a fixed Vin and based on the actual Vout at the output terminal 112, Vc1 can be generated by the voltage regulator 120. Vc1 can also be variable and continuously adjusted by the voltage regulator 120 as any changes in the actual Vout (e.g., as temperature-related changes in Vout), thereby continuously bringing the voltage level of Vout back to the desired voltage level. However, one skilled in the art will recognize that the voltage regulator 120 can not be able to maintain the desired output voltage for the pass transistor 110 when the output current (Iout) (also referred to in the present disclosure as the load current (Iload)) is above a maximum output current limit (Iout-max) (also referred to in the present disclosure as Iload-max). That is, if Iout-max is exceeded, Vc1 generated by the voltage regulator 120 can not be sufficient to maintain Vout at the desired voltage level.

[0020] Accordingly, the power supply 100 can also include a current limiter 130 that generates and outputs (i.e., is configured to generate and output) a second control voltage (Vc2) for application to the control terminal 113 of the pass transistor 110 during an over-current protection mode to prevent the output current (Iout) from rising above Iout-max, Vc2 can be generated and output by the current limiter 130 such that, for example, it is approximately equal to Vc1 generated by the voltage regulator 120 when Iout is just at but not exceeding Iout-max.

[0021] As needed, the power supply 100 can also include a means for detecting when over-current protection is needed (e.g., due to an overload) and for automatically switching between the voltage regulation mode and the over-current protection mode (i.e., for automatically switching the control voltage applied to the control terminal 113 of the pass transistor 110 from Vcl to Vc2, and vice versa). Specifically, the power supply 100 can also include a comparator 141 that compares (i.e., is configured or adapted to compare) Vcl to Vc2 and generates and outputs (i.e., is configured to generate and output) a select signal (SEL) having a logic value based on the difference between Vcl and Vc2. The power supply 100 can also include a switching circuit 140 that selectively and automatically applies (i.e., is configured to selectively and automatically apply) either Vcl or Vc2 to the control terminal 113 of the pass transistor 110 in dependence on the logic value of the SEL. For example, the comparator 141 can generate and output the SEL having a first logic value indicating that over-current protection is not needed, in which case the switching circuit 140 can apply Vcl from the voltage regulator 120 to the control terminal 113 of the pass transistor 110, either keeping the power supply 100 in the voltage regulation mode or switching the power supply 100 to the voltage regulation mode. Alternatively, the comparator 141 can generate and output the SEL having a second logic value indicating that over-current protection is needed, in which case the switching circuit 140 can apply Vc2 from the current limiter 130 to the control terminal 113 of the pass transistor 110, either keeping the power supply 100 in the over-current protection mode or switching the power supply 100 to the over-current protection mode.

[0022] Figure 2 and Figure 3 are schematic diagrams illustrating two exemplary embodiments of such power supplies 100A and 100B, respectively.

[0023] Referring to Figure 2 and Figure 3 , the power supplies 100A, 100B can include a pass transistor 110 for supplying power to an electrical load 125 (e.g., a variable electrical load), i.e., the power supplies 100A, 100B can include an input voltage node 115, an output voltage node 116 connected to the electrical load 125, and the pass transistor 110 connected between the input voltage node 115 and the output voltage node 116. The pass transistor 110 can have an input terminal 111 that receives a fixed input voltage (Vin). The pass transistor 110 can also have a control terminal 113 that receives a control voltage (Vc) (discussed below). The pass transistor 110 can also have an output terminal 112 that outputs an output voltage (Vout) having a voltage level that is dependent on both Vin and Vc.

[0024] The pass transistor 110 can be, for example, a p-type transistor. As shown, the p-type transistor can be a p-type field effect transistor (PFET), which can include a channel region between a source region (i.e., input terminal) and a drain region (i.e., output terminal) and a gate (i.e., control terminal) adjacent to the channel region. Alternatively, the p-type transistor can be a pnp bipolar junction transistor (pnp-BJT), which can include a base region (i.e., control terminal) between an emitter region (i.e., input terminal) and a collector region (i.e., output terminal). Alternatively, the pass transistor 110 can be any other suitable type of pass transistor.

[0025] The power supply 100A, 100B can also include a voltage regulator 120, which can be a low-dropout voltage regulator, and in particular, a DC linear voltage regulator that regulates (i.e., is configured to regulate) Vout at the output voltage node 116 even when the fixed Vin at the input voltage node 115 is very close to Vout. More specifically, the voltage regulator 120 generates (i.e., is configured to generate) a first control voltage (Vci) for automatically maintaining Vout at a desired voltage level during a voltage regulation mode as long as Vin is maintained fixed and does not exceed a maximum output current limit (Iout-max) of the pass transistor 110.

[0026] In some embodiments, the voltage regulator 120 can include a pair of resistors 121 and 122 connected in series between the output voltage node 116 and ground (Vss) 199 and an error amplifier 123 (also referred to in this disclosure as a differential amplifier), which can include an inverting input (-) that receives a first reference voltage (Vrefi), which can be a constant reference voltage (i.e., a temperature-independent reference voltage set at a predetermined voltage level). For example, Vrefi can be generated and received by a bandgap reference circuit, which is well known in the art and, therefore, details are omitted from this specification to allow the reader to focus on the salient aspects of the disclosed embodiments. The error amplifier 123 can also include a non-inverting input (+) connected to a feedback voltage node 126 at the interface between the pair of series resistors 121-122. Thus, the non-inverting input (+) can monitor a fraction of Vout (referred to in this disclosure as a feedback voltage (Vfb)) at the feedback voltage node 126, which can be determined by the resistance ratio of the two resistors 121-122 as follows:

[0027] Vout = Vfb * (1 + R1 / R2), (1)

[0028] where R1 is a first resistance value of the first resistor 121 and R2 is a second resistance value of the second resistor 122. The error amplifier 123 can also have an output and can generate and output (i.e., can be configured to generate and output) Vc1 at the output based on a difference between Vfb and Vref1. Specifically, the generated and output Vc1 is equal to the difference between Vref1 and Vfb multiplied by any gain. Moreover, it should be noted that as Vfb rises above Vref1, Vc1 will become increasingly positive until a positive saturation voltage is reached, and as Vfb falls below Vref1, Vc1 will become increasingly negative until a negative saturation voltage is reached. As noted above and discussed in more detail below, Vc1 can be selectively applied to the control terminal 113 of the pass transistor 110 during the voltage regulation mode to maintain Vout at the output voltage node 116 at a desired voltage level. However, as noted above, when Iout rises above Iout-max for the pass transistor 110, the voltage regulator 120 can be unable to maintain Vout at the desired voltage level, i.e., the Vc1 generated by the voltage regulator 120 can not be sufficient to maintain Vout at the desired voltage level.

[0029] Accordingly, the power supply 100A, 100B can also include a current limiter 130 that generates and outputs (i.e., is configured to generate and output) a second control voltage (Vc2) for application to the control terminal 113 of the pass transistor 110 during the over-current protection mode to prevent the output current (Iout) from rising above Iout-max, Vc2 can be generated and output by the current limiter 130 such that, for example, it is approximately equal to Vc1 generated by the voltage regulator 120 when Iout is just at but not exceeding Iout-max.

[0030] In some embodiments, the current limiter 130 can include at least an emulated transistor 160 and a feedback amplifier 131, as well as a reference current generation circuit (e.g., 150A or 150B, as discussed in more detail below).

[0031] The simulation transistor 160 can be a p-type simulation transistor and specifically can be an additional instance of the same transistor used for the pass transistor 110. Alternatively, the simulation transistor 160 can be a scaled down version of the pass transistor 110. For example, for a PFET pass transistor and simulation transistor, the PFET simulation transistor can have a channel length (L) and a channel width (W), while the PFET pass transistor can have the same channel length (L) but a channel width of (K*W). For purposes of illustration, since the pass transistor 110 is shown as a PFET, the simulation transistor 160 is similarly shown as a PFET. In any case, the simulation transistor 160 has an input end 161, an output end 162, and a control end 163, the input end 161 of the simulation transistor 160 can be connected to the voltage input node 115 so that it also receives the input voltage (Vin), and the output end 162 of the simulation transistor 160 can be connected to the simulation output voltage node 134.

[0032] A reference current (Iref) generation circuit can be connected between the simulation output voltage node 134 and ground, the Iref generation circuit can generate (i.e., can be configured to generate) a particular Iref across the simulation output voltage node 134, and thereby set the simulation output voltage (Vout-m) at the simulation output voltage node 134.

[0033] The feedback amplifier 131 can include a non-inverting (+) input connected to the simulation output voltage node 134. The feedback amplifier 131 can also include an inverting (-) input that receives a second reference voltage (Vref2), for example, which can be received from a reference voltage generation circuit configured to generate Vref2 based on Vrefl and such that it is independent of Vout but emulates the Vout of the pass transistor 110 at Iout-max. Figure 4is a schematic diagram illustrating an exemplary reference voltage generation circuit that can be used to generate Vref2 as described. Specifically, the reference voltage generation circuit can include an amplifier 401 having a pair of inputs and an output, a pair of reference resistors 411-412 can be connected in series between the output of the amplifier 401 and ground (Vss) 199 (e.g., a ground rail), the reference resistors 411-412 can be substantially identical to the resistors 121-122 used in the voltage regulator 120, while the first reference resistor 411 has a first resistance value (Rl) that is identical to the first resistor 121 and the second reference resistor 412 has a second resistance value (R2) that is identical to the second resistor 122. One input of the amplifier 401 can receive Vrefl, while the other input of the amplifier 401 can receive a reference feedback voltage (Vref-fb) from a reference feedback voltage node 415 at the junction between the two reference resistors 411-412. It should be noted that Vref-fb can be substantially identical to Vfb on the feedback voltage node 126 of the voltage regulator 120. Based on the difference between Vrefl and Vref-fb and further on any gain, the amplifier 401 can output Vref2. Given equation (1) above, given that the reference resistors 411-412 are identical to the resistors 121-122, given that Vref-fb is substantially identical to Vfb, and further given the following equation that defines Vref2, it should be understood that the relationship of Vout to Vrefl will be substantially identical to the relationship of Vref2 to Vrefl, and thus, Vref2 will be substantially identical to Vout but independent of Vout, as long as the maximum output current limit (Iout-max) of the pass transistor 110 is not exceeded.

[0034] Vref2 = Vref-fb * (1 + R1 / R2), (2)

[0035] Vref2 = Vrefl * (1 + R1 / R2), and (3)

[0036] Vref2 = Vout, when Iout < Iout-max. (4)

[0037] Referring again to Figure 2 and Figure 3, the feedback amplifier 131 of the current limiter 130 can also have an output and can generate and output (i.e., can be configured to generate and output) Vc2 at the output based on a difference between Vref2 and a simulated output voltage (Vout-m) at the simulated output voltage node 134, in this configuration, for example, Vc2 can be set to be approximately equal to Vc1 generated by the voltage regulator 120 when Iout is just below but not exceeding Iout-max, which can be continuously applied to the control terminal 163 of the simulated transistor 160 such that the current density through the simulated transistor 160 is substantially the same as the current density through the pass transistor 110 at Iout-max. Furthermore, Vc2 can be selectively applied to the control terminal 113 of the pass transistor 110 during the over-current protection mode to prevent the output current at the output terminal 112 from rising above Iout-max.

[0038] As desired, the power supplies 100A, 100B can also include additional circuitry for detecting when over-current protection is needed (e.g., due to overload) and for automatically switching between the voltage regulation mode and the over-current protection mode (i.e., for automatically switching Vc applied to the control terminal 113 of the pass transistor 110 from Vc1 to Vc2, and vice versa). Specifically, the power supplies 100A, 100B can also include a comparator 141 that continuously compares (i.e., is configured to continuously compare) Vc1 from the voltage regulator 120 and Vc2 from the current limiter 130, and that outputs (i.e., is configured to output) a selection signal (SEL) having a logic value based on a difference between Vc1 and Vc2.

[0039] The power supplies 100A, 100B can also include a switching circuit 140 that selectively and automatically applies (i.e., is configured to selectively and automatically apply) either Vci or Vc2 to the control terminal 113 of the pass transistor 110 depending on the logic value of SEL. In some embodiments, the switching circuit 140 can include a pair of inverters connected in series (i.e., a first inverter 143 and a second inverter 145 connected in series), the first inverter 143 can receive SEL as an input from the comparator 141. The switching circuit can also include a pair of switches (i.e., a first switch 147 and a second switch 148), the second switch 148 can receive an inverted select signal (SELb) output from the first inverter 143 and is controlled by the inverted select signal (SELb), and depending on the logic value of SELb, can connect the output of the feedback amplifier 131 of the current limiter 130 to the control node 149 and thus to the control terminal 113 of the pass transistor 110 (i.e., can cause Vc2 to be applied to the control terminal 113), or alternatively, can disconnect the output of the feedback amplifier 131 from the control node 149, the first switch 147 can receive a double-inverted select signal (SEL2) from the second inverter 145 and is controlled by the double-inverted select signal (SEL2), and based on SEL2, can connect the output of the error amplifier 123 of the voltage regulator 120 to the control node 149 and thus to the control terminal 113 of the pass transistor 110 (i.e., can cause Vci to be applied to the control terminal 113), or alternatively, can disconnect the output of the error amplifier 123 from the control node 149, with this configuration, either Vci or Vc2 is applied to the control terminal 113 of the pass transistor 110 at any given time, but not both.

[0040] Figure 5 and Figure 6are schematic diagrams illustrating exemplary first and second switches 147, 148, respectively, which can be incorporated into the switching circuit 140 for selectively and alternatively applying either Vcl or Vc2 to the control terminal 113 of the pass transistor 110, each of these switches 147, 148 can include a p-type field effect transistor and an n-type field effect transistor connected in parallel between an input node (which receives the control voltage, e.g., Vcl in the case of the first switch 147 and Vc2 in the case of the second switch 148) and the control node 149, each of these switches 147, 148 can also include an additional inverter having an output connected to the gate of the p-type field effect transistor. In the first switch 147, a twice-inverted select signal (SEL2) is applied to the gate of the n-type field effect transistor and also to the input of the additional inverter, so that a thrice-inverted select signal is applied to the gate of the p-type field effect transistor. In the second switch 148, an inverted select signal (SELb) is applied to the gate of the n-type field effect transistor and also to the input of the additional inverter, so that another twice-inverted select signal is applied to the gate of the p-type field effect transistor.

[0041] With this configuration, if the SEL logic value of the comparator 141 is 1 (i.e., indicating that Vcl is greater than Vc2, no over-current protection is needed), then both the p-type field effect transistor and the n-type field effect transistor of the first switch 147 will be turned on, and Vcl will be applied to the control terminal 113 of the pass transistor 110, while both the p-type field effect transistor and the n-type field effect transistor of the second switch 148 will be turned off, and Vc2 will not be applied to the control terminal 113 of the pass transistor 110. Thus, the power supply 100A, 100B either continues to operate in the voltage regulation mode (if it was already operating in the voltage regulation mode) or switches back to operating in the voltage regulation mode. However, if the SEL logic value of the comparator 141 is 0 (i.e., indicating that Vcl is less than Vc2, over-current protection is needed), then both the p-type field effect transistor and the n-type field effect transistor of the first switch 147 will be turned off, Vcl will not be applied to the control terminal 113 of the pass transistor 110, while both the p-type field effect transistor and the n-type field effect transistor of the second switch 148 will be turned on, and Vc2 will be applied to the control terminal 113 of the pass transistor 110. Thus, the power supply 100A, 100B either switches to operating in the current protection mode or continues to operate in the over-current protection mode (if it was already operating in the over-current protection mode).

[0042] As mentioned above, the Iref generation circuit can optionally be a variable Iref generation circuit (e.g., refer to Figure 2 the variable Iref generation circuit 150A of the current limiter 130 in the power supply 100A, also refer to Figure 3the variable Iref generation circuit 150A, 150B automatically adjusts (i.e., can be configured to automatically adjust) Iref across the simulation output voltage node 134 such that during operation in the voltage regulation mode, Iref is at a first current level (Iref-vrm) resulting in Vc2 being at a first voltage level (Vc2-vrm), and such that during operation in the overcurrent protection mode, Iref is at a second current level (Iref-ocpm) resulting in Vc2 being at a second voltage level (Vc2-ocpm) different from the first voltage level. Specifically, the Iref generation circuit automatically adjusts (i.e., can be configured to automatically adjust) Iref such that when the power supply 100A, 100B is operating in the voltage regulation mode, Vc2 is set to the first voltage level (Vc2-vrm), which is approximately equal to Vci generated by the voltage regulator 120 when Iout is just below but not exceeding Iout-max. Thus, in the voltage regulation mode, Vci will be greater than Vc2. However, as described above, Vci is variable and it decreases as Iout increases until the load reaches Iout_max. Once Vci falls below Vc2, the comparator 141 will cause SEL to switch from a logic value of 1 to a logic value of 0, thereby switching the power supply 100A, 100B to operate in the overcurrent protection mode during which Vc2 will be applied to the control terminal 113 of the pass transistor as long as Vci is below Vc2. However, if Vc2 is maintained at the same voltage level during both the voltage regulation mode and the overcurrent protection mode, the power supply 100A, 100B can automatically switch back to the voltage regulation mode when Vc2 is applied to the control terminal 113 of the pass transistor 110, the power supply 100A, 100B can automatically switch back to the overcurrent protection mode when Vci is applied to the control terminal 113, and so on. To prevent this continuous oscillation between the two modes, the variable Iref generation circuit 150A, 150B can be used to automatically adjust the current level of Iref to be smaller in the overcurrent protection mode (i.e., such that during operation in the voltage regulation mode, Iref is at a first current level (Iref-vrm), and such that during operation in the overcurrent protection mode, Iref is at a second current level (Iref-ocpm) smaller than the first current level). Thus, during operation in the voltage regulation mode, Vc2 will be at the first voltage level (Vc2-vrm), and during operation in the overcurrent protection mode, Vc2 will be at a second voltage level (Vc2-ocpm) higher than the first voltage level. Thus, Vci will have to be pulled up to a higher level than it would have been before the power supply 100A, 100B can switch back from the overcurrent protection mode to the voltage regulation mode.In other words, Vc1 only needs to drop below Vc2-vrm for the switch to operate in overcurrent protection mode, but it must rise to at least Vc2-ocpm (i.e., Vc1 ≥ Vc2-ocpm) to trigger the switch to return to voltage regulation mode.

[0043] For example, such as Figure 2 As shown, in some embodiments, the variable Iref generation circuit 150A may include a resistor 152 (e.g., a variable resistor) connected to the simulated output voltage node 134. The variable Iref generation circuit 150A may also include an additional resistor 153 (also referred to herein as a hysteresis resistor) connected in series between the resistor 152 and ground (Vss) 199. The variable Iref generation circuit 150A may also include an NFET 151 connected in parallel with an additional resistor 153 and in series between a resistor 152 and ground (Vss) 199. The NFET 151 may have a gate connected to the output of the comparator 141, such that it is controlled by SEL. In this case, when the logic value of SEL is 1 (i.e., indicating that overcurrent protection is not required), the NFET 151 will be in the on state, and current will flow through the resistor 152 and the NFET 151 to ground (e.g., effectively bypassing the additional resistor 153), such that during operation in voltage regulation mode, Iref is at a first current level (Iref-vrm) and Vc2 is at a first voltage level (Vc2-vrm). However, when the logic value of SEL is 0 (i.e., indicating that overcurrent protection is required), the NFET 151 will switch to the off state to prevent current from flowing through the NFET 151. Therefore, during operation in overcurrent protection mode, current must flow through both resistor 152 and additional resistor 153 to ground, and Iref will drop to the second current level (Iref-ocpm), causing Vc2 to rise to the second voltage level (Vc2-ocpm). It should be noted that the following equation applies to the variable Iref generation circuit 150A.

[0044] Iref-vrm = Vout-m / Rref, and (5)

[0045] Iref-ocpm=Vout-m / (Rref+Rhyst), (6)

[0046] Where Vout-m is the simulated output voltage at node 134, Rref is the resistance value of resistor 152, and Rhyst is the resistance value of additional resistor 153.

[0047] In other embodiments, such as Figure 3As shown, the variable Iref generation circuit 150B can include a current source 155 (e.g., a variable current source) connected between the emulated output voltage node 134 and ground (Vss) 199. The variable Iref generation circuit 150B can also include an additional current source 154 (also referred to in the present disclosure as a hysteresis current source) also connected to the emulated output voltage node 134 and less than the current source 155. The variable Iref generation circuit 150B can also include an n-type field effect transistor (NFET) 151 (also referred to in the present disclosure as a hysteresis on / off switch) connected in series between the additional current source 154 and ground (Vss) 199, which can have a gate connected to the output of the comparator 141, such that it is controlled by SEL, in which case when the logic value of SEL is 1 (i.e., indicating that overcurrent protection is not needed), then the NFET 151 will be in an on state and current will flow through the additional current source 154 and the NFET 151 to ground, such that Iref in the voltage regulation mode (Iref-vrm) is at a first current level, while Vc2 is at a first voltage level (Vc2-vrm). However, when the logic value of SEL is 0 (i.e., indicating that overcurrent protection is needed), then the NFET 151 will be switched to an off state to prevent current from flowing from the additional current source 154 through the NFET 151. Thus, current will only flow to ground through the current source 155 and Iref in the overcurrent protection mode (Iref-ocpm) will drop to a second current level, causing Vc2 to rise to a second voltage level (Vc2-ocpm). It should be noted that for the variable Iref generation circuit 150B, the following equations apply,

[0048] Iref-vrm = Ivar + Ihyst, and (7)

[0049] Iref-ocpm = Ivar, (8)

[0050] where Ivar is the current through the current source 155, and Ihyst is the current through the additional current source 154.

[0051] Notably, the variable Iref generation circuits 150A, 150B can be configured such that the difference between the first voltage level of Vc2 during the voltage regulation mode (i.e., Vc2-vrm) and the second voltage level of Vc2 during the overcurrent protection mode (i.e., Vc2-ocpm) is relatively small. For example, Vc2-vrm can be a few millivolts (mV) or even 1 mV less than Vc2-ocpm. It should also be noted that this relatively small increase in Vc2 that occurs when entering the overcurrent protection mode will result in a corresponding relatively small decrease in Iout.

[0052] Referring again to Figure 2 andFigure 3 Optionally, the switching circuit 140 can also include at least one status monitor (e.g., at least one buffer) that can monitor (i.e., can be configured to monitor) the on / off state of a respective one of the switches 147 and 148 and can output (i.e., can be configured to output) a status signal indicative of the state of the switch and, thus, the mode of operation of the power supply 100A, 100B. For illustrative purposes, a single status monitor 170 is shown connected to the output of the first inverter 143, which can receive (i.e., can be configured to receive) SELB from the first inverter 143 and can output (i.e., can be configured to output) a mode status signal (MS) having a logic value indicative of whether the second switch 148 is on or off and, thus, whether the power supply 100A, 100B is operating in the over-current protection mode. It should be understood that, additionally or alternatively, such a status monitor can be connected to the output of the second inverter 145 and can receive (i.e., can be configured to receive) SEL2 from the second inverter 145 and can output (i.e., can be configured to output) a mode status signal having a logic value indicative of whether the first switch 147 is on or off and, thus, whether the power supply 100A, 100B is operating in the voltage regulation mode. As noted above, the power supply 100A, 100B can only operate in one of these two modes at any given time.

[0053] Referring to the flowchart of Figure 7 , embodiments of a power supply method associated with the power supply architecture described in detail above and generally outlined in Figure 1 , and more particularly in Figure 2 and Figure 3 , are also disclosed herein. The method can include supplying power to an electrical load 125 (e.g., a variable electrical load) through a pass transistor 110 of a power supply 100 (see process step 702). As described above, the pass transistor 110 can have an input end 111 connected to an input voltage node 115 that receives an input voltage (Vin); an output end 112 connected to an output voltage node 116 that outputs an output voltage (Vout); and a control end 113.

[0054] The method can also include generating and outputting, through a voltage regulator 120 of the power supply 100, a first control voltage (Vc1) for application to the control end 113 of the pass transistor 110 during the voltage regulation mode to maintain the output voltage (Vout) at the output voltage node 116 at a desired voltage level (see process step 704). Vc1 can be variable and can be generated specifically given Vin and based on Vout.

[0055] The method can further include generating and outputting, by the current limiter 130 of the power supply 100, a second control voltage (Vc2) for application to the control terminal 113 of the pass transistor 110 during the over-current protection mode to prevent the output current (Iout) from rising above a maximum output current limit (Iout-max) of the pass transistor 110 (see process step 706).

[0056] The method can further include automatically switching operation between the voltage regulation mode and the over-current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa) as needed to detect when over-current protection is needed (e.g., due to an overload) (see process steps 708-712).

[0057] More specifically, the method can include comparing Vc1, Vc2 by the comparator 141 of the power supply 100 and outputting, by the comparator 141, a selection signal (SEL) having a logic value dependent on the difference between Vc1 and Vc2 (see process step 708). The method can further include selectively and automatically applying either Vc1 to the control terminal 113 of the pass transistor 110 to enable or maintain operation in the voltage regulation mode (see process step 710) or Vc2 to the control terminal 113 of the pass transistor 110 to enable or maintain operation in the over-current protection mode (see process step 712) by the switching circuit 140 of the power supply 100 dependent on the logic value of SEL. For example, if SEL has a first logic value (e.g., logic value 1) indicating that over-current protection is not needed, the method can include applying Vc1 from the voltage regulator 120 to the control terminal 113 of the pass transistor 110 to either maintain the power supply 100 in the voltage regulation mode or switch the power supply 100 to the voltage regulation mode. Alternatively, if SEL has a second logic value (e.g., logic value 0) indicating that over-current protection is needed, the method can include applying Vc2 from the current limiter 130 to the control terminal 113 of the pass transistor 110 to either maintain the power supply 100 in the over-current protection mode or switch the power supply 100 to the over-current protection mode.

[0058] Optionally, the method can include automatically adjusting Vc2 to be at a first voltage level during the voltage regulation mode and to be at a slightly different second voltage level during the over-current protection mode to prevent continuous oscillation between the two modes. More specifically, as described above, Vc2 is generated and output at process step 706. However, if it is determined at process step 708 that Vci has dropped below Vc2, then the over-current protection mode will be initiated at process step 712 and Vc2 will be applied to the control terminal 113 of the pass transistor. As long as Vci remains below Vc2, Vci will be repeatedly compared to Vc2 and Vc2 will continue to be applied to the control terminal of the pass transistor. However, if Vci and Vc2 are approximately the same, then the power supply can automatically switch back to the voltage regulation mode once Vc2 is applied to the control terminal 113 of the pass transistor 110, automatically switch back to the over-current protection mode once Vci is applied to the control terminal 113, and so on. To prevent such continuous oscillation between the two modes (i.e., between process steps 710 and 712), the current level of Iref can be automatically decreased slightly from a first current level (Iref-vrm) to a second current level (Iref-ocpm) when switching from the voltage regulation mode to the over-current protection mode, such that the voltage level of Vc2 is automatically increased slightly from a first voltage level (Vc2-vrm) to a second voltage level (Vc2-ocpm) (see process step 714). Thus, Vci must be pulled higher than otherwise before switching back from operation in the over-current protection mode to operation in the voltage regulation mode. That is, Vci need only drop below Vc2-vrm to cause the switch to operate in the over-current protection mode, but it must rise at least to equal Vc2-ocpm (i.e., Vci > Vc2-ocpm) to trigger the switch back to operation in the voltage regulation mode. Furthermore, the current level of Iref can be automatically increased slightly from Iref-ocpm to Iref-vrm when switching from operation in the over-current protection mode to operation in the voltage regulation mode, such that the voltage level of Vc2 is automatically decreased slightly from Vc2-ocpm to Vc2-vrm (see process step 716). See the detailed discussion above regarding the operation of the variable Iref generation circuit 150A of the current limiter 130 of the power supply 100A of Figure 2 or the variable Iref generation circuit 150A of the current limiter 130 of the power supply 100B of Figure 3 .

[0059] It should be understood that the terminology used in this invention is for illustrative purposes of the disclosed methods and structures and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” “an,” and “the” are also intended to include the plural forms, unless the context otherwise requires. Furthermore, as used herein, the terms “comprising” and / or “including” indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Moreover, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “submerged,” “above,” “overlapping,” “parallel,” and “vertical” are intended to describe the relative positions as they are oriented and illustrated in the figures (unless otherwise indicated), and terms such as “contact,” “direct contact,” “adjacent,” “directly adjacent,” and “closely adjacent” are intended to indicate that at least one component is in physical contact with another component (without any other component separating the described components). The term "lateral" is used in this invention to describe the relative position of components, and more specifically, to indicate that a component is positioned to the side of another component rather than above or below it, as these components are oriented and illustrated in the drawings. For example, a component laterally adjacent to another component will be next to that component, a component laterally close to another component will be directly next to that component, and a component laterally surrounding another component will be adjacent to and bordering the outer side wall of that component. The structures, materials, actions, and all such means or steps, plus functional components, corresponding to the claims appended below are intended to include any structure, material, or action that performs a function in combination with other specially protected components.

[0060] The various specific embodiments described herein are for illustrative purposes only and are not intended to be exhaustive or limiting. Those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the disclosed embodiments. The terminology used in this invention is chosen to best explain the principles of the specific embodiments, to practically apply or to improve upon commercially available technologies, or to enable others skilled in the art to understand the specific embodiments disclosed herein.

[0061] Thus, disclosed above are embodiments of power supplies having integrated voltage regulators and integrated current limiters and configured to automatically switch between operation in a voltage regulation mode and an overcurrent protection mode as needed. These embodiments do not require generation of a replica of Iout for overcurrent protection, but rather they employ a reference voltage and a replica transistor having the same current density as the pass transistor to generate a mode-specific control voltage for application to the control terminal of the pass transistor. Thus, matching is relatively easy, the quiescent current of all electrical loads is constant, losses are low, and fast loop correction is not needed. Furthermore, because the voltage regulator does not need to be enabled, the configuration of the disclosed power supplies provides for fast recovery from the overcurrent protection mode back to the voltage regulation mode. Instead, the voltage regulator continuously generates Vcl, while the current limiter continuously generates Vc2, and the switching between the two modes (i.e., between applying Vcl to the control terminal of the pass transistor and applying Vc2 to the control terminal of the pass transistor) is dynamic, depending only on the relationship between Vcl and Vc2.

Claims

1. A power supply structure, characterized in that, include: Input voltage node; Output voltage node; The channel transistor includes: an input terminal directly connected to the input voltage node; an output terminal connected to the output voltage node; and a control terminal; A voltage regulator adapted to output a first control voltage based on the output voltage at the output voltage node; A current limiter, adapted to output a second control voltage, and including an input terminal connected to the input voltage node; A comparator adapted to compare the first control voltage and the second control voltage, and output a selection signal based on the difference between the first control voltage and the second control voltage; and A switching circuit adapted to apply one of the first control voltage and the second control voltage to the control terminal of the channel transistor based on the selection signal.

2. The power supply structure as described in claim 1, characterized in that, This channel transistor has a maximum output current limit. The comparator and the switching circuit are configured to automatically switch the operation control of the channel transistor from the first control voltage to the second control voltage. Wherein, as long as the output current from the channel transistor is less than the maximum output current limit, the first control voltage controls the operation of the channel transistor to adjust the output voltage at the output voltage node, and Specifically, when the output current reaches the maximum output current limit, the second control voltage controls the operation of the channel transistor to prevent the maximum output current limit from being exceeded.

3. The power supply structure as described in claim 1, characterized in that, The channel transistor includes either a p-type field-effect transistor or a pnp bipolar junction transistor, and the voltage regulator includes a low-dropout voltage regulator.

4. The power supply structure as described in claim 1, characterized in that, The voltage regulator includes: A pair of resistors are connected in series between the output voltage node and ground; and An error amplifier includes: a non-inverting input connected to a feedback voltage node between the pair of resistors; an inverting input receiving a first reference voltage; and an output connected to the comparator and the switching circuit, wherein the error amplifier is configured to output the first control voltage based on the difference between the feedback voltage at the feedback voltage node and the first reference voltage.

5. The power supply structure as described in claim 1, characterized in that, The current limiter includes: Simulate the output voltage node; The simulated transistor includes: an input terminal connected to the input voltage node; an output terminal connected to the simulated output voltage node; and a control terminal; and A feedback amplifier includes: a non-inverting input connected to the simulated output voltage node; an inverting input receiving a second reference voltage; and an output connected to the control terminal of the simulated transistor, the comparator, and the switching circuit, wherein the feedback amplifier is configured to output the second control voltage based on the difference between the simulated output voltage at the simulated output voltage node and the second reference voltage.

6. The power supply structure as described in claim 5, characterized in that, The current limiter also includes a variable reference current generation circuit, and The variable reference current generation circuit is configured to automatically adjust the reference current across the simulated output voltage node such that during voltage regulation mode, the reference current is at a first current level, causing the second control voltage to be at a first voltage level, and during overcurrent protection mode, the reference current is at a second current level, causing the second control voltage to be at a second voltage level different from the first voltage level.

7. A power supply structure, characterized in that, include: Input voltage node; Output voltage node; The p-channel transistor includes: an input terminal directly connected to the input voltage node; an output terminal connected to the output voltage node; and a control terminal. A voltage regulator adapted to output a first control voltage based on the output voltage at the output voltage node; A current limiter, adapted to output a second control voltage, and including an input terminal connected to the input voltage node; A comparator is adapted to compare the first control voltage with and the second control voltage, and output a selection signal based on the difference between the first control voltage and the second control voltage, wherein the selection signal has a first logic value when the first control voltage is greater than the second control voltage, and has a second logic value when the first control voltage is less than the second control voltage; and The switching circuit is adapted to apply a first control voltage to the control terminal of the channel transistor when the selection signal has the first logic value, and to apply a second control voltage to the control terminal of the p-type channel transistor when the selection signal has the second logic value.

8. The power supply structure as described in claim 7, characterized in that, This p-channel transistor has a maximum output current limit. The comparator and the switching circuit are configured to automatically switch the operation control of the p-type channel transistor from the first control voltage to the second control voltage. Wherein, as long as the output current from the p-type channel transistor is less than the maximum output current limit, the first control voltage controls the operation of the p-type channel transistor to adjust the output voltage at the output voltage node, and When the output current of the p-type channel transistor reaches the maximum output current limit, the second control voltage controls the operation of the p-type channel transistor to prevent the maximum output current limit from being exceeded.

9. The power supply structure as described in claim 7, characterized in that, The p-channel transistor includes either a p-type field-effect transistor or a pnp bipolar junction transistor, and the voltage regulator includes a low-dropout voltage regulator.

10. The power supply structure as described in claim 7, characterized in that, The voltage regulator includes: A pair of resistors are connected in series between the output voltage node and ground; and An error amplifier includes: a non-inverting input connected to a feedback voltage node between the pair of resistors; an inverting input receiving a first reference voltage; and an output connected to the comparator and the switching circuit, wherein the error amplifier is configured to output the first control voltage based on the difference between the feedback voltage at the feedback voltage node and the first reference voltage.

11. The power supply structure as described in claim 7, characterized in that, The current limiter includes: Simulate the output voltage node; A p-type simulated transistor includes: an input terminal connected to the input voltage node; an output terminal connected to the simulated output voltage node; and a control terminal; and A feedback amplifier includes: a non-inverting input connected to the simulated output voltage node; an inverting input receiving a second reference voltage; and an output connected to the control terminal of the p-type simulated transistor, the comparator, and the switching circuit, wherein the feedback amplifier is configured to output the second control voltage based on the difference between the simulated output voltage at the simulated output voltage node and the second reference voltage.

12. The power supply structure as described in claim 11, characterized in that, The current limiter also includes a variable reference current generation circuit, and The variable reference current generation circuit is configured to automatically adjust the reference current across the simulated output voltage node such that during voltage regulation mode, the reference current is at a first current level, causing the second control voltage to be at a first voltage level, and during overcurrent protection mode, the reference current is at a second current level, causing the second control voltage to be at a second voltage level different from the first voltage level.

13. The power supply structure as described in claim 12, characterized in that, The first logic value of the selection signal is 1, and the second logic value of the selection signal is 0. The variable reference current generation circuit includes: The resistor connected to the simulated output voltage node; An additional resistor is connected in series between the resistor and ground; and An n-type field-effect transistor connected in parallel with the additional resistor and also in series between the resistor and ground, and The n-type field-effect transistor has a gate controlled by the selection signal.

14. The power supply structure as described in claim 12, characterized in that, The first logic value of the selection signal is 1, and the second logic value of the selection signal is 0. The variable reference current generation circuit includes: A current source connected between the simulation output voltage node and ground; An additional current source is connected to the simulated output voltage node; and An n-type field-effect transistor connected in series between the additional current source and ground, and The n-type field-effect transistor has a gate controlled by the selection signal.

15. The power supply structure as described in claim 7, characterized in that, The first logic value of the selection signal is 1, and the second logic value of the selection signal is 0, and The switching circuit includes: A first inverter and a second inverter connected in series, wherein the first inverter receives the selection signal from the comparator; First switch; and Second switch, The second switch receives an inverting selection signal from the first inverter, and based on this inverting selection signal, either connects the current limiter to the control terminal of the p-type channel transistor or disconnects the current limiter from the control terminal of the p-type channel transistor. The first switch receives a secondary inverting selection signal from the second inverter, and based on the secondary inverting selection signal, either connects the voltage regulator to the control terminal of the p-type channel transistor or disconnects the voltage regulator from the control terminal of the p-type channel transistor.

16. The power supply structure as described in claim 15, characterized in that, The first switch and the second switch each include: a p-type field-effect transistor and an n-type field-effect transistor connected in parallel between the input node and the output node; and an additional inverter connected to the gate of the p-type field-effect transistor. In the first switch, the secondary inverting selection signal is applied to the gate of the additional inverter and the gate of the n-type field-effect transistor, and In the second switch, the inverting selection signal is applied to the gate of the additional inverter and the n-type field-effect transistor.

17. A method for supplying power, characterized in that, The method includes: The power supply provides power to the electrical load via a channel transistor, wherein the channel transistor includes: an input terminal directly connected to the input voltage node; an output terminal connected to the output voltage node; and a control terminal; Based on the output voltage of the output voltage node, a first control voltage is generated by the voltage regulator of the power supply; A second control voltage is generated by a current limiter of the power supply, wherein the current limiter includes an input terminal connected to the input voltage node; The comparator of the power supply compares the first control voltage with the second control voltage, and based on the difference between the first control voltage and the second control voltage, the comparator outputs a selection signal; and Based on the selection signal, one of the first control voltage and the second control voltage is applied to the control terminal of the channel transistor through the power supply switching circuit.

18. The method as described in claim 17, characterized in that, This channel transistor has a maximum output current limit. Specifically, the output of the selection signal, and the application of one of the first control voltage and the second control voltage to the control terminal of the channel transistor based on the selection signal, cause the operation control of the channel transistor to automatically switch from the first control voltage to the second control voltage. Wherein, as long as the output current from the channel transistor is less than the maximum output current limit, the first control voltage controls the operation of the channel transistor to adjust the output voltage at the output voltage node, and Specifically, when the output current reaches the maximum output current limit, the second control voltage controls the operation of the channel transistor to prevent the maximum output current limit from being exceeded.

19. The method as described in claim 17, characterized in that, The voltage regulator includes a low-dropout voltage regulator.

20. The method as described in claim 17, characterized in that, It also includes automatically setting the second control voltage to the first voltage level during voltage regulation mode, and automatically setting the second control voltage to a second voltage level different from the first voltage level during overcurrent protection mode.

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