Optical signal transmitting apparatus, optical signal receiving apparatus, optical communication system and method

Abstract

An optical signal sending device, an optical signal receiving device, an optical communication system and a method, the optical signal sending device comprising: a control circuit and a driving backboard; the control circuit comprising: a control sub-circuit, a first signal processing sub-circuit and a second signal processing sub-circuit, the driving backboard comprising a plurality of light emitting device units; the control sub-circuit is configured to generate a first driving signal; the first signal processing sub-circuit is electrically connected with the control sub-circuit and is configured to generate a second driving signal according to the first driving signal; the second signal processing sub-circuit is electrically connected with the first signal processing sub-circuit and is configured to process a signal swing of the second driving signal, generate a third driving signal, and generate a light emitting driving signal according to the third driving signal; the driving backboard is electrically connected with the second signal processing sub-circuit and is configured to emit an optical signal according to the light emitting driving signal.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of optical communication technology, specifically to an optical signal transmitting device, an optical signal receiving device, an optical communication system, and a method. Background Technology

[0002] Visible light communication (VLS) is an emerging wireless optical communication technology that uses the invisible, high-speed flickering signals emitted by light-emitting components such as fluorescent lamps or LEDs to transmit information. Optical components receive the light signals and convert them into electrical signals to achieve signal reception and conversion. VLS boasts advantages such as wide applicability, practicality, security, high speed, and wide spectrum, potentially filling gaps in current wireless communication. Communication can be achieved wherever there is light, making it applicable to various fields. While current solutions combining display panels and optical communication can achieve optical communication, they impact the lifespan of the backlight. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides an optical signal transmitting device, including: a control circuit and a driving backplane; the control circuit includes: a control sub-circuit, a first signal processing sub-circuit and a second signal processing sub-circuit, and the driving backplane includes a plurality of light-emitting device units;

[0005] The control sub-circuit is configured to generate a first drive signal;

[0006] The first signal processing sub-circuit, electrically connected to the control sub-circuit, is configured to generate a second drive signal based on the first drive signal;

[0007] The second signal processing sub-circuit, which is electrically connected to the first signal processing sub-circuit, is configured to process the signal swing of the second driving signal, generate a third driving signal, and generate a light-emitting driving signal based on the third driving signal.

[0008] The driving backplane is electrically connected to the second signal processing sub-circuit and is configured to emit a light signal according to the light emission driving signal.

[0009] In an exemplary embodiment, the first signal processing sub-circuit includes a digital-to-analog conversion sub-circuit and an amplification sub-circuit, and the second signal processing sub-circuit includes an attenuation sub-circuit and an AC / DC coupling sub-circuit.

[0010] The digital-to-analog converter sub-circuit is electrically connected to the control sub-circuit and is configured to convert the first drive signal into a digital-to-analog signal to form a first analog drive signal, wherein the first drive signal is a digital signal.

[0011] The amplification sub-circuit is electrically connected to the digital-to-analog conversion sub-circuit and is configured to amplify the first analog drive signal to generate a second drive signal, wherein the second drive signal is an analog signal.

[0012] The attenuation sub-circuit, electrically connected to the amplification sub-circuit, is configured to process the signal swing of the second driving signal to generate a third driving signal, wherein the third driving signal is an analog signal and is an AC signal.

[0013] An AC / DC coupling sub-circuit, electrically connected to the attenuation sub-circuit, is configured to generate a light-emitting driving signal based on a third driving signal, wherein the light-emitting driving signal is an analog signal.

[0014] The AC / DC coupling sub-circuit includes an AC input terminal and a DC input terminal, and the attenuation sub-circuit is electrically connected to the AC input terminal of the AC / DC coupling circuit.

[0015] In an exemplary embodiment, it further includes: a first power supply sub-circuit and a second power supply sub-circuit;

[0016] The first power supply sub-circuit is electrically connected to the control sub-circuit, the digital-to-analog converter sub-circuit, the amplifier sub-circuit, the attenuation sub-circuit, the AC / DC coupling sub-circuit, and the drive backplane, and is configured to provide a first power signal.

[0017] The second power supply sub-circuit is electrically connected to the DC input terminal of the AC / DC coupling sub-circuit and is configured to provide a second power supply signal, wherein the first power supply signal and the second power supply signal are DC current signals.

[0018] In an exemplary embodiment, the digital-to-analog conversion subcircuit includes a digital-to-analog converter; the amplification subcircuit includes a first operational amplifier; the AC / DC coupling subcircuit includes a bias subcircuit; and the attenuation subcircuit includes a first attenuation resistor, a second attenuation resistor, a third attenuation resistor, an attenuation capacitor, and a second operational amplifier.

[0019] The first end of the attenuation capacitor is electrically connected to the amplification sub-circuit, the second end of the attenuation capacitor is electrically connected to the first end of the first attenuation resistor, the second end of the first attenuation resistor is electrically connected to the inverting input terminal of the second operational amplifier and the first end of the second attenuation resistor, the second end of the second attenuation resistor is electrically connected to the output terminal of the second operational amplifier, the first end of the third attenuation resistor is electrically connected to the non-inverting input terminal of the second operational amplifier, and the first end of the third attenuation resistor is electrically connected to the first power supply sub-circuit or the second power supply sub-circuit.

[0020] The resistance value of the third attenuation resistor is equal to the ratio of the resistance value of the first attenuation resistor to the resistance value of the second attenuation resistor.

[0021] In an exemplary embodiment, the driving backplane further includes: a driving circuit configured to drive the light-emitting device unit to emit light, the driving circuit including: a first light-emitting resistor, a second light-emitting resistor, a third light-emitting resistor, a light-emitting capacitor, and a light-emitting transistor; the light-emitting device unit includes a first electrode and a second electrode;

[0022] The first power supply sub-circuit is electrically connected to the first electrode of the light-emitting device unit and the first terminal of the second light-emitting resistor, respectively. The second electrode of the light-emitting device unit is electrically connected to the first electrode of the light-emitting transistor. The control electrode of the light-emitting transistor is electrically connected to the AC / DC coupling sub-circuit, the first terminal of the first light-emitting resistor, and the second terminal of the second light-emitting resistor, respectively. The second electrode of the light-emitting transistor is electrically connected to the first terminal of the third light-emitting resistor and the first terminal of the light-emitting capacitor, respectively. The second terminals of the first light-emitting resistor, the third light-emitting resistor, and the light-emitting capacitor are grounded.

[0023] The light-emitting transistor is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor.

[0024] Secondly, this disclosure also provides an optical signal receiving device, including: a photoelectric conversion sub-circuit and a third signal processing sub-circuit;

[0025] The photoelectric conversion sub-circuit is configured to receive an optical signal and convert the received optical signal into a first electrical signal, wherein the first electrical signal is an analog signal and is a differential signal;

[0026] The third signal processing sub-circuit is electrically connected to the photoelectric conversion sub-circuit and is configured to convert the first electrical signal into a second electrical signal, wherein the second electrical signal is a digital signal and includes a clock signal.

[0027] In an exemplary embodiment, it further includes: a third power supply sub-circuit, which is electrically connected to the photoelectric conversion sub-circuit and the third signal processing sub-circuit, respectively, and is configured to provide a third power supply signal.

[0028] In an exemplary embodiment, the photoelectric conversion sub-circuit includes: a photoelectric converter and a transimpedance amplifier;

[0029] The photoelectric converter, electrically connected to the transimpedance amplifier, is configured to convert the received optical signal into an initial electrical signal, wherein the initial electrical signal is a current signal.

[0030] The transimpedance amplifier, electrically connected to the third signal processing sub-circuit, is configured to convert the initial electrical signal into a voltage signal and amplify it to generate the first electrical signal.

[0031] In an exemplary embodiment, the optical signal transmitting device includes: a control sub-circuit;

[0032] The third signal processing sub-circuit is also electrically connected to the control sub-circuit and is configured to transmit the second electrical signal to the control sub-circuit.

[0033] In an exemplary embodiment, the third signal processing sub-circuit includes: a clock reset sub-circuit, the clock reset sub-circuit including: a reset control chip;

[0034] The reset control chip includes: an active power pulse output pin, a reactive power pulse output pin, a positive analog input pin, a negative analog input pin, a first digital power supply pin, a second digital power supply pin, a first analog power supply pin, a second analog power supply pin, a positive digital output pin, a negative digital output pin, a positive clock output pin, a negative clock output pin, a digital ground pin, and an analog ground pin; wherein, the active power pulse output pin and the reactive power pulse output pin are electrically connected, the first digital power supply pin, the second digital power supply pin, the first analog power supply pin, and the second analog power supply pin are electrically connected to a third power supply sub-circuit, the positive analog input pin and the negative analog input pin are electrically connected to a transimpedance amplifier, the positive digital output pin, the negative digital output pin, the positive clock output pin, and the negative clock output pin are electrically connected to a control sub-circuit, and the digital ground pin and the analog ground pin are grounded.

[0035] In an exemplary embodiment, the clock reset sub-circuit further includes an input processing sub-circuit and an output processing sub-circuit. The input processing sub-circuit includes a first resistor to a fourth resistor and a first capacitor to a fourth capacitor. The output processing sub-circuit includes a fifth resistor to a sixteenth resistor and a fifth capacitor to an eighth capacitor.

[0036] The first terminal of the first capacitor and the first terminal of the second capacitor are electrically connected to the transimpedance amplifier. The second terminal of the first capacitor is electrically connected to the positive analog input pin and the first terminal of the fourth resistor, respectively. The second terminal of the second capacitor is electrically connected to the first terminal of the first resistor and the negative analog input pin, respectively. The first terminal of the third capacitor is electrically connected to the second terminals of the first resistor, the second resistor, the third resistor, and the fourth resistor, respectively. The second terminals of the third capacitor and the second resistor are grounded. The first terminal of the fourth capacitor is electrically connected to the active power pulse output pin, and the second terminal of the fourth capacitor is electrically connected to the reactive power pulse output pin. The second terminal of the third resistor is electrically connected to the third power supply sub-circuit.

[0037] The first terminals of the fifth, sixth, seventh, and eighth capacitors are electrically connected to the control sub-circuit. The second terminal of the fifth capacitor is electrically connected to the first terminals of the fifth and ninth resistors, respectively. The second terminal of the sixth capacitor is electrically connected to the first terminals of the sixth and tenth resistors, respectively. The second terminal of the seventh capacitor is electrically connected to the first terminals of the seventh and eleventh resistors, respectively. The second terminal of the eighth capacitor is electrically connected to the first terminals of the eighth and twelfth resistors, respectively. The second terminal of the fifth resistor is electrically connected to the first terminal of the thirteenth resistor and the negative digital output pin, respectively. The second terminal of the sixth resistor is electrically connected to the first terminal of the fourteenth resistor and the positive digital output pin, respectively. The second terminal of the seventh resistor is electrically connected to the first terminal of the fifteenth resistor and the negative clock output pin, respectively. The second terminal of the eighth resistor is electrically connected to the first terminal of the sixteenth resistor and the positive clock output pin, respectively. The second terminals of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth resistors are grounded.

[0038] Thirdly, this disclosure also provides an optical communication system, including: the above-mentioned optical signal transmitting device and / or the above-mentioned optical signal receiving device.

[0039] In an exemplary embodiment, it further includes: a signal processing device;

[0040] The signal processing device is electrically connected to the optical signal transmitting device and is configured to filter the signal received by the optical signal transmitting device.

[0041] Fourthly, this disclosure also provides an optical communication method applied in the above-mentioned optical signal transmitting device, the method comprising:

[0042] Generate the first drive signal;

[0043] A second drive signal is generated based on the first drive signal;

[0044] The signal swing of the second driving signal is processed to generate a third driving signal, and a light-emitting driving signal is generated based on the third driving signal.

[0045] A light signal is emitted according to the light emission driving signal.

[0046] Fifthly, this disclosure also provides an optical communication method applied in the above-mentioned optical signal receiving device, the method comprising:

[0047] The system receives optical signals and converts the received optical signals into a first electrical signal, wherein the first electrical signal is an analog signal and is a differential signal;

[0048] The first electrical signal is converted into a second electrical signal, the second electrical signal being a digital signal and including a clock signal.

[0049] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0050] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0051] Figure 1 This is a schematic diagram of the structure of the optical signal transmitting device provided in the embodiments of this disclosure;

[0052] Figure 2 A schematic diagram of the structure of an optical signal transmitting device provided for an exemplary embodiment;

[0053] Figure 3 The equivalent circuit diagrams for the attenuation sub-circuit and the AC / DC coupling sub-circuit are shown below.

[0054] Figure 4 A schematic diagram of the structure of an optical signal transmitting device provided for an exemplary embodiment;

[0055] Figure 5 This is a schematic diagram of the structure of the optical signal receiving device provided in the embodiments of this disclosure;

[0056] Figure 6 A schematic diagram of the structure of an optical signal receiving device provided for an exemplary embodiment;

[0057] Figure 7 This is a schematic diagram of the clock reset sub-circuit.

[0058] Figure 8 This is a schematic diagram of the structure of an optical communication system provided in an embodiment of this disclosure. Detailed Implementation

[0059] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0060] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0061] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0062] Unless otherwise defined, the technical or scientific terms used in the embodiments of this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0063] Currently, optical communication systems consist of signal transmitting devices and signal receiving devices. The signal transmitting device sends optical signals, and the signal receiving device converts the optical signals into electrical signals. The signal output by the signal transmitting device is unstable, and the signal receiving device is expensive and complex in structure, resulting in low efficiency and poor stability of the entire optical communication system.

[0064] Figure 1 This is a schematic diagram of the structure of an optical signal transmitting device provided in an embodiment of this disclosure. Figure 1 As shown, the optical signal transmitting device 100 provided in this embodiment may include a control circuit 100A and a driving backplane 100B. The control circuit 100A may include a control sub-circuit 110, a first signal processing sub-circuit 120, and a second signal processing sub-circuit 130. The driving backplane 100B may include multiple light-emitting device units.

[0065] In an exemplary embodiment, a control sub-circuit 110 is configured to generate a first driving signal; a first signal processing sub-circuit 120, electrically connected to the control sub-circuit 110, is configured to generate a second driving signal based on the first driving signal; a second signal processing sub-circuit 130, electrically connected to the first signal processing sub-circuit 120, is configured to process the signal swing of the second driving signal to generate a third driving signal, and generate a light emission driving signal based on the third driving signal; and a driving backplane 100B, electrically connected to the second signal processing sub-circuit 130, is configured to emit a light signal based on the light emission driving signal.

[0066] In an exemplary embodiment, the control sub-circuit 110 can generate a first drive signal based on the control signal. The control signal can be sent by a terminal (e.g., a computer or a mobile phone). For example, the control signal can be sent by the RS232 interface of a computer.

[0067] In an exemplary embodiment, the control sub-circuit 110 may be a circuit board, such as a field-programmable gate array (FPGA) circuit board.

[0068] In an exemplary embodiment, the control sub-circuit includes a general-purpose input / output interface (GPIO), through which control signals can be input and first drive signals can be output.

[0069] In an exemplary embodiment, the light-emitting device unit may include at least one light-emitting element, which may be a light-emitting diode.

[0070] In an exemplary embodiment, the optical signal transmitting device may be a mobile device, and at least one light-emitting element may be a flash lamp on the mobile device.

[0071] This disclosure improves the stability and efficiency of the optical signal emission device by processing the signal swing of the second driving signal through a second signal processing sub-circuit to generate a third driving signal, thereby ensuring that the light emission driving signal is within the working range of the light emission device unit.

[0072] In an exemplary embodiment, Figure 2 A schematic diagram of the structure of an optical signal transmitting device provided in an exemplary embodiment. Figure 3This is the equivalent circuit diagram of the attenuation sub-circuit and the AC / DC coupling sub-circuit. For example... Figure 2 and Figure 3 As shown, the first signal processing sub-circuit 120 may include a digital-to-analog conversion sub-circuit 121 and an amplification sub-circuit 122, and the second signal processing sub-circuit 130 may include an attenuation sub-circuit 131 and an AC / DC coupling sub-circuit 132.

[0073] In an exemplary embodiment, the digital-to-analog converter sub-circuit 121 is electrically connected to the control sub-circuit and is configured to convert the first drive signal into a digital signal to form a first analog drive signal, wherein the first drive signal is a digital signal.

[0074] In an exemplary embodiment, the digital-to-analog converter sub-circuit 121 may include a digital-to-analog converter.

[0075] In an exemplary embodiment, the amplification sub-circuit 122, electrically connected to the digital-to-analog converter sub-circuit 121, is configured to amplify the first analog drive signal to generate a second drive signal, wherein the second drive signal is an analog signal.

[0076] In an exemplary embodiment, the amplifier sub-circuit 122 may include a first operational amplifier.

[0077] In an exemplary embodiment, the attenuation sub-circuit 131, electrically connected to the amplification sub-circuit 122, is configured to process the signal swing of the second drive signal to generate a third drive signal, which is an analog signal and an AC signal.

[0078] In an exemplary implementation, such as Figure 3 As shown, the attenuation sub-circuit 131 may include: a first attenuation resistor SR1, a second attenuation resistor SR2, a third attenuation resistor SR3, an attenuation capacitor SC, and a second operational amplifier SF. The first terminal of the attenuation capacitor SC is electrically connected to the amplification sub-circuit 122; the second terminal of the attenuation capacitor SC is electrically connected to the first terminal of the first attenuation resistor SR1; the second terminal of the first attenuation resistor SR1 is electrically connected to both the inverting input terminal of the second operational amplifier SF and the first terminal of the second attenuation resistor SR2; the second terminal of the second attenuation resistor SR2 is electrically connected to the output terminal of the second operational amplifier SF; the first terminal of the third attenuation resistor SR3 is electrically connected to the non-inverting input terminal of the second operational amplifier SF; and the first terminal of the third attenuation resistor SR3 is electrically connected to the power supply signal Vcc2.

[0079] In an exemplary embodiment, the overall voltage gain A of the attenuation sub-circuit satisfies A = r2 / r1, where r1 is the resistance value of the first attenuation resistor SR1 and r2 is the resistance value of the second attenuation resistor SR2. That is, this disclosure can change the attenuation ratio at the output of the second operational amplifier SF by controlling the ratio of the resistance values ​​of the first attenuation resistor SR1 and the second attenuation resistor SR2.

[0080] In an exemplary implementation, such as Figure 3 As shown, the second operational amplifier SF is also electrically connected to the first power supply signal Vcc1.

[0081] In an exemplary embodiment, the power signal Vcc2 can be either a first power signal or a second power signal.

[0082] In an exemplary embodiment, the resistance value of the third attenuation resistor SR3 is equal to the ratio of the resistance value of the first attenuation resistor SR1 to the resistance value of the second attenuation resistor SR2. This ratio ensures symmetry of the parameters at the two input terminals of the second operational amplifier circuit, preventing the generation of additional bias voltages.

[0083] In an exemplary embodiment, the AC / DC coupling sub-circuit 132, electrically connected to the attenuation sub-circuit 131, is configured to generate a light-emitting driving signal based on a third driving signal, wherein the light-emitting driving signal is an analog signal.

[0084] In an exemplary implementation, such as Figure 3 As shown, the AC / DC coupling sub-circuit may include an AC input terminal ACIN and a DC input terminal DCIN. The attenuation sub-circuit 131 is electrically connected to the AC input terminal ACIN of the AC / DC coupling circuit. The DC input terminal DCIN is configured to provide a sufficient DC signal to make the light-emitting device unit emit light, and the AC input terminal is configured to provide an AC signal, causing the brightness of the light-emitting device unit to change continuously, thereby realizing the transmission of the light signal. The light-emitting driving signal is the signal input from the coupled DC input terminal and the signal input from the AC input terminal.

[0085] In an exemplary embodiment, the AC / DC coupling sub-circuit further includes an output terminal OUT, and the AC / DC coupling sub-circuit includes a bias sub-circuit. For example... Figure 3As shown, the bias sub-circuit includes a bias capacitor BC and a bias oscillator BL. The first end of the bias capacitor BC serves as an AC input terminal and is electrically connected to the attenuation sub-circuit 131. The second end of the bias capacitor BC serves as an output terminal and is electrically connected to the first end of the bias oscillator BL. The second end of the bias oscillator BL serves as a DC input terminal and is electrically connected to the third power supply signal Vcc3. The power supply signal Vcc3 can be the same as the first power supply signal or the same as the second power supply signal. That is, the second end of the bias oscillator BL can be electrically connected to the first power supply sub-circuit or the second power supply sub-circuit.

[0086] In an exemplary embodiment, the output terminal OUT of the AC / DC coupling sub-circuit is electrically connected to the drive backplane.

[0087] In an exemplary implementation, such as Figure 2 As shown, the optical signal transmitting device 100 may further include: a first power supply sub-circuit 100C and a second power supply sub-circuit 100D.

[0088] In an exemplary implementation, such as Figure 2 As shown, the first power supply sub-circuit 100C is electrically connected to the control sub-circuit 110, the digital-to-analog converter sub-circuit 121, the amplifier sub-circuit 122, the attenuator sub-circuit 131, the AC / DC coupling sub-circuit 132, and the drive backplane 100B, and is configured to provide a first power signal to the control sub-circuit 110, the digital-to-analog converter sub-circuit 121, the amplifier sub-circuit 122, the attenuator sub-circuit 131, the AC / DC coupling sub-circuit 132, and the drive backplane 100B.

[0089] In an exemplary implementation, such as Figure 2 As shown, the second power supply sub-circuit 100D is electrically connected to the DC input terminal of the AC / DC coupling sub-circuit 132 and is configured to provide a second power signal to the DC input terminal of the AC / DC coupling sub-circuit.

[0090] In an exemplary implementation, such as Figure 2 As shown, the first power supply signal and the second power supply signal are DC current signals.

[0091] In an exemplary embodiment, Figure 4 This is a schematic diagram of the structure of an optical signal transmitting device provided for an exemplary embodiment. (See diagram below.) Figure 4 As shown, the driving backplane 100B also includes a driving circuit configured to drive the light-emitting device unit to emit light. The driving circuit includes a first light-emitting resistor LR1, a second light-emitting resistor LR2, a third light-emitting resistor LR3, a light-emitting capacitor C, and a light-emitting transistor LT. The light-emitting device unit L includes a first electrode and a second electrode.

[0092] In an exemplary implementation, such as Figure 4As shown, the first electrode of the light-emitting device unit L and the first terminal of the second light-emitting resistor LR2 are electrically connected to the first power signal of the first power supply sub-circuit. The second electrode of the light-emitting device unit L is electrically connected to the first electrode of the light-emitting transistor LT. The control electrode of the light-emitting transistor LT is electrically connected to the AC / DC coupling sub-circuit 132, the first terminal of the first light-emitting resistor LR1, and the second terminal of the second light-emitting resistor LR2. The second electrode of the light-emitting transistor LR2 is electrically connected to the first terminal of the third light-emitting resistor LR3 and the first terminal of the light-emitting capacitor C. The second terminals of the first light-emitting resistor LR1, the third light-emitting resistor LR3, and the second terminal of the light-emitting capacitor C are grounded.

[0093] In an exemplary embodiment, the light-emitting transistor is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor.

[0094] In this disclosure, a common-source circuit is used. The light-emitting device unit L is connected between the power supply signal and the first terminal of the light-emitting transistor LT. The resistance value can be adjusted according to the voltage value of the light-emitting drive signal output by the second signal processing sub-circuit and the current value of the light-emitting device unit L, so as to provide a dynamic current for the light-emitting device unit L and ensure the brightness change of the light-emitting device unit L.

[0095] The driving circuit in this disclosure is current driven, which makes the intensity of the optical signal proportional to the magnitude of the light-emitting driving signal, which is more conducive to the complete transmission of the optical signal.

[0096] In an exemplary embodiment, the control electrode of the light-emitting transistor LT is electrically connected to the output terminal OUT of the AC / DC coupling sub-circuit 132.

[0097] Figure 5 This is a schematic diagram of the structure of an optical signal receiving device provided in an embodiment of this disclosure. Figure 5 As shown, the optical signal receiving device 200 provided in this embodiment may include: a photoelectric conversion sub-circuit 210 and a third signal processing sub-circuit 220. The photoelectric conversion sub-circuit 210 is configured to receive an optical signal and convert the received optical signal into a first electrical signal, which is an analog signal and a differential signal. The third signal processing sub-circuit 220 is electrically connected to the photoelectric conversion sub-circuit 210 and is configured to convert the first electrical signal into a second electrical signal, which is a digital signal and includes a clock signal.

[0098] In the exemplary embodiments, the optical signal can be the optical signal emitted by the optical signal transmitting device provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0099] This disclosure replaces the analog-to-digital converter and operational amplifier in the prior art by setting a third signal processing sub-circuit, integrating analog-to-digital conversion and amplification functions into one structure. This simplifies the structure of the optical signal receiving device while achieving the transmission effect of the optical signal receiving device, reduces the circuit cost and area of ​​the optical signal receiving device, and is more conducive to the miniaturization design of the optical signal receiving device.

[0100] Figure 6 This is a schematic diagram of the structure of an optical signal receiving device provided for an exemplary embodiment. Figure 6 As shown, the photoelectric conversion sub-circuit 210 may include a photoelectric converter 211 and a transimpedance amplifier 212. The photoelectric converter 211, electrically connected to the transimpedance amplifier 212, is configured to convert the received optical signal into an initial electrical signal, which is a current signal. The transimpedance amplifier 212, electrically connected to the third signal processing sub-circuit 220, is configured to convert the initial electrical signal into a voltage signal and amplify it to generate a first electrical signal.

[0101] In an exemplary embodiment, the photoelectric converter can be PIN type, that is, formed by fabricating an intrinsic semiconductor layer between PN junctions, or it can be other structural forms that can realize photoelectric conversion. This disclosure does not specifically limit it.

[0102] In an exemplary embodiment, a transimpedance amplifier can convert a current signal from a photoelectric converter, photomultiplier tube, or similar current source into a voltage signal, which can then be displayed on a screen. Because transimpedance amplifiers are low-noise, high-gain converters, they are widely used as precise readout devices for Unity Quantum high-efficiency detectors, such as the QED-150 manufactured by UDT Instruments, for detector dark current characteristics, spectrometer readout interfaces, detector spectral calibration, high-gain precision transimpedance amplifiers, and as sensitive, high-precision optical power meters. The transimpedance amplifier has a total current range of ±20nA to ±20mA, a noise level of less than 1pA, and excellent dynamic range. The variable bias voltage range is from -14.00V to +14.00V.

[0103] In an exemplary embodiment, the optical signal receiving device may further include: a third power supply sub-circuit (not shown in the figure), which is electrically connected to the photoelectric conversion sub-circuit and the third signal processing sub-circuit, respectively, and is configured to provide a third power supply signal to the photoelectric conversion sub-circuit and the third signal processing sub-circuit.

[0104] In an exemplary embodiment, the voltage value of the third power supply signal can be 5V.

[0105] In an exemplary embodiment, the optical signal transmitting device includes: a control sub-circuit; and a third signal processing sub-circuit, further electrically connected to the control sub-circuit and configured to transmit a second electrical signal to the control sub-circuit. The transmission of the second electrical signal by the third signal processing sub-circuit to the control sub-circuit allows the control sub-circuit to adjust a first driving signal based on the second electrical signal, thereby providing real-time update compensation for the first driving signal.

[0106] In an exemplary embodiment, Figure 7 This is a schematic diagram of the clock reset sub-circuit. Figure 7 As shown, the third signal processing sub-circuit may include a clock reset sub-circuit. The clock reset sub-circuit includes a reset control chip 221.

[0107] In an exemplary implementation, such as Figure 7 As shown, the reset control chip 221 may include: active power pulse output pin CF1, reactive power pulse output pin CF2, positive analog input pin PIN, negative analog input pin PIN, first digital power supply pin VCC1, second digital power supply pin VCC2, first analog power supply pin AVCC1, second analog power supply pin AVCC2, positive digital output pin DATAOUTP, negative digital output pin DATAOUTN, positive clock output pin CLKOUTP, negative clock output pin CLKOUTN, digital ground pin VEE, and analog ground pin AVEE. Among them, the active power pulse output pin CF1 and the reactive power pulse output pin CF2 are electrically connected; the first digital power supply pin VCC1, the second digital power supply pin VCC2, the first analog power supply pin AVCC1 and the second analog power supply pin AVCC2 are electrically connected to the third power supply sub-circuit; the positive analog input pin PIN and the negative analog input pin PIN are electrically connected to the transimpedance amplifier; the positive digital output pin DATAOUTP, the negative digital output pin DATAOUTN, the positive clock output pin CLKOUTP and the negative clock output pin CLKOUTN are electrically connected to the control sub-circuit; and the digital ground pin VEE and the analog ground pin AVEE are grounded.

[0108] In an exemplary embodiment, the active power pulse output pin CF1 and the reactive power pulse output pin CF2 of the clock reset chip are electrically connected to form a frequency acquisition and control loop. The frequency acquisition and control loop is initially configured to acquire the frequency of the input data, and to acquire the frequency lock of random or scrambled data without requiring a preamble. During frequency locking, the frequency error is zero, which can improve the performance of the optical signal receiving device.

[0109] In an exemplary embodiment, the first digital power supply pin VCC1, the second digital power supply pin VCC2, the first analog power supply pin AVCC1, and the second analog power supply pin AVCC2 are electrically connected to form a phase acquisition control loop. The phase acquisition control loop is configured to acquire the phase of the input data so that the phase of the output data tracks the phase of the input data, which can improve the performance of the optical signal receiving device.

[0110] In an exemplary embodiment, the clock reset subcircuit may also employ a ring oscillator structure and low-noise design techniques. The low noise can stem from the use of a fully differential signal architecture, power supply rejection ratio (PSRR) circuitry, and dielectric isolation. The ring oscillator structure and low-noise design techniques enable the clock reset subcircuit to be immune to external signal interference, allowing the optical signal receiving device to withstand hundreds of millivolts of power supply noise without affecting performance.

[0111] In an exemplary implementation, such as Figure 7 As shown, the clock reset sub-circuit also includes an input processing sub-circuit 222 and an output processing sub-circuit 223. Figure 7 IN1 and IN2 refer to the input terminals of the clock reset sub-circuit, which are electrically connected to the transimpedance amplifier. DATA_N, DATA_P, CLK_N, and CLK_P refer to the output terminals of the clock reset sub-circuit, which are electrically connected to the control sub-circuit.

[0112] In an exemplary implementation, such as Figure 7As shown, the input processing sub-circuit 222 includes: first resistors R1 to fourth resistors R4 and first capacitors C1 to fourth capacitors C4, and the output processing sub-circuit 223 includes: fifth resistors R5 to sixteenth resistors R16 and fifth capacitors C5 to eighth capacitors C8. Specifically, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are electrically connected to the transimpedance amplifier. The second terminal of the first capacitor C1 is electrically connected to the positive analog input pin PIN and the first terminal of the fourth resistor R4, respectively. The second terminal of the second capacitor C2 is electrically connected to the first terminal of the first resistor R12 and the negative analog input pin PIN, respectively. The first terminal of the third capacitor C3 is electrically connected to the second terminals of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, respectively. The second terminals of the third capacitor C3 and the second resistor R2 are grounded. The first terminal of the fourth capacitor C4 is electrically connected to the active energy pulse output pin CF1 and the reactive energy pulse output pin CF2. The second terminal of the third resistor R3 is electrically connected to the third power supply signal Vcc of the third power supply sub-circuit. The first terminals of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 are electrically connected to the control sub-circuit. The second terminal of the fifth capacitor C5 is electrically connected to the first terminal of the fifth resistor R5 and the first terminal of the ninth resistor R9, respectively. The second terminal of the sixth capacitor C6 is electrically connected to the first terminal of the fifth resistor R5 and the first terminal of the ninth resistor R9, respectively. The first terminal of the sixth resistor R6 and the first terminal of the tenth resistor R10 are electrically connected. The second terminal of the seventh capacitor C7 is electrically connected to the first terminal of the seventh resistor R7 and the first terminal of the eleventh resistor R11. The second terminal of the eighth capacitor C8 is electrically connected to the first terminal of the eighth resistor R8 and the first terminal of the twelfth resistor R12. The second terminal of the fifth resistor R5 is electrically connected to the first terminal of the thirteenth resistor R13 and the negative digital output pin DATAOUTN. The second terminal of the sixth resistor R6 is electrically connected to the first terminal of the fourteenth resistor R14 and the positive digital output pin DATAOUTP. The second terminal of the seventh resistor R7 is electrically connected to the first terminal of the fifteenth resistor R15 and the negative clock output pin CLKOUTN, respectively. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the sixteenth resistor R16 and the positive clock output pin CLKOUTP, respectively. The second terminals of the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, and the sixteenth resistor R16 are grounded.

[0113] In an exemplary embodiment, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 can be equal and can be 100 nanofarads (nF), the capacitance value of the third capacitor C3 can be 2.2 microfarads (μF), the capacitance value of the fourth capacitor C4 can be 150 nanofarads (nF), and the capacitance values ​​of the fifth capacitor C5 to the eighth capacitor C8 can be the same and can be 100 nanofarads (nF).

[0114] In an exemplary embodiment, the resistance values ​​of the first resistor R1 and the fourth resistor R4 can be equal and can be 49.9 ohms, the resistance value of the second resistor R2 can be 360 ​​ohms, the resistance value of the third resistor R3 can be 300 ohms, the resistance values ​​of the fifth resistor R5 to the twelfth resistor R12 are equal and can be 100 ohms, and the resistance values ​​of the thirteenth resistor R13 to the sixteenth resistor R16 can be equal and can be 150 ohms.

[0115] Figure 8 This is a schematic diagram of the structure of an optical communication system provided in an embodiment of this disclosure. Figure 8 As shown in the embodiments of this disclosure, an optical communication system is also provided, which may include: an optical signal transmitting device 100 and / or an optical signal receiving device 200. Figure 8 The following description uses an example where the communication system may include an optical signal transmitting device 100 and an optical signal receiving device 200.

[0116] The optical signal transmitting device is the optical signal transmitting device provided in any of the foregoing embodiments, and the optical signal receiving device is the optical signal receiving device provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0117] In an exemplary embodiment, the drive backplane in the optical signal transmitting device and the photoelectric converter in the optical signal receiving device can be integrated on a single substrate. This allows the visible light communication device to not only receive optical signals but also transmit them, enabling bidirectional communication. This achieves true system integration, avoiding the problem of large and redundant optical communication systems. It also enables miniaturization, flexibility, ease of system deployment, space saving, and improved efficiency, while significantly reducing costs.

[0118] In an exemplary embodiment, the signal receiving end of the photoelectric converter and the light emitting side of the driving backplate can be parallel or at a certain angle.

[0119] In the exemplary embodiments, the optical communication system can be used in various application scenarios, and different optical signal transmitting devices and optical signal receiving devices are used for different application scenarios. This disclosure does not limit the scope of the application scenarios.

[0120] In an exemplary embodiment, the optical communication system may further include a signal processing device (not shown in the figure). The signal processing device is electrically connected to the optical signal transmitting device and is configured to filter the signal received by the optical signal transmitting device.

[0121] In an exemplary embodiment, the signal processing device can compensate for the amplitude and phase frequencies of the entire optical communication system, and can avoid signal distortion input to the optical signal transmitting device and avoid inter-symbol interference, thereby reducing the bit error rate of the optical communication system and improving the reliability of the optical communication system.

[0122] In an exemplary embodiment, the signal processing device may be a filter.

[0123] In an exemplary embodiment, in order to enable impedance matching between a signal of any frequency and the signal processing device, the forward transmission gain of the signal processing device can be made to approach 1, thereby greatly increasing the bandwidth of the signal output by the optical signal receiving device.

[0124] This disclosure also provides an optical communication method applied in an optical signal transmitting device. The optical communication method may include the following steps:

[0125] Step S11: Generate the first drive signal.

[0126] Step S12: Generate a second driving signal based on the first driving signal.

[0127] Step S13: Process the signal swing of the second driving signal to generate the third driving signal, and generate the light-emitting driving signal based on the third driving signal.

[0128] Step S14: Emit a light signal according to the light emission driving signal.

[0129] The optical signal transmitting device is the optical signal transmitting device provided in any of the foregoing embodiments, and the implementation principle and effect are similar, so it will not be described again here.

[0130] This disclosure also provides an optical communication method applied to an optical signal receiving device. The optical communication method may include the following steps:

[0131] Step S21: Receive the optical signal and convert the received optical signal into a first electrical signal.

[0132] In an exemplary embodiment, the first electrical signal may be an analog signal and a differential signal;

[0133] Step S22: Convert the first electrical signal into a second electrical signal.

[0134] In an exemplary embodiment, the second electrical signal may be a digital signal and includes a clock signal.

[0135] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0136] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0137] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0138] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. An optical communication system, characterized in that, include: Optical signal transmitting device and optical signal receiving device; The optical signal transmitting device includes: a control circuit and a driving backplane; the control circuit includes: a control sub-circuit, a first signal processing sub-circuit and a second signal processing sub-circuit, and the driving backplane includes multiple light-emitting device units; The control sub-circuit is configured to generate a first drive signal, wherein the first drive signal is a digital signal; The first signal processing sub-circuit is electrically connected to the control sub-circuit and is configured to generate a second drive signal based on a first drive signal; the first signal processing sub-circuit includes an amplification sub-circuit, and the second drive signal is an analog signal. The second signal processing sub-circuit includes: an attenuation sub-circuit and an AC / DC coupling sub-circuit; The attenuation sub-circuit, electrically connected to the amplification sub-circuit of the first signal processing sub-circuit, is configured to process the signal swing of the second driving signal to generate a third driving signal, which is an analog signal and an AC signal. The attenuation sub-circuit includes: a first attenuation resistor, a second attenuation resistor, a third attenuation resistor, an attenuation capacitor, and a second operational amplifier. The first terminal of the attenuation capacitor is electrically connected to the amplification sub-circuit, and the second terminal of the attenuation capacitor is electrically connected to the first terminal of the first attenuation resistor. The second terminal of the first attenuation resistor is electrically connected to both the inverting input terminal of the second operational amplifier and the first terminal of the second attenuation resistor. The second terminal of the second attenuation resistor is electrically connected to the output terminal of the second operational amplifier. The first terminal of the third attenuation resistor is electrically connected to the non-inverting input terminal of the second operational amplifier, and the second terminal of the third attenuation resistor is electrically connected to either the first power supply sub-circuit or the second power supply sub-circuit. The resistance value of the third attenuation resistor is equal to the ratio of the resistance value of the first attenuation resistor to the resistance value of the second attenuation resistor. The AC / DC coupling sub-circuit, electrically connected to the attenuation sub-circuit, is configured to generate a light-emitting driving signal based on a third driving signal. The AC / DC coupling sub-circuit includes a bias sub-circuit; the bias sub-circuit includes a bias capacitor and a bias oscillator; the first terminal of the bias capacitor serves as an AC input terminal and is electrically connected to the attenuation sub-circuit; the second terminal of the bias capacitor serves as an output terminal and is electrically connected to the first terminal of the bias oscillator; the second terminal of the bias oscillator serves as a DC input terminal and is electrically connected to a third power supply signal, which is a DC current signal. The driving backplane is electrically connected to the second signal processing sub-circuit and is configured to emit a light signal according to the light emission driving signal; The optical signal receiving device includes: a photoelectric conversion sub-circuit and a third signal processing sub-circuit; The photoelectric conversion sub-circuit is configured to receive an optical signal and convert the received optical signal into a first electrical signal, wherein the first electrical signal is an analog signal and is a differential signal; The third signal processing sub-circuit is electrically connected to the photoelectric conversion sub-circuit and is configured to convert the first electrical signal into a second electrical signal, wherein the second electrical signal is a digital signal and includes a clock signal. The third signal processing sub-circuit includes a clock reset sub-circuit, which includes a reset control chip. The reset control chip includes an active energy pulse output pin and a reactive energy pulse output pin. The active energy pulse output pin and the reactive energy pulse output pin are electrically connected to form a frequency acquisition and control loop.

2. The system according to claim 1, characterized in that, The first signal processing sub-circuit further includes: a digital-to-analog converter sub-circuit; The digital-to-analog converter sub-circuit is electrically connected to the control sub-circuit and is configured to convert the first drive signal into a digital-to-analog signal to form a first analog drive signal. The amplification sub-circuit is electrically connected to the digital-to-analog conversion sub-circuit and is configured to amplify the first analog drive signal to generate the second drive signal. The light-emitting driving signal is an analog signal.

3. The system according to claim 2, characterized in that, Also includes: First power supply sub-circuit and second power supply sub-circuit; The first power supply sub-circuit is electrically connected to the control sub-circuit, the digital-to-analog converter sub-circuit, the amplifier sub-circuit, the attenuation sub-circuit, the AC / DC coupling sub-circuit, and the drive backplane, and is configured to provide a first power signal. The second power supply sub-circuit is electrically connected to the DC input terminal of the AC / DC coupling sub-circuit and is configured to provide a second power supply signal, wherein the first power supply signal and the second power supply signal are DC current signals.

4. The system according to claim 3, characterized in that, The digital-to-analog conversion sub-circuit includes a digital-to-analog converter, and the amplification sub-circuit includes a first operational amplifier.

5. The system according to any one of claims 2 to 4, characterized in that, The driving backplane further includes a driving circuit configured to drive the light-emitting device unit to emit light, the driving circuit including a first light-emitting resistor, a second light-emitting resistor, a third light-emitting resistor, a light-emitting capacitor, and a light-emitting transistor; the light-emitting device unit includes a first electrode and a second electrode; The first power supply sub-circuit is electrically connected to the first electrode of the light-emitting device unit and the first terminal of the second light-emitting resistor, respectively. The second electrode of the light-emitting device unit is electrically connected to the first electrode of the light-emitting transistor. The control electrode of the light-emitting transistor is electrically connected to the AC / DC coupling sub-circuit, the first terminal of the first light-emitting resistor, and the second terminal of the second light-emitting resistor, respectively. The second electrode of the light-emitting transistor is electrically connected to the first terminal of the third light-emitting resistor and the first terminal of the light-emitting capacitor, respectively. The second terminals of the first light-emitting resistor, the third light-emitting resistor, and the light-emitting capacitor are grounded. The light-emitting transistor is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor.

6. The system according to claim 1, characterized in that, Also includes: The third power supply sub-circuit, which is electrically connected to the photoelectric conversion sub-circuit and the third signal processing sub-circuit respectively, is configured to provide a third power supply signal.

7. The system according to claim 6, characterized in that, The photoelectric conversion sub-circuit includes: a photoelectric converter and a transimpedance amplifier; The photoelectric converter, electrically connected to the transimpedance amplifier, is configured to convert the received optical signal into an initial electrical signal, wherein the initial electrical signal is a current signal. The transimpedance amplifier, electrically connected to the third signal processing sub-circuit, is configured to convert the initial electrical signal into a voltage signal and amplify it to generate the first electrical signal.

8. The system according to claim 7, characterized in that, The optical signal transmitting device includes: a control sub-circuit; The third signal processing sub-circuit is also electrically connected to the control sub-circuit and is configured to transmit the second electrical signal to the control sub-circuit.

9. The system according to claim 8, characterized in that, The reset control chip further includes: a positive analog input pin, a negative analog input pin, a first digital power supply pin, a second digital power supply pin, a first analog power supply pin, a second analog power supply pin, a positive digital output pin, a negative digital output pin, a positive clock output pin, a negative clock output pin, a digital ground pin, and an analog ground pin; wherein, the first digital power supply pin, the second digital power supply pin, the first analog power supply pin, and the second analog power supply pin are electrically connected to the third power supply sub-circuit; the positive analog input pin and the negative analog input pin are electrically connected to the transimpedance amplifier; the positive digital output pin, the negative digital output pin, the positive clock output pin, and the negative clock output pin are electrically connected to the control sub-circuit; and the digital ground pin and the analog ground pin are grounded.

10. The system according to claim 9, characterized in that, The clock reset sub-circuit further includes an input processing sub-circuit and an output processing sub-circuit. The input processing sub-circuit includes a first resistor to a fourth resistor and a first capacitor to a fourth capacitor. The output processing sub-circuit includes a fifth resistor to a sixteenth resistor and a fifth capacitor to an eighth capacitor. The first terminal of the first capacitor and the first terminal of the second capacitor are electrically connected to the transimpedance amplifier. The second terminal of the first capacitor is electrically connected to the positive analog input pin and the first terminal of the fourth resistor, respectively. The second terminal of the second capacitor is electrically connected to the first terminal of the first resistor and the negative analog input pin, respectively. The first terminal of the third capacitor is electrically connected to the second terminals of the first resistor, the second resistor, the third resistor, and the fourth resistor, respectively. The second terminals of the third capacitor and the second resistor are grounded. The first terminal of the fourth capacitor is electrically connected to the active power pulse output pin, and the second terminal of the fourth capacitor is electrically connected to the reactive power pulse output pin. The second terminal of the third resistor is electrically connected to the third power supply sub-circuit. The first terminals of the fifth, sixth, seventh, and eighth capacitors are electrically connected to the control sub-circuit. The second terminal of the fifth capacitor is electrically connected to the first terminals of the fifth and ninth resistors, respectively. The second terminal of the sixth capacitor is electrically connected to the first terminals of the sixth and tenth resistors, respectively. The second terminal of the seventh capacitor is electrically connected to the first terminals of the seventh and eleventh resistors, respectively. The second terminal of the eighth capacitor is electrically connected to the first terminals of the eighth and twelfth resistors, respectively. The second terminal of the fifth resistor is electrically connected to the first terminal of the thirteenth resistor and the negative digital output pin, respectively. The second terminal of the sixth resistor is electrically connected to the first terminal of the fourteenth resistor and the positive digital output pin, respectively. The second terminal of the seventh resistor is electrically connected to the first terminal of the fifteenth resistor and the negative clock output pin, respectively. The second terminal of the eighth resistor is electrically connected to the first terminal of the sixteenth resistor and the positive clock output pin, respectively. The second terminals of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth resistors are grounded.

11. The system according to claim 1, characterized in that, Also includes: Signal processing device; The signal processing device is electrically connected to the optical signal transmitting device and is configured to filter the signal received by the optical signal transmitting device.

12. An optical communication method, characterized in that, Applied to the optical communication system as described in any one of claims 1 to 11, wherein the process of emitting an optical signal includes: Generate the first drive signal; A second drive signal is generated based on the first drive signal; The signal swing of the second driving signal is processed to generate a third driving signal, and a light-emitting driving signal is generated based on the third driving signal. A light signal is emitted according to the light emission driving signal; The process of receiving optical signals includes: The system receives optical signals and converts the received optical signals into a first electrical signal, wherein the first electrical signal is an analog signal and is a differential signal; The first electrical signal is converted into a second electrical signal, the second electrical signal being a digital signal and including a clock signal.

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