Physically unclonable function device

Abstract

Embodiments of the present disclosure relate to physically unclonable functional devices. In one embodiment, an integrated device includes a first physically unclonable function module configured to generate an initial data set and a management module configured to generate an output data set from at least the initial data set; authorize only D consecutive transfers of the output data set on a first output interface of the device, D being a non-zero positive integer; and prevent any new generation of the output data set.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of French Patent Application No. 2107580, filed July 13, 2021, which is incorporated by reference herein. TECHNICAL FIELD

[0003] Embodiments of the invention relate to physical unclonable functions (PUF), and more particularly to physical unclonable functions executed within an integrated circuit. BACKGROUND

[0004] A physical unclonable function automatically generates a unique, unpredictable code that is related to random or partially random physical features of the physical unclonable function. These physical features can be caused by variations during manufacturing of the physical unclonable function.

[0005] Thus, cloning such a function is very difficult, if not impossible.

[0006] Furthermore, the content of the generated code is unique, in that it differs from a physical unclonable function and another physical unclonable function, and thus cannot be predicted and can be related to, for example, a particular configuration of components during functional power-up. Thus, for example, a physical unclonable function can be executed by a non-volatile memory that, upon power-up, has a content related to partially random physical features of the memory, these manufacturing variations leading to different physical features for different memories. SUMMARY

[0007] Embodiments provide random variations in physical features that are easy to identify, to clearly distinguish between different data.

[0008] Further embodiments provide that implementation of the physical unclonable function requires little or no dedicated manufacturing steps.

[0009] The unique, unpredictable code generally comprises a random sequence of data and is primarily used as an encryption key. This data is generally secret.

[0010] The physical unclonable function can be executed using, for example, a random access or non-volatile memory, or a ring oscillator or other specific logic circuit.

[0011] However, these devices of the prior art can be more or less easily detected within an integrated circuit in certain cases, or are sensitive to attacks by fault injection, or to adverse surface bodies.

[0012] The embodiments provide an enhancement of the security of a physically unclonable function structure, in particular proposing that the data of the physically unclonable function structure is clearly distinguishable in a read mode, while being difficult to extract by an attack from a third party.

[0013] The structure provided by the embodiments is easy to produce in the state of the art and has a non-disadvantageous surface body.

[0014] According to one embodiment, a physically unclonable function device is provided, the physically unclonable function device being used only a predetermined number of times, the device becoming inoperative after this number is reached.

[0015] One possible, but not exclusive, application of such a device is for example to limit the number of possible pairings between a device (for example a printer) and an object (for example an ink cartridge).

[0016] According to another embodiment, a physically unclonable function device is provided, the physically unclonable function device being able to deliver both a unique unpredictable code (for example usable as an encryption / decryption key) a predetermined number of times and another unique unpredictable code that can be used for example as an encryption key an unlimited number of times.

[0017] According to this other embodiment, therefore, a physically unclonable function device is provided, the physically unclonable function device being able to provide for example a first key for limited use and a second key for unlimited use.

[0018] According to one aspect, an integrated physically unclonable function device is provided, comprising: a first physically unclonable function module configured inside the device to generate an initial data set; and a management means configured inside the device to generate an output data set from at least the initial data set, to authorize only D successive deliveries of the output data set on a first output interface of the device (i.e. outside the device), D being a non-zero positive integer number, and to prevent any new generation of the output data set.

[0019] The output data set, i.e. the unique unpredictable code forming for example a first key for limited use, can be for example the initial data set generated by the first module or obtained for example by a combination of this initial data set and additional data, the additional data itself being generated by a second physically unclonable function module.

[0020] The number D is determined for example by the number of uses of the device under test and by the number of operational uses of the device by the end user.

[0021] Moreover, the first physically unclonable function module and the management means are inside the integrated device, which makes the integrated device autonomous without the need to receive external data to deliver the output data set, i.e. the unique unpredictable code.

[0022] This makes the device more robust.

[0023] According to one embodiment, the managing device is configured to prevent any new generation of the output data set by preventing any new generation of the initial data set.

[0024] According to one embodiment, the first module comprises a first set of non-volatile storage cells, each non-volatile storage cell having a select transistor buried in a semiconductor substrate and a depletion-mode state transistor having a control gate and a floating gate, the state transistor having a respective effective threshold voltage belonging to a common random distribution, and a reading device configured to deliver the initial data set from a reading of the effective threshold voltages of the state transistors of the storage cells of said first set.

[0025] This type of non-volatile storage cell with a buried select transistor has a particularly compact structure. It is described in detail, for example, in patent application US 2013 / 0 228 846.

[0026] The storage cells of the first set can be read by applying zero voltage to the control gate, for example by connecting this control gate to ground, since the state transistors are normally on.

[0027] Furthermore, the state transistors are depletion-mode, the on characteristic of the state transistor ("normally on") being related to the threshold voltage value in the original state of the storage cell when it is, for example, in the original state and zero voltage is applied to the control gate, the threshold voltage value being, for example, chosen to be negative or substantially zero.

[0028] As an indication, this threshold voltage can be of the order of -1 volt.

[0029] The state transistors of all the storage cells in the first set have the same theoretical threshold voltage. However, the effective threshold voltage, i.e. the actual value of the threshold voltage, varies slightly depending on random differences (for example due to physical manufacturing distortions).

[0030] And, the common random distribution is advantageously the distribution of the effective threshold voltages of the state transistors of the original storage cells that have not been written.

[0031] According to one embodiment, the first set of non-volatile storage cells is organized in a first and a second matrix sub-set arranged symmetrically with respect to the reading device, all the lines of the first and second matrix sub-sets being parallel, and the reading device is configured to perform said reading comprising a differential reading of the effective threshold voltages of the state transistors of a pair of symmetric storage cells, and the pair of symmetric storage cells being respectively located on homologous columns of the first and second sub-sets in the first and second sub-sets.

[0032] The two homologous columns of the first and second sub-sets are understood to be columns having the same column address.

[0033] The distribution of the first set into two subsets of symmetric matrices associated with the differential method at the time of reading is particularly advantageous in the sense of a difference within a common random distribution that allows increasing the effective threshold voltage of the state transistor.

[0034] According to one embodiment, the management means are configured to program or erase the memory cells of one of the two subsets after reading the initial data set, in order to prevent any new generation of the initial data set.

[0035] Indeed, any new differential reading of the memory cells of the first set will provide a constant value, which is of course different from the generated initial data set.

[0036] Here, the source of entropy at the source of generation of the initial data set is thus destroyed.

[0037] According to one embodiment, the initial data set comprises G initial data, and the management means comprise a non-volatile memory device comprising a memory plane with D memory regions, each configured to store a piece of information comprising N consecutive data with G initial data, N being greater than or equal to G, and the first processing means are configured to extract N data consecutively from the D memory regions of the memory device and to destroy at least part of the content of the corresponding memory region during the extraction of the N corresponding data.

[0038] The D memory regions each containing an initial data set, which is a random sequence of data, will allow D successive passes of the output data set outside the device.

[0039] Moreover, it is possible to store only the initial data set in each memory region. In this case, N is equal to G, and the N consecutive data stored in each memory region are exactly the G consecutive initial data.

[0040] In this case, it is possible to provide N greater than G. In this case, for example, the G initial data are completed by N-G dummy bits each having for example the value 1, to obtain the N consecutive data stored in the memory region.

[0041] Each memory region advantageously also comprises non-volatile memory cells with buried select transistors.

[0042] More particularly, according to one embodiment, each memory region comprises a matrix of memory cells with two rows and N columns.

[0043] Each memory cell comprises a state transistor with a control gate and a floating gate, which can be selected by a vertical select transistor buried in the substrate and comprising a buried select gate.

[0044] Each memory cell column comprises a pair of twin memory cells.

[0045] When the two selection transistors of the pair of memory cells have a common selection gate, the two memory cells are said to be twins.

[0046] The first processing means are configured to store, in a memory area, said piece of information comprising N consecutive bits.

[0047] The storage of said piece of information is advantageously performed so that, except for the last consecutive bit, the current bit of said consecutive bits is stored in two memory cells located on the same row and on two adjacent columns, and the current bit and the next bit are respectively stored in two twin cells.

[0048] Such a twin cell structure combined with this filling of the memory area of the checkerboard type and the redundant storage of the current bit in two memory cells leads to a robust storage of the piece of information and makes it difficult to recover the correct values of the bits of the piece of information, and thus of the initial data group, in particular using a conventional method for reading these memory cells.

[0049] In this regard, to ensure a correct reading of the bits, the first processing means are advantageously configured, to be able to read the bits stored in the first twin cell, to first replace the bits stored in the second twin cell with reference bits having reference values chosen to allow a correct recovery of the values of the bits stored in the first twin cell. This reference value is for example the logical value 0 corresponding to the programmed state of the twin memory cells.

[0050] Indeed, since the two twin cells are simultaneously selected, the value of the bits stored in the second twin cell must not be able to "mask" (for example if this value is equal to 1) the value of the bits stored in the first twin cell.

[0051] Furthermore, the first processing means are also advantageously configured to read the N bits of the piece of information sequentially and, for each bit consecutive except the last one, to replace the current bit of said piece of information that has been read with a reference bit before being able to read said consecutive next bit.

[0052] Such a reading using a reference bit to replace each bit that has been read before being able to read the next bit of the piece of information is equivalent to "destroying" these bits when reading them except the last one, and thus makes it impossible to recover the stored piece of information, and thus the initial data group.

[0053] Each memory area can thus only be read once to deliver the stored piece of information only once.

[0054] Thus, the D memory areas will authorize only D recoveries of the initial data set and thus D passes of the unique unpredictable code.

[0055] According to one embodiment, the memory area comprises a single bit line connected to the drain of the state transistor of each pair of twin cells of the corresponding column, and a gate control line connected to all the control gates of the state transistors of the storage cells of the corresponding row.

[0056] According to one embodiment, the first processing means comprise a column decoder configured to select two bit lines associated with two columns located at the two ends of the memory area separately, and to select two adjacent bit lines simultaneously, for the operations of storing information and of pre-reading and replacing bits.

[0057] Such a non-limiting example of column decoder allows to implement the specific storage and reading described above.

[0058] The storage cells of the memory area are cells having one bit line per column, while the other storage cells of the device are storage cells having two bit lines per column.

[0059] While it is possible to provide a separate column decoder for each type of architecture (unit line or double bit line), it is particularly advantageous to provide a single column decoder structure compatible with both architectures. This will be explained in more detail below.

[0060] In a first variant, the output data set, i.e. the unique, unpredictable, limited use code passed by the physically unclonable function device, can simply comprise N bits of said piece of information stored in the memory area.

[0061] However, in order to make the device more robust against attacks, the N bits of the piece of information stored in each memory area can be combined with an additional data set generated by a second physically unclonable function module.

[0062] Thus, according to another variant, the management means comprise a second physically unclonable function module configured to generate an additional data set, and development means configured to develop the output data set from at least the initial data set and at least the additional data set.

[0063] However, this additional data set can also be used alone as a unique unpredictable code, for example as an encryption / decryption key.

[0064] The device is then able to pass the first unpredictable unique code (output data set) D times and to pass the second unpredictable unique code (additional data set) a very large, unlimited number of times.

[0065] More specifically, according to one embodiment, the management device is configured to deliver an additional set of data on a second output interface of the device, which can be the same or different from the first output interface.

[0066] According to one embodiment, the second physically unclonable function module comprises a second set of non-volatile storage cells each having a select transistor buried in a semiconductor substrate and a depletion-mode transistor having a control gate and a floating gate electrically connected, the state transistor having a respective effective threshold voltage belonging to a common random distribution; and a second processing device configured to deliver an additional set of data from a reading of the effective threshold voltage of the state transistor of the storage cells of said second set.

[0067] The non-volatile storage cells of the second set having a buried select transistor can be of the type described in patent application US 2013 / 0228 846.

[0068] However, here, the state transistor of the storage cells of the second set can be depletion-mode and have a control gate and a floating gate electrically connected, in contrast to these conventional cells.

[0069] These features are particularly advantageous because for the storage cells of the first set, i.e. the storage cells of the first physically unclonable function module, it is then possible to read the storage cells of the second set by applying a zero voltage on the control gate, for example by grounding this control gate, since the state transistor is generally in the on state.

[0070] Moreover, since the reading voltage on the control gate is zero, no stress is induced in the gate dielectric during reading ("read stress"), which can significantly reduce or even eliminate the risk of occurrence of a phenomenon known to those skilled in the art, termed "read disturbance", which can lead to a modification of the logical value of the stored bit.

[0071] This is particularly advantageous for those storage cells which can be read many times.

[0072] Moreover, the state transistor being depletion-mode, when the storage cell is for example in the original state and a zero voltage is applied to the control gate, the on characteristic of the state transistor ("normally on") is related to the threshold voltage value in the original state of this storage cell, which can for example be chosen to be negative or substantially zero.

[0073] As an indication, this threshold voltage can be of the order of -1 volt.

[0074] Likewise, the state transistor of all the storage cells has the same theoretical threshold voltage. However, the effective threshold voltage, i.e. the actual value of the threshold voltage, varies slightly depending on random differences, for example due to physical manufacturing distortions.

[0075] However, since the control gate and the floating gate of the state transistor are electrically connected, the state transistor intrinsically has a greater variability to resist these distortions and therefore a wider distribution than other types of electronic components, such as MOS transistors or resistors.

[0076] Thus, these cells of the second set provide a very wide difference in effective threshold voltage.

[0077] The difference obtained from the effective threshold voltage is for example equal to -1 volt plus or minus 100%.

[0078] And, advantageously, the common random distribution is that of the connection state, the floating gate and the effective threshold voltage of the control transistor of the blank memory cells not written.

[0079] Advantageously, each memory cell of the second set comprises a gate oxide provided between the floating gate and the substrate of the state transistor, the thickness of which is greater than 8 nanometers, for example comprised between 8 and 10 nanometers.

[0080] This thick gate oxide allows to obtain a good robustness of the physically unclonable second functional module against aging.

[0081] According to one embodiment, the second processing means comprise second reading means configured to perform said reading of the effective threshold voltage of the state transistor and the second set of non-volatile memory cells is organized in two second matrix subsets provided symmetrically with respect to the reading means, all the lines or rows of the two second matrix subsets being parallel.

[0082] Moreover, the second reading means are configured to perform said reading which then comprises a differential reading of the effective threshold voltage of the state transistor of a pair of symmetric memory cells and the pair of symmetric memory cells is respectively located on homologous columns of the two second subsets.

[0083] Again, the two homologous columns of the two second subsets are understood as columns having the same column address.

[0084] In a similar way to that indicated for the first set, the distribution of the second set into the two symmetric matrix subsets associated with the differential method at the time of reading is particularly advantageous in the sense that it allows to increase the difference within the common random distribution of the effective threshold voltage of the state transistor.

[0085] Further particularly preferably, the reliability of the memory cells of the second set is ensured so as to retain, for the transmission of the additional data group, only the pairs of memory cells of the second set whose content is reliable, i.e. not liable to vary from one power-up to another.

[0086] Furthermore, according to one embodiment, the second processing means advantageously comprise a third set of memory cells, each memory cell having a select transistor buried in a semiconductor substrate and a state transistor having a control gate and a floating gate, the memory cells of the third set being intended to contain a piece of reliability information representative of the reliability or of the non-reliability of the content of a pair of memory cells of the second set.

[0087] Unlike the memory cells of the second set, the memory cells of the third set intended to contain a piece of reliability information do not comprise a state transistor whose floating gate and whose control gate are electrically connected. On the other hand, these state transistors are also advantageously of the depletion type.

[0088] Thus, just as the memory cells of the second set can be read by applying a zero voltage to the control gate, for example by grounding this control gate, as illustrated above, since the state transistors are generally conductive, the memory cells of the third set can also be read by applying a zero voltage to the control gate, since the state transistors of such cells are also advantageously generally conductive.

[0089] In other words, the memory cells of the third set are conventional memory cells having a state transistor and a buried select transistor, such as those of the type described in the above-mentioned US patent application, but with, for example, arsenic implanted channel regions to obtain depletion type transistors.

[0090] According to one embodiment, the third set comprises a matrix arrangement of memory cells sharing the same columns as the matrix arrangement of memory cells of the second set.

[0091] This thus facilitates decoding, since the second set and the third set then share the same column decoding.

[0092] Furthermore, it is further advantageous for the third set to also comprise two third subsets distributed respectively on either side of the second subset.

[0093] Furthermore, the piece of reliability information associated with a pair of memory cells is stored in a memory cell of the third set on the same column as the corresponding pair of memory cells of the second set on which the column is located.

[0094] This symmetrical storage on either side of the second subset of the piece of reliability information allows easier reading.

[0095] According to one embodiment, the second processing means comprise first generating means configured to generate said piece of reliability information by considering a margin value of the differential reading of the effective threshold voltage of the state transistors of a pair of memory cells of the second set.

[0096] According to one embodiment, the second processing means comprise second generating means configured to generate said additional data set from at least the differential reading of the effective threshold voltage of the state transistors of the pairs of storage cells of the second set and from said pieces of reliability information of these pairs of storage cells.

[0097] As mentioned above, according to one embodiment, the first set of storage cells, the second set of storage cells and the third set of storage cells each have an architecture comprising two bit lines per column of storage cells.

[0098] In other words, the columns of storage cells comprise pairs of twin storage cells, the two selection transistors of which have a common selection gate, two adjacent twin storage cells of the same column not being connected to the same bit line and two adjacent non-twin storage cells of the same column being connected to the same bit line.

[0099] According to one embodiment, some columns of the non-volatile memory device, comprising D memory regions, are common to some columns of the first set, the second set and the third set.

[0100] The management means then advantageously comprise a single column decoder configured to individually select the two bit lines associated with the two columns located at the two ends of each memory region and to simultaneously select the two adjacent bit lines of each memory region and the bit lines of the first, second and third sets common to one of these two adjacent bit lines, and to individually select the other bit lines of the first, second and third sets.

[0101] As mentioned above, such a column decoder structure is compatible with an architecture of one bit line per column of the non-volatile memory device and with an architecture of two bit lines per column of the sets of storage cells of the first and second physically unclonable function modules.

[0102] According to another aspect, there is provided a method for automatically generating a unique unpredictable code at said first output interface of a physically unclonable function device as defined above, the method comprising a power-up of the device and at least one reading of a memory region of the non-volatile memory device.

[0103] According to one embodiment, the method further comprises reading the effective threshold voltage of the state transistors of the storage cells of said second set, the control gates of the state transistors of these storage cells being grounded during said reading, and developing a unique unpredictable code from the content of the read memory region and from the additional data set obtained from said reading.

[0104] According to another aspect, there is provided a method for producing a physically unclonable function device as defined above, the method comprising producing the device within an integrated circuit and, at a test stage of the integrated circuit,

[0105] - generating an initial data set,

[0106] - storing said pieces of information of N data in D memory areas,

[0107] - programming or erasing part of the memory cells of the first set after the initial data set is generated,

[0108] - generating and storing a piece of reliability information. BRIEF DESCRIPTION OF DRAWINGS

[0109] Other advantages and features of the present application will become apparent from the detailed description of non-limiting implementations and embodiments, and from the drawings, wherein:

[0110] Figure 1 An integrated circuit device is shown;

[0111] Figure 2 A method of manufacturing an integrated circuit device is shown;

[0112] Figure 3 A method for generating a code is described according to one embodiment;

[0113] Figure 4 A method of using an integrated device is illustrated according to one embodiment;

[0114] Figure 5 A split-gate type non-volatile memory cell is illustrated;

[0115] Figure 6 Two twin cells according to one embodiment are illustrated;

[0116] Figure 7 A memory plane structure with a single bit line per column is illustrated;

[0117] Figure 8 A memory plane and structure of twin memory cells referred to as double bit lines is illustrated;

[0118] Figure 9 A set of non-volatile memory cells organized in two subsets of matrices according to one embodiment is shown;

[0119] Figure 10 A reading device configured to perform a differential read is described;

[0120] Figure 11 A method for breaking a code is shown;

[0121] Figure 12 Two twin cells according to another embodiment are illustrated;

[0122] Figure 13Different threshold voltages corresponding to erased, blank, and programmed memory cells are schematically shown;

[0123] Figure 14 A column decoder configured to individually select two bit lines associated with two columns located at the two ends of a memory region is illustrated;

[0124] Figure 15 All memory cells of a memory region are in an erased state before storing a piece of information in the memory region is illustrated;

[0125] Figure 16 A column decoder configured to select two bit lines according to one embodiment is illustrated;

[0126] Figure 17 A column decoder configured to select two bit lines according to another embodiment is illustrated;

[0127] Figure 18 A column decoder configured to select two bit lines according to yet another embodiment is illustrated;

[0128] Figure 19 A checkerboard fill of a memory region at the end of a write operation is illustrated;

[0129] Figure 20 Replacing stored values in twin cells before reading a cell is illustrated;

[0130] Figure 21 Reading of two twin cells according to one embodiment is illustrated;

[0131] Figure 22 Correct recovery of logical values of data is illustrated;

[0132] Figure 23 Selection of two bit lines according to one embodiment is illustrated;

[0133] Figure 24 Programming a cell before reading is shown;

[0134] Figure 25 Reading a cell is shown;

[0135] Figure 26 Programming twin cells is shown;

[0136] Figure 27 Reading a cell is shown;

[0137] Figure 28 A second processing device including a third set of memory cells is shown;

[0138] Figure 29The third set of cells is shown to comprise state transistors having a control gate and a floating gate;

[0139] Figure 30 A second set of non-volatile storage cells is shown;

[0140] Figure 31 A reading device is illustrated, the reading device being configured to perform a differential reading with a margin value;

[0141] Figure 32 A reading device is illustrated, the reading device being configured to perform a differential reading with a margin value;

[0142] Figure 33 Another reading device is shown, the reading device being configured to perform a differential reading;

[0143] Figure 34 An example of a structure of a first generating device configured to generate a piece of reliability information is described;

[0144] Figure 35 An example of a structure of a second generating device configured to generate a code is described;

[0145] Figure 36 A third set of storage cells configured to store a piece of reliability information is illustrated;

[0146] Figure 37 The metallization is shown in relation to the BL; and

[0147] Figure 38 Columns of memory planes of a memory region are shown. DETAILED DESCRIPTION

[0148] Before returning in more details to the various components of the physically unclonable function device, reference will be made to Figures 1-4 The overall architecture and an example of operation are described.

[0149] In Figure 1 The reference DIS denotes an integrated device having a physically unclonable function, advantageously produced entirely within a single integrated circuit IC.

[0150] The device DIS comprises a first physically unclonable function module MPF1 inside the device DIS, configured to generate an initial data group RD2, the initial data group RD2 being generally a random binary data sequence forming a unique unpredictable initial code.

[0151] As will be seen in more details below, the first module MPF1 comprises a first set of storage cells 1 intended to generate the initial code RD2.

[0152] The device DIS also comprises a management device MGST inside the device DIS, the management device MGST being configured to generate an output data set HUK2 from at least the initial data set RD2; to authorize only D successive transfers of the output data set HUK2 on a first output interface INST1 of the device, D being a non-zero positive integer; and to prevent any new generation of the output data set HUK2.

[0153] The output data set HUK2 forms a first unpredictable unique code, which can for example be used as an encryption / decryption key.

[0154] This first code HUK2 is thus limited in use, since it can only be transferred D times.

[0155] As will be seen in more detail hereafter, the management device is configured to prevent any new generation of the output data set HUK2 by preventing any new generation of the initial data set RD2.

[0156] The management device MGST comprises a non-volatile memory device DM having a memory plane comprising D memory areas ZM1-ZMD.

[0157] Each memory area is able to store N bits.

[0158] In the example described here, it is assumed that the initial data set RD2 also comprises N bits.

[0159] As mentioned above, in the case where the set RD2 comprises G bits and G is less than N, the G bits can be completed with N-G virtual bits.

[0160] Each memory area ZMi is thus configured here to store N successive data of the initial code RD2.

[0161] And as will be seen in more detail hereafter, the memory device DM comprises first processing means (not shown in this figure) configured to successively extract N data of the code RD2 from the D memory areas of the memory device, and to at least destroy part of the content of the corresponding memory area during the extraction of the N corresponding data. Figure 1

[0162] Although the first unpredictable unique code HUK2 can be the initial code RD2, it is preferred to improve the robustness of the device DIS against attacks from malicious third parties to combine the initial code RD2 with an additional data set to form a second unpredictable unique code HUK1.

[0163] In this regard, the management device MGST comprises development means MLB, for example a logic circuit of the XOR type, to develop the first code HUK2 from the initial code RD2 and from the second code HUK1.

[0164] ​The management device MGST also comprises a second physical unclonable function module MPF2 configured to generate a second code HUK1.

[0165] As will be seen in more detail hereafter, the second module comprises a second set of storage units 2 intended to use the piece of reliability information MSK contained in the third set of storage units 3 to generate the code HUK1.

[0166] The second module MPF2 can also deliver the second code HUK1 on a second output interface INTS2 of the device, which can be the first output interface INTS1 or a different output interface.

[0167] The second code HUK1 can for example be used as an encryption / decryption key.

[0168] The second code HUK1 can be an infinite code.

[0169] Manufacture and use of a physical unclonable function device

[0170] Reference will now be made more particularly to Figure 2 to illustrate an example of a method for manufacturing Figure 1 a device, thus allowing its use.

[0171] Figure 2 The steps mentioned in the above summary are overall steps, some of which will be explained in more detail hereafter.

[0172] These steps are part of a first phase PHI, which is generally a test phase of the acronym EWS ("electronic wafer sort") known to those skilled in the art.

[0173] Once the integrated circuit incorporating the device DIS has been produced, the device DIS is powered (step ST20).

[0174] An initial code RD2 is then generated (step ST21), which is stored D times respectively in the D memory areas ZM1-ZMD (step ST23).

[0175] Any new generation of the initial code RD2 is then prevented (step ST23).

[0176] The number D is determined on the basis of the necessary number of times the device DIS is used during the functional tests of the device and the maximum number of times the device is used by the end user.

[0177] In practice, the device DIS will no longer be able to deliver the code HUK2 after it has delivered it D times.

[0178] In addition to the steps just mentioned, the method also comprises, in a step ST24, generating a piece of reliability information MSK and storing it in the set 3 of memory units (step ST25).

[0179] At the end of this first phase PH1, the device DIS is ready for use.

[0180] Figure 3 A first embodiment is described which allows the generation of the code HUK2.

[0181] The code HUK1 is generated after the powering up of the device DIS in a step ST30 (step ST31).

[0182] This generation can be triggered automatically or in response to an internal control generated by a control unit internal to the device, for example software or a state machine.

[0183] The code HUK1 is then stored, for example in internal registers (step ST32).

[0184] After receiving another internal control HUK2CMD, also generated for example by the control unit, in a step ST33, and if the code HUK2 has not been generated D times (step ST34), a step ST36 is executed in which the initial code RD2 is read in one of the memory areas ZMi still available.

[0185] On the other hand, if the code HUK2 has been generated D times, a new generation and a new delivery of the code HUK2 are not possible (step ST35).

[0186] After reading the initial code RD2 in a step ST36, the code HUK2 is generated from the initial code RD2 and the stored code HUK1 in a step ST37.

[0187] In addition, as will be seen in more detail below, the reading of the initial code RD2 in the memory area ZMi automatically causes its destruction in the memory area ZMi (step ST38).

[0188] The code HUK2 is then delivered to the first output interface INST1 of the device DIS.

[0189] The code HUK2 is therefore a limited use code, since it can only be generated D times.

[0190] Figure 4 Another example of use of the device DIS is illustrated.

[0191] In this example, after the powering up of the device DIS in a step ST40, the code HUK1 is generated in a step ST41. It is then delivered to the output interface INST2 (step ST42).

[0192] Likewise, this generation of HUK1 can be triggered automatically or in response to an internal control generated by an internal control unit of the device.

[0193] These steps can be repeated an infinite number of times.

[0194] The key HUK1 is thus not limited in use.

[0195] Reference will now be made more particularly to Figure 5 and to subsequent figures to describe more in detail Figure 1 some components of the device DIS.

[0196] Memory cells used in a physically unclonable function device

[0197] As mentioned above, the device DIS comprises memory areas ZMi and various sets 1, 2 and 3 of memory cells.

[0198] These memory cells are split-gate type non-volatile cells.

[0199] In Figure 5 , the reference M denotes such a split-gate type non-volatile memory cell, for example of the select transistor type with a vertical gate buried in the integrated circuit substrate.

[0200] More particularly, the memory cell M comprises a state transistor T comprising a floating gate FG covered by a control gate CG connected to a gate control line CGL.

[0201] The drain (D) of the state transistor T is connected to a bit line BL, while the source (S) of the state transistor T is connected to the drain of a select transistor ST.

[0202] The select transistor ST comprises a gate CSG connected to a word line WL.

[0203] The source (S) of the select transistor ST is connected to a source line SL.

[0204] As Figure 6 illustrated, each state transistor of a memory cell cooperates with a select transistor ST vertically and buried in the substrate SB.

[0205] The channel ZCH of the state transistor is referred to as ZCH.

[0206] The select transistor ST connected to two state transistors Ti,j and Ti+1,j each have a vertical channel ZCV and a buried vertical common select gate CSG. Note that, for simplicity of the figures, the contact allowing the connection of the common buried gate CSG to the corresponding word line WLi,i+1 is not shown.

[0207] Figure 6 More particularly, two twin cells Mi,j and Mi+1,j belonging to the same column j and to two lines i and i+1 are illustrated.

[0208] The state transistor is here a depletion-mode state transistor as described in the French patent application n°3049380.

[0209] As known by the person skilled in the art, a depletion-mode MOS transistor is turned on in the absence of a control voltage applied to the control gate of the state transistor (control gate grounded) and thus, by capacitive coupling, to the floating gate. The state transistor is thus said to be "normally on". On the other hand, as the absolute value of the control voltage present on the control gate increases (becomes more and more negative), the transistor becomes more and more non-conductive, eventually turning off beyond the blocking voltage.

[0210] The channel ZCH of the state transistor is advantageously a surface channel, making it possible to block the conduction of the channel by applying an acceptable control voltage to the control gate of the state transistor.

[0211] The implantation energy of the dopant defines the depth of the channel ZCH. As an indication, this energy can be comprised between 5 keV and 100 keV, then leading to a channel depth of the order of 100 nm.

[0212] In the case of an N-conductivity channel, the implanted dopant can be for example arsenic As, and the concentration of the dopant determines the threshold voltage Vth0 of the state transistor of the memory cell in its original state. The state transistor is here configured to have such a negative threshold voltage Vth0. In this respect, a dose of implanted dopant comprised between 10 12 atoms / cm 2 and 10 14 atoms / cm 3 may be used.

[0213] With such a dose of dopant, a negative voltage Vth0 of for example between -1 volt and -0.5 volt can be obtained.

[0214] Memory plane structure used in a physically unclonable function device

[0215] With such a memory cell, different memory plane structures are possible, i.e. a structure with a single bit line per column or a structure with two (or double) bit lines per column.

[0216] The memory plane of the memory device DM comprising D memory zones ZMi has a structure with one bit line per column, while the sets 1, 2 and 3 have a structure with double bit lines per column. Memory plane structure with one bit line per column

[0217] As an example, Figure 7 denotes a memory plane structure PM having single bit lines per column and comprising memory cells Mi,j, Mi,j+1, Mi-1,j, Mi-1,j+1 of the type described in patent application US 2013 / 0228846.

[0218] The memory cells Mi,j and Mi,j+1 of rank "i" belong to the line or row of rank i of the memory plane and are connected to the word line WLi-1,i and to the gate control line CGLi.

[0219] The memory cells Mi-1,j and Mi-1,j+1 of rank "i-1" belong to the line or row of rank "i-1" of the memory plane and are connected to the word line WLi-1,i and to the gate control line CGLi-1.

[0220] The memory cells Mi,j and Mi-1,j belonging to rank "j" of column j can be read and written via a single bit line BLj and the memory cells Mi,j+1 and Mi-1,j of rank "j-1" can be read and written via a single bit line BLj+1.

[0221] Each memory cell comprises a floating gate transistor FG, respectively Ti,j; Ti,j+1; Ti-1,j; Ti-1,j+1. The drain region (D) of the transistors Ti,j and Ti-1,j is connected to the bit line BLj and the drain terminal of the transistors Ti,j+1 and Ti-1,j+1 is connected to the bit line BLj+1. The control gate CG of the transistors Ti,j and Ti,j+1 is connected to the gate control line CGLi and the control gate CG of the floating gate transistors Ti-1,j and Ti-1,j+1 is connected to the gate control line CGLi-1.

[0222] The source terminal (S) of each floating gate transistor is connected to the source line SL by means of a selection transistor ST. The selection transistors ST of the memory cells Mi,j and Mi-1,j have a common selection gate CSG and these two memory cells are therefore called "twins". Likewise, the memory cells Mi,j+1 and Mi-1,j+1 are twin memory cells and their selection transistors ST have a common selection gate CSG.

[0223] Each selection gate CSG is a vertical gate buried in the substrate in which the memory plane PM is produced, the source line SL also being buried. The common selection gate CSG of these twin memory cells is connected to the word line WLi-1,i.

[0224] Memory plane structure with two bit lines per column

[0225] Figure 8The structure of a memory plane and twin storage cells, called "double bit lines" (two bit lines per column) is illustrated.

[0226] The memory plane PM comprises rows and columns of storage cells, eight storage cells C1,j; C2,j; C3,j; C4,j; C1,j+1; C2,j+1; C3,j+1; C4,j+1 are represented here. Each storage cell comprises a state transistor, respectively labeled T1,j; T2,j; T3,j; T4,j; T1,j+1; T2,j+1; T3,j+1; T4,j+1 and a selection transistor ST connected between the source plane SL and the state transistor.

[0227] The storage cells C1,j; C2,j; C3,j; C4,j belong to a column of rank j and the storage cells C1,j+1; C2,j+1; C3,j+1; C4,j+1 belong to an adjacent column of rank j+1. The storage cells C1,j; C1,j+1 belong to a first storage cell row and their state transistors T1,j; T1,j+1 have a control gate CG1 connected to a common gate control line CGL1. The storage cells C2,j; C2,j+1 belong to a second storage cell row and their state transistors T2,j; T2,j+1 have a control gate CG2 connected to a common gate control line CGL2. The storage cells C3,j; C3,j+1 belong to a third storage cell row and their state transistors T3,j; T3,j+1 have a control gate CG3 connected to a common gate control line CGL3. The storage cells C4,j; C4,j+1 belong to a fourth storage cell row and their state transistors T4,j; T4,j+1 have a control gate CG4 connected to a common gate control line CGL4.

[0228] In the column of rank j, the storage cells C1,j; C2,j are twin storage cells and their selection transistors ST comprise a common selection gate CSG1,2 connected to a common word line WL1,2.

[0229] Likewise, the storage cells C3,j; C4,j are twin storage cells and their selection transistors ST comprise a common selection gate CSG3,4 connected to a common word line WL3,4.

[0230] In the column of rank j+1, the storage cells C1,j+1; C2,j+1 are twin storage cells and their selection transistors ST comprise a common selection gate CSG1,2 connected to a word line WL1,2.

[0231] The storage cells C3,j+1; C4,j+1 are twin storage cells and their selection transistors ST comprise a common selection gate CSG3,4 connected to a common word line WL3,4.

[0232] The common select gates CSG1,2 or CSG3,4 of the pair of twin memory cells are electrically conductive vertically buried gates of trench shape made in the substrate, and the source terminal (S) of the select transistor ST is connected at the buried source plane SL, extending under the region of the substrate where the memory cells are implanted.

[0233] The memory plane PM comprises two bit lines per column of memory cells. Thus, two bit lines B1,j; B2,j are allocated to the memory cells of rank j, and two bit lines B1,j+1; B2,j+1 are allocated to the memory cells of the column of rank j+1.

[0234] The two twin memory cells are connected to different bit lines among the two bit lines allocated to the column in which they are located, while the two adjacent but not twin memory cells are connected to the same bit line.

[0235] Thus, in the column of rank j:

[0236] - the drain terminal (D) of the state transistor T1,j is connected to the bit line B1,j via the electrically conductive path 1A;

[0237] - the drain terminal of the state transistor T2,j is connected to the bit line B2,j via the electrically conductive path 23B;

[0238] - the drain terminal of the state transistor T3,j is connected to the bit line B2,j via the electrically conductive path 23B (the memory cell C2,j is adjacent but not twin to the memory cell C3,j), and

[0239] - the drain terminal of the state transistor T4,j is connected to the bit line B1,j via the electrically conductive path 4A.

[0240] In the column of rank j+1:

[0241] - the drain terminal of the state transistor T1,j+1 is connected to the bit line B1,j+1 via the electrically conductive path 1C;

[0242] - the drain terminal of the state transistor T2,j+1 is connected to the bit line B2,j+1 via the electrically conductive path 23D;

[0243] - the drain terminal of the state transistor T3,j+1 is connected to the bit line B2,j+1 via the electrically conductive path 23D (the memory cell C2,j+1 is adjacent but not twin to the memory cell C3,j+1), and

[0244] - the drain terminal of the state transistor T4,j+1 is connected to the bit line B1,j+1 via the electrically conductive path 4C.

[0245] Column decoder and line decoder

[0246] As will be seen below, the various components of the device DIS use column and line decoders to select the memory cells.

[0247] A specific column decoder can be used for each component. Some of these decoders can have a conventional structure. The column decoders associated with the non-volatile memory device DM have a specific structure.

[0248] In this case, as will be seen in more detail at the end of the description with reference to Figure 37 and Figure 38 It is particularly advantageous to provide a single column decoder able to address the various memory planes.

[0249] This allows to simplify the overall architecture of the device and to reduce the volume on silicon.

[0250] The line decoders in turn have a conventional structure.

[0251] First physical unclonable function module MPF1 and its operation

[0252] Reference will now be made more specifically to Figures 9-11 to describe an exemplary embodiment of the first module MPF1 having a physical unclonable function aimed at generating an initial unpredictable code RD2 in more detail.

[0253] As mentioned above, the first module MPF1 comprises a first set of memory cells.

[0254] Each memory cell has the features described with reference to Figure 6 .

[0255] The state transistor is of the depletion type, its normally on characteristic when the memory cell is in the original state and a zero voltage is applied to the control gate is related to a value of threshold voltage of the memory cell in its original state which can be chosen negative or substantially zero.

[0256] The state transistor of the memory cell in the original state is here configured to have such a negative threshold voltage, of the order of -1 volt for example.

[0257] All the memory cells of this first set 1 are in the original state.

[0258] All the state transistors of all the cells of the first set 1 are aimed at having the same threshold voltage.

[0259] However, the effective threshold voltage, i.e. the actual value of the threshold voltage, varies slightly according to random differences, for example due to physical manufacturing distortions. Differences of this type are common and known per se.

[0260] The transistors of the cells of the first set 1 thus each have an effective threshold voltage belonging to a common random distribution.

[0261] And here this common random distribution is the threshold voltage distribution of the transistors of the original memory cells which are not written.

[0262] Now, if we refer more particularly to Figure 9 It can be seen that in this advantageous embodiment, the first set 1 of non-volatile memory cells CEL is organized in a first two matrix subsets 10L and 10R symmetrically arranged with respect to the reading means LECT of a conventionally known structure per se, the reading means LECT generally comprising a sense amplifier 5.

[0263] All the lines or rows of the first two matrix subsets 10L and 10R are parallel.

[0264] The line decoding of each of these two subsets 10L, 10R is performed by a line decoder XDEC of a conventionally known structure per se, while the column decoding of these first two subsets is performed by two column decoders YDEC also of a known conventional structure per se, symmetrically arranged with respect to the sense amplifier 5.

[0265] And, these reading means LECT are configured to perform a differential reading of the effective threshold voltage of the state transistors of a pair of symmetric memory cells CELijL and CELijR, the pair of symmetric memory cells CELijL and CELijR being respectively located in the first two subsets 10L and 10R on homologous columns in these first two subsets 10L and 10R.

[0266] Now more particularly referring to Figure 10 to describe the differential reading RD performed by the reading means LECT incorporating the sense amplifier 5.

[0267] In the example illustrated Figure 10 , the reading means LECT are configured to measure the difference between the effective threshold voltages of a pair of state transistors T respectively belonging to two memory cells CELijL and CELijR.

[0268] The reading means are coupled to the transistors T via respective bit lines BLL and BLR.

[0269] The selection transistors ST are controlled on their gate by signals transmitted on respective word lines WLL and WLR.

[0270] The differential reading RD such as Figure 10 is advantageously performed with the control gates of the state transistors grounded.

[0271] The sense amplifier 5 is configured to amplify the difference between the current ICL flowing in the cell CELijL and the current ICR flowing in the cell CELijR.

[0272] As these reading currents ICL and ICR represent the effective threshold voltages of the floating gate transistors of the respective cells CELijL and CELijR, the difference of these currents represents the difference between the effective threshold voltages of the state transistors.

[0273] The reading device LECT is thus able to measure the difference between the effective threshold voltages of the state transistor pairs of the two cells arranged on the corresponding bit line.

[0274] And, by way of non-limiting example, it can be decided that the data DATAij contained in the cell pair has the logical value 0 if the current ICL is greater than the current ICR, and the logical value 1 if the current ICL is less than the current ICR.

[0275] Of course, the opposite convention can be adopted.

[0276] The differential reading RD of the storage cells of the first set 1 thus provides an initial code RD2.

[0277] Once this code RD2 has been generated, it is destroyed, for example as shown in Figure 11

[0278] More particularly, in this respect, the management device can comprise a programming device MPROG of conventional structure configured to program the storage cells of the first subset 10L or of the second subset 10R.

[0279] The subsequent differential reading of the cells of this first set will thus provide a series of constant values.

[0280] Alternatively, the programming device can be replaced by an erasing device of conventional structure configured to erase the storage cells of the first subset 10L or of the second subset 10R.

[0281] Non-volatile memory device DM and operation thereof

[0282] An example of structure of the non-volatile memory device DM and of operation thereof will now be described in more detail with reference to Figures 12-27

[0283] Such an example is described in the French patent application entitled "Non-volatile memory device readable only a predetermined number of times" filed on the same day as the present application in the name of the Applicant. ​​

[0284] The content of this other patent application is incorporated herein by reference for all practical purposes.

[0285] Some of its features are recalled here.

[0286] The memory plane structure PM of the memory device DM is a structure with only one bit line per column as described in Figure 7 The memory plane structure PM of the memory device DM is a structure with only one bit line per column as described in

[0287] Figure 12 Two twin cells Mi,j and Mi+1,j belonging to the same column j and to two lines i and i+1 are more precisely illustrated.

[0288] Their drains are connected to the same bit line BLj, the bit line BLj being the only bit line for the column j.

[0289] Each memory cell has the features described with reference to Figure 6 Each memory cell has a first state, for example an erased state, in which it stores a bit having a first logical value, for example the logical value 1, and a second state, for example a programmed state, in which it stores a bit having a second logical value, for example the logical value 0.

[0290] The state transistor of the memory cell is advantageously configured to be on when the memory cell is in its first state and off when the memory cell is in its second state.

[0291]

[0292] The different threshold voltages Vthe, Vth0 and Vthp corresponding respectively to an erased, blank and programmed memory cell are schematically illustrated. Figure 13 In the read mode, a zero read voltage can be applied to the control gate CG of the state transistor and a positive voltage to the bit line BL.

[0293] Since the state transistor is depleted with a negative voltage Vth0, it is generally on for a blank memory cell, that is to say, there is no charge in the floating gate.

[0294] The state transistor of the memory cell is advantageously configured to be on when the memory cell is in its first state and off when the memory cell is in its second state.

[0295] It can be seen that the state transistor of the erased memory cell will be on, while the state transistor of the programmed memory cell will be off. And the fact of applying a zero voltage to the control gate and therefore to the floating gate FG of the state transistor does not induce a read stress. Figure 13 Furthermore, the programming or erasing of the floating gate transistor is here performed by injecting or extracting charges in the gate of the transistor by means of hot electron(s) injection at high voltage(s).

[0296]

[0297] ​More specifically, the erasing of a memory cell is ensured by combining a positive voltage applied to the substrate with a negative voltage applied to the control gate of its state floating gate transistor.

[0298] For twin cells, if simultaneous erasing is not desired, a positive voltage is applied to the control gate of its state transistor.

[0299] The programming of a memory cell can be ensured, for example, by applying a positive voltage to the bit line concerned, by applying a zero voltage to the substrate and a positive voltage to the control gate of its floating gate state transistor.

[0300] The selection of such a memory cell to be programmed is performed by applying to the word line concerned a positive voltage greater than the threshold voltage of the state transistor.

[0301] As for twin cells, if simultaneous programming is not desired, a weak negative voltage (for example -0.5 volts or -1 volt) or zero is applied to the control gate of its state transistor.

[0302] Finally, as mentioned above, the reading of a memory cell is ensured by applying a zero voltage to the control gate CG of its state transistor and a positive voltage to the corresponding bit line.

[0303] The selection of such a memory cell to be read is performed by applying to the word line concerned a positive voltage greater than the threshold voltage of the state transistor.

[0304] Indeed, a zero voltage will be applied to all the cells of the memory plane in the reading mode.

[0305] Thus, the two selected twin cells will be read simultaneously.

[0306] And, if in addition, the column decoder is configured to select two adjacent bit lines simultaneously as will be seen in more detail below, the two corresponding twin cell pairs will be read simultaneously.

[0307] Embodiments and implementations of the memory device DM will now be more particularly described with reference to Figures 14-27 for the sake of simplicity, only one memory region ZM is shown and the operation of this memory region only will be described, it being understood that the structure and operation of the D memory regions ZM1-ZMD of the memory device DM are identical.

[0308] In Figure 14 for the sake of simplicity, only one memory region ZM is shown and the operation of this memory region only will be described, it being understood that the structure and operation of the D memory regions ZM1-ZMD of the memory device DM are identical.

[0309] This memory region ZM here contains a matrix of memory cells Mi,j having two rows or lines L0 and L1 and N columns, here 32.

[0310] In this example, i denotes the row or line index and i is 0 or 1.

[0311] In this example, the index j denotes the column index and ranges from 0 to 31.

[0312] The memory zone ZM is intended to store a piece of information comprising N binary data D0-D31.

[0313] It is considered here that the N binary data D0-D31 are data of an initial code RD2 generated by the first module MPF1.

[0314] The memory device DM also comprises first processing means MTR1, which specifically comprise a conventional structure line decoder DECR, and are configured to pass voltages on the word lines WL0,1 and on the gate control lines CGL0 and CGL1.

[0315] The processing means also comprise a column decoder DECC.

[0316] This column decoder DECC comprises here a set of switches SW0-SW31, each switch comprising two MOS transistors in parallel.

[0317] The first terminal of the switch SWj is connected to the corresponding bit line BLj.

[0318] The second terminal of the switch SWj is connected, either to a sense amplifier circuit AMP, through a MOS transistor whose gate is controlled by a read signal READ, or to a conventional structure programming means PRGL, through another MOS transistor whose gate is controlled by a programming control signal PROG.

[0319] These READ and PROG signals are passed by the first processing means MTR1 depending on whether it is a read phase or a programming phase.

[0320] As Figure 14 illustrated, the column decoder DECC is configured to select two bit lines BL0 and BL31 associated with two columns located at the two ends of the memory zone ZM, individually, with the aid of the logic signals COL0 and COL31.

[0321] In addition, the column decoder is also configured to select two adjacent bit lines BLj and BLj+1 simultaneously, through the logic signal COLjj+1.

[0322] This individual selection of the two bit lines BL0 and BL31 and the simultaneous selection of two adjacent bit lines are performed for the operation of storing the piece of information D0-D31 in the memory cells of the memory zone ZM and for the read operation which will be described in more detail below, which comprises replacing a previous bit with a reference bit which is in this case a bit of logical value 0.

[0323] The logic signals COL0, COL31 and COLjj+1 are delivered by the logic device MCC.

[0324] As mentioned above, the memory zone is intended to store the 32-bit data D0-D31 of the code RD2.

[0325] And, as Figure 15 illustrated, before storing this piece of information (code RD2) in the memory zone ZM, all the memory cells of the memory zone ZM are in the erased state, i.e. they all contain the logic value 1.

[0326] Reference will now be made more particularly to Figures 16-19 illustrate the successive writing of the N bits D0-D31 of the piece of information (code RD2) in the memory zone ZM.

[0327] Overall, since the initial state of the memory cells of the memory zone ZM is the erased state, i.e. contains the logic "1", no operation for writing data having the logic value "1" will be performed in the memory cells.

[0328] On the other hand, in the case where the data to be written in the cell is "0", a programming operation of the memory cell will be performed.

[0329] The voltages to be applied to the bit line, the substrate, the control gate and the word line to select and program the cell are indicated above.

[0330] Likewise, the voltages to be applied to the bit line, the control gate and the word line to select and read the cell are indicated above.

[0331] In Figure 16 , the column decoder DECC selects the two bit lines BL0 and BL1 using the logic signal COL1.

[0332] Furthermore, the gate control line CGL1 is selected.

[0333] As a result, the data D0 is written in both the memory cell M1,0 and the memory cell M1,1.

[0334] Then, as Figure 17 illustrated, the column decoder selects the two bit lines BL1 and BL2 using the logic signal COL12.

[0335] Furthermore, at this time, it is the gate control line CGL0 which is selected.

[0336] Thus, the second data D1 of the piece of information is stored simultaneously in the two memory cells M0,2 and M0,3 of the first line L0.

[0337] The write operation then continues sequentially until the last data D31 of the information piece is written in the storage cell M0,31.

[0338] This is done by selecting the bit line BL31 with the logic signal COL31 and selecting the gate control line CGL0. Figure 18 ).

[0339] At the end of this write operation, as shown in Figure 19 , a checkerboard filling of the memory area is obtained, so that the data except the last data D31 are stored in two adjacent storage cells of the same line and two consecutive data are respectively stored in two twin cells of the same column.

[0340] Moreover, the twin cell M0,0 of M1,0 storing the data D0 stores the value 1, while the last data D31 is stored in the twin storage cell M0,31 of the storage cell M1,31 storing the data D30.

[0341] Reference will now be made more particularly to Figures 20-27 to illustrate an example of reading the information piece stored in the memory area ZM (code RD2).

[0342] Since a zero voltage (ground GND) is applied at the control gate of all the storage cells of the memory area at the reading, the reading of the first twin storage cell of a column simultaneously causes the reading of the second twin cell.

[0343] Now, if the first twin cell contains the logic "1", this logic "1" will mask the read value of the data located in the second twin cell.

[0344] In fact, whatever the value of the stored data, the reading of the two twin cells will always give a logic "1".

[0345] This is the reason why it is necessary to replace the value stored in the twin cell of a storage cell by a selected reference bit before reading this storage cell, to allow the correct recovery of the stored data. In this case, this reference bit will have the value "0", the value "0" corresponding to the previous programming of the twin cell to store "0" therein.

[0346] This is illustrated in Figure 20 .

[0347] More particularly, the bit line BL0 is selected using the logic signal COL0 and the storage cell M0,0 is programmed to store therein the logic "0" using the line control signal CGL0.

[0348] Then, the two twin cells M0,0 can be read to store therein the logic "0".

[0349] Then, asFigure 21 As shown, by using the logical signal COL0 to select the bit line BLO, both twin cells M0,0 and M1,0 can always be read.

[0350] And, at this time, the data DO is correctly read.

[0351] Indeed, if the data DO is equal to 0, the value 0 will be actually read by the sense amplifier circuit AMP.

[0352] And, if the logical value of the data DO is equal to 1, the sense amplifier circuit AMP will read a logical "1".

[0353] As Figure 22 and Figure 23 shown, the data D1 is then read.

[0354] And, since at this time the column decoder will select both bit lines BLO and BL1 at the same time, and a zero voltage GND is applied to the control gates of the pass transistors of all the memory cells, both the two twin cells located at column "0" and the two twin cells located at column "1" will be read at the same time.

[0355] Moreover, in order to obtain a correct recovery of the logical value of the data D1, not only the twin cells of the cell D1 need to be programmed to the value "0" before reading this data D1, but also the cells including the previously read data DO can be programmed.

[0356] This is illustrated in Figure 22 .

[0357] It can be seen that, in this preliminary programming step, the memory cells M1,0 and M1,1 will be programmed with a logical value "0" by selecting the bit lines BLO and BL1 by the logical signal COL01 and by applying a programming voltage to the gate control line CGL1.

[0358] As a result, as Figure 23 shown, the selection of both bit lines BLO and BL1 and the application of a zero voltage GND on the control gates of the pass transistors results in the simultaneous reading of the logical value of the data D1 and of the three logical values "0" stored in the memory cells M0,0; M1,0 and M1,1.

[0359] As a result, the logical value of the data D1 is correctly recovered. Indeed, if this data is equal to 0, the sense amplifier circuit will effectively read "0", while if this logical value is equal to 1, the sense amplifier circuit will effectively read "1".

[0360] It should thus be noted here that not only does the previous programming allow a correct recovery of the data to be read, but this previous programming also corrupts the data that has been previously read.

[0361] Figure 24 and Figure 25 The reading of the following data D2 is illustrated.

[0362] Before this reading, the cells M0,1 and M0,2 are programmed Figure 24 and then the data D2 stored in the memory cell M1,2 Figure 25 are read.

[0363] The data D1 have thus been destroyed.

[0364] Figure 26 and Figure 27 The reading of the last data D31 is illustrated.

[0365] In this respect, as Figure 26 illustrated, the twin cell M1,31 is programmed in advance, and then, as Figure 27 illustrated, the cell D31 stored in the memory cell M0,31 is read.

[0366] At the end of this reading, note that all the memory cells, except the last cell M0,31, store a logical 0.

[0367] The reading of the N binary data of the stored code RD2 thus destroys all the bits of this code, except the last one.

[0368] And, it is no longer possible to read this code RD2 again in the memory zone ZM.

[0369] In this case, the D zones ZM1-ZMD will be read in succession as indicated above for the zone ZM, to allow the information piece RD2 to be read only D times.

[0370] Second physically unclonable function module MPF2 and operation thereof

[0371] The second module MPF2 can be a physically unclonable function module, with the features of the physically unclonable function device described in the French patent application filed under n°2002929, which is incorporated into the present patent application by reference for all practical purposes.

[0372] Some features are now recalled.

[0373] As Figure 28 illustrated, the second module MPF2 comprises a second set 2 of non-volatile memory cells CEL.

[0374] The device DIS also comprises second processing means MT2 configured to pass from the reading of the effective threshold voltage of the state transistor of the memory cells CEL of the second set 2 an unpredictable code HUK1.

[0375] Each memory cell CEL has a reference Figure 6 to the described features.

[0376] However, as Figure 29 illustrated, the cell CEL comprises a state transistor T having a control gate CG and a floating gate FG, the control gate CG and the floating gate FG being electrically connected here, for example, by a via or a contact, which is not located in the plane of Figure 29 but is schematically illustrated by the two dashed lines.

[0377] The floating gate FG is separated from the semiconductor substrate SUB by a gate oxide OX, the thickness of which is advantageously greater than 8 nanometers, for example comprised between 8 and 10 nanometers.

[0378] The drain D of the state transistor T is connected to the bit line by a contact CBL.

[0379] The control gate CG of the transistor T is in turn connected to the gate control line.

[0380] As mentioned above, the channel of the state transistor T comprises an implantation in the surface CH, the channel being, for example, N-doped, so that the corresponding memory cell operates in depletion mode.

[0381] In other words, the state transistor T is of the depletion type, the normally on characteristic of the state transistor when the memory cell is in the original state and a zero voltage is applied to the control gate is related to the value of the threshold voltage of the transistor T in the original state of the memory cell, which can be chosen to be negative or substantially zero.

[0382] In the case of a channel of conductivity N, the implanted dopant can be, for example, arsenic As, and the concentration of the dopant determines the threshold voltage of the transistor T of the memory cell in the original state.

[0383] As for the cells of the first set 1, if the memory cell is in the original state, the state transistor is here configured to have a negative threshold voltage, for example of the order of -1 volt.

[0384] All the state transistors of all the cells CEL of the first set are intended to have the same threshold voltage.

[0385] However, the effective threshold voltage, i.e. the actual value of the threshold voltage, varies slightly according to random differences, for example due to physical manufacturing distortions. Differences of this type are common and known per se.

[0386] Since the control gate and the floating gate of the state transistor are electrically connected, the state transistor inherently has a greater variability of resistance to these distortions and therefore a wider distribution.

[0387] Thus, the transistors T of the cells CEL of the second set 2 each have an effective threshold voltage belonging to a common random distribution.

[0388] In particular, the common random distribution can be a distribution of threshold voltages of the transistors of the original memory cells not written.

[0389] If reference is now made more particularly to Figure 28 It can be seen that the second processing means MT2 comprise a third set 3 of memory cells CELM, each also having a selection transistor buried in the semiconductor substrate and a state transistor having a control gate and a floating gate.

[0390] In fact, the memory cells CELM are similar to the memory cells CEL, except that the floating gate and the control gate of the state transistor are not electrically connected. They also have the features described with reference to Figure 6 .

[0391] As will be seen in more detail hereafter, these memory cells CELM are intended to store a piece of reliability information representative of the reliability or of the unreliability of the content of the memory cells CEL of the second set 2.

[0392] The second processing means MT2 comprise first generating means MGEN1 configured to generate said piece of reliability information.

[0393] The second processing means MT2 also comprise second generating means MGEN2 configured to generate a code HUK1 as a function of at least the reading of the effective threshold voltage of the state transistor of the memory cells CEL and of said piece of reliability information contained in the memory cells CELM of the third set 3.

[0394] Examples of the structure and operation of the first generating means MGEN1, of the second generating means MGEN2 and of the matrix arrangement of the second set of cells 3 will be given in more detail.

[0395] If reference is now made more particularly to Figure 30 It can be seen that, in this advantageous embodiment, the second set 2 of non-volatile memory cells CEL is organized in a second two matrix subsets 20L and 20R, the second two matrix subsets 20L and 20R being symmetrically arranged with a second reading means LECT2 of a conventional structure known per se, the second reading means LECT2 generally comprising a sense amplifier 5.

[0396] All the lines or rows of the second two matrix subsets 20L and 20R are parallel.

[0397] The line decoding of each of these two subsets 20L, 20R is performed by a line decoder XDEC of a conventional structure known per se, while the column decoding of the first two subsets is performed by two column decoders YDEC also of a conventional structure known per se, the two column decoders YDEC being symmetrically arranged with respect to the sense amplifier 5.

[0398] And, these second reading means LECT2 are configured to perform a differential reading of the effective threshold voltages of the state transistors of a pair of symmetric memory cells CELijL and CELijR or CELmpL and CELmpR, the pair of symmetric memory cells being located in the second two subsets 20L and 20R on similar columns of these second two subsets.

[0399] And, the memory cells of the third set 3 are intended to contain a piece of reliability information representative of the reliability or of the unreliability of the content of a pair of memory cells of the second set.

[0400] These pieces of reliability information are here binary data having a first logical value, for example the logical value 0, or a second logical value, for example the logical value 1, the first logical value being representative of the content of a given pair of memory cells of the second set, the second logical value being representative of the reliability of the content of a given pair of memory cells of the second set.

[0401] Thus, as an example, in Figure 30 the piece of reliability information Mij having the logical value 0 here represents the unreliability of the content bijL and bijR of the pair of memory cells CELijL and CELijR of the second set.

[0402] On the other hand, the piece of reliability information Mmp having the logical value 1 here represents the reliability of the content bmpL and bmpR of the pair of memory cells CELmpL and CELmpR of the second set.

[0403] The set of these pieces of reliability information forms a mask MSK.

[0404] Reference will now be made more particularly to Figure 31 to describe the differential reading RD performed by the second reading means LECT2 incorporating the sense amplifier 5.

[0405] In the example illustrated in Figure 31 , the second reading means LECT2 are configured to measure the difference between the effective threshold voltages of the pair of transistors T belonging respectively to the two memory cells CELijL and CELijR.

[0406] The second reading means are coupled to the transistors T via the respective bit lines BLL and BLR.

[0407] The selection transistors ST are controlled on their gate by signals transmitted on the respective word lines WLL and WLR.

[0408] In addition to the sense amplifier 5, the second reading device comprises a reference current generator 51, which can or can not be connected to the sense amplifier 5 via a switch.

[0409] In the context of a differential reading RD such as Figure 31 In the context of a differential reading RD such as

[0410] The sense amplifier 5 is configured to amplify the difference between the current ICL flowing in the cell CELijL and the current ICR flowing in the cell CELijR.

[0411] Since these reading currents ICL and ICR represent the effective threshold voltages of the floating gate transistors of the respective cells CELijL and CELijR, the difference of these currents represents the difference between the effective threshold voltages of these state transistors.

[0412] The second reading device LECT2 is thus able to measure the difference between the effective threshold voltages of the pair of state transistors of the two cells arranged on the corresponding bit line.

[0413] And, as a non-limiting example, it can be decided that the data DATAij contained in this pair of cells has the logical value 0 if the current ICL is greater than the current ICR, and the logical value 1 if the current ICL is less than the current ICR.

[0414] Of course, the opposite convention can be adopted.

[0415] Reference will now be made more particularly to Figure 32 and Figure 33 to describe a differential reading of the effective threshold voltages of the state transistors of a pair of storage cells taking into account a margin value.

[0416] Again, these differential readings are advantageously performed through the control gates of the grounded state transistors.

[0417] Figure 32 A first differential reading RDM0 taking into account a margin value is illustrated.

[0418] More particularly, during this reading RDM0, an additional current IREF generated by one of the current generators 51 is added to the current flowing by the cell CELijR.

[0419] This allows to measure a difference between the effective threshold voltages higher than a certain margin.

[0420] The margin value corresponds to the current IREF representative of the reference voltage offset.

[0421] The margin value is specifically selected based on the accuracy of the second reading device LECT2.

[0422] As an indicator, the value of the current IREF can be equal to 2 microamps.

[0423] Furthermore, in this case, if the current ICL is greater than the sum of the currents ICR and IREF, the stored data DATAij is set to, for example, equal to 0.

[0424] exist Figure 33 The diagram illustrates another differential readout RDM1 performed by the second reading device LECT2 and taking into account the margin value.

[0425] More specifically, in this case, a reference current IEF is added to the current ICL flowing in the cell CELijL.

[0426] Furthermore, for example, if the current ICR is greater than the sum of the currents ICL and IREF, then DATAij equals 1.

[0427] Now for more specific reference Figure 34 Here is an example to describe the structure of the first generation device MGEN1, which allows the generation of reliability information fragments of the mask MSK.

[0428] Such as Figure 34 As shown, a reliability information fragment is generated by differentially reading the margin values ​​on RDM0 and RDM1 of the effective threshold voltage of the state transistor of the storage cell pair.

[0429] More specifically, the first generation device MGEN1 includes a second reading device LECT2, which is configured to perform a first reading for each pair of memory cells in the second set 1, for example, reading the difference between the current flowing through the first memory cell of the pair by the RDM0 (on the one hand) increased by a reference current representing the margin value, and (on the other hand) the current flowing through the second memory cell of the pair, to obtain first binary data.

[0430] The second reading device LECT2 is also configured to perform a second reading, such as reading the difference between the current flowing through the second memory cell via the reference current and the current flowing through the first memory cell, to obtain second binary data.

[0431] In the example described here, for simplicity, a group of 16 first binary data DB1 obtained at the end of the first reading RDM0 is shown (for example [0000 0111 1111 1111]), as well as a corresponding group of 16 second binary data DB2 obtained after the reading RDM1 (for example [0000 0000 0000 1111]).

[0432] The generating device MGEN1 also comprises a module, generally denoted by the reference 222, configured to generate a mask MSK and to write the mask MSK in the memory cells of the third set 3.

[0433] This module 222 comprises an inverter IV which allows inverting one of the groups of binary data (for example the first group of binary data DB1 resulting from the reading RDM0) to obtain, in the case shown, the group [1111 1000 0000 0000].

[0434] Then, a comparison device, for example an OR gate denoted PL, allows comparing bit by bit the second group of binary data DB2 resulting from the reading RDM1 with the inverse of the first group of binary data DB1 resulting from the reading RDM0.

[0435] If the inverted bit actually has a logical value opposite to that of the corresponding non-inverted bit, the data can be considered reliable and a 1 is assigned to the corresponding piece of reliability information obtained by the logical OR gate.

[0436] On the other hand, if the logical value of the inverted bit is equal to that of the corresponding non-inverted bit, the data is considered unreliable and the corresponding piece of reliability information will have the logical value 0.

[0437] Thus, a mask MSK is obtained comprising as many bits as pairs of memory cells in the second set 2. In the case illustrated, the mask MSK is equal to [1111 1000 0000 1111].

[0438] Of course, the inverter and the OR gate can be replaced by a logical gate of the exclusive OR (XOR) type.

[0439] The module 222 also comprises writing means PROG, of conventional and known structure, allowing the pieces of reliability information (bits) of the mask MSK to be written in the corresponding memory cells of the third set 3.

[0440] Reference will now be made more particularly to Figure 35 to describe an example of structure of a second generating device MGEN2 configured to generate a code HUK1 as a function of the differential reading of the effective threshold voltage of the transistors of the pairs of memory cells and of the pieces of reliability information associated with these pairs of memory cells.

[0441] More particularly, the second reading means LECT2 perform a regular differential reading RD on the pairs of homologous memory cells respectively located in the two subsets 20L and 20R to obtain a first set of output data JS1, for example [0000 0000 0111 1111], comprising in this simplified example 16 binary output data.

[0442] This reading is advantageously performed with the control gate of the grounded state transistor.

[0443] The regular reading means MLCT, also comprising a sense amplifier such as the sense amplifier 5, perform a regular reading RDMSK of the reliability information fragments MSK corresponding to the pairs of cells read and contained in the memory cells of the third set 3, for example [1111 1000 0000 1111].

[0444] This reading RDMSK is also advantageously performed with the control gate of the grounded state transistor.

[0445] The second generating means MGEN2 then comprise masking means 4 configured to retain only the binary data of the set JS1 as a code HUK1, to which is assigned a reliability information fragment meaning that this data is reliable, in this case equal to 1.

[0446] In the current case, the data considered reliable (value 1) are the first five bits on the left and the last four bits, the other bits being uncertain (X).

[0447] Thus, as an example, as Figure 35 illustrated, the code HUK1 will have only 9 bits out of the 16 bits of the set JS1 [0000 0XXX XXXX 1111].

[0448] Although this is not essential, it is preferred, as Figure 36 illustrated, that the third set of memory cells 3 intended to store the reliability information fragments comprises two third subsets 30L and 30R distributed respectively on the two sides of the second subsets 20L and 20R.

[0449] Furthermore, the reliability information fragments associated with the pairs of memory cells are stored in the memory cells of the third set, which are located in the same column as the column in which said corresponding pairs of memory cells are located.

[0450] Furthermore, the first set of memory cells 1 comprises two subsets 10L and 10R, the second set of memory cells 2 comprises two subsets 20L and 20R, the third set of memory cells 3 comprises two subsets 30L and 30R, the memory plane of the non-volatile memory device DM and the managing means are located within the same integrated circuit IC.

[0451] This simplifies the column decoding and makes it more difficult to extract data from the device DIS by an attack for example on the back.

[0452] Column decoder architecture compatible with "unit line" and "double bit line" memory plane architecture

[0453] Due to the difference in structure of the different memory planes of the device DIS (architecture with a single bit line per column for the memory planes of the memory zones ZM1-ZMD and architecture with two bit lines per column for the memory planes of the sets 1, 2 and 3 of memory cells), some metallizations of the integrated circuit are interrupted and allocated only to some columns (bit lines) of the memory planes of the memory zones ZM1-ZMD, while other metallizations are common to the columns of the memory planes of the memory zones ZM1-ZMD and to the columns of the memory planes of the sets 1, 2 and 3 of memory cells, and other metallizations are allocated only to the columns of the memory planes of the sets 1, 2 and 3 of memory cells.

[0454] This is illustrated in part in Figure 37 where it can be seen that the interrupted metallization MET2A corresponds to the bit line BLO of the column 0 marked COL0 of the memory planes of the memory zones ZM1-ZMD and the other metallization MET2B corresponds to the bit line BL1 of the 1stcolumn COL1 of the memory planes of the memory zones ZM1-ZMD and to one of the bit lines B1,0 of the 0thcolumn COL0 of the memory planes of the sets 1, 2 and 3 of memory cells.

[0455] The other bit line B2,0 of the 0thcolumn COL0 of the memory planes of the sets 1, 2 and 3 of memory cells is represented by the metallization MET3.

[0456] The two other metallizations MET5 correspond to the two bit lines B1,1 and B2,1 of the 1stcolumn COL1 of the memory planes of the sets 1, 2 and 3 of memory cells.

[0457] Thus, as Figure 38 illustratively shown in

[0458] The odd numbered columns COL1, COL3,... of the memory planes of the memory zones ZM1-ZMD can be addressed simultaneously to the columns of the memory planes of the sets 1, 2 and 3 of memory cells ordered 4k, COL0, COL4,...

[0459] The columns COL1, COL2, COL3, COL5, COL6, COL7,... of the memory planes of the sets 1, 2 and 3 of memory cells ordered 4k+1, 4k+2 and 4k+3 are individually addressable.

[0460] Figure 38 The single column decoder COLDEC schematically illustrated is configured to:

[0461] - select individually the two columns located at both ends of each memory zone ZMi,

[0462] - select simultaneously the two adjacent columns of each memory zone ZMi and the columns of the first, second and third sets common with one of these two adjacent columns, and

[0463] - select individually the other columns of the first, second and third sets.

[0464] This column decoder comprises MOS transistor-based switches controlled on their gate by control signals and whose source is connected to a common node ND connected to the reading or programming means.

[0465] Here, for simplicity, only 10 switches SW0-SW9 controlled by control signals SCO, SCA to SCJ are shown.

[0466] The signal SCO controlling the switch SW0 allows the individual selection of the column COL0 of the memory zone ZMi.

[0467] The signal SCA controlling the switches SW0 and SW1 allows the selection of the column COL0 of the memory cell sets 1, 2 and 3 and simultaneously the selection of the columns COL0 and COL1 of the memory zone ZMi.

[0468] The signal SCB controlling the switches SW1 and SW5 allows the selection of the column COL0 of the memory cell sets 1, 2 and 3 and simultaneously the selection of the columns COL1 and COL2 of the memory zone ZMi.

[0469] The signal SCC controlling the switch SW2 allows the selection of the column COL1 of the memory cell sets 1, 2 and 3.

[0470] The signal SCD controlling the switch SW3 allows the selection of the column COL2 of the memory cell sets 1, 2 and 3.

[0471] The signal SCE controlling the switch SW4 allows the selection of the column COL3 of the memory cell sets 1, 2 and 3.

[0472] The signal SCF controlling the switches SW5 and SW6 allows the selection of the column COL4 of the memory cell sets 1, 2 and 3 and simultaneously the selection of the columns COL2 and COL3 of the memory zone ZMi.

[0473] For simplicity, the signal SCG, which controls the switch SW6 and another switch not shown in the figure, allows the selection of the column COL4 of the memory cell sets 1, 2 and 3 and simultaneously the selection of the columns COL3 and COL4 of the memory area ZMi.

[0474] The signal SCH, which controls the switch SW7, allows the selection of the column COL5 of the memory cell sets 1, 2 and 3.

[0475] The signal SCI, which controls the switch SW8, allows the selection of the column COL6 of the memory cell sets 1, 2 and 3.

[0476] The signal SCJ, which controls the switch SW9, allows the selection of the column COL7 of the memory cell sets 1, 2 and 3, and so on.

[0477] While the application has been described with reference to exemplary embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the application, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. An integrated device, comprising: The first physically unclonable functional module is configured to generate the initial data set; as well as The management module is configured as follows: At least based on the initial data set, generate an output data set. Only D consecutive transmissions of the output data group are authorized on the first output interface of the device, where D is a non-zero positive integer, and Prevent the generation of any new output data group.

2. The device of claim 1, wherein the management module is configured to prevent the generation of any new output data group by preventing the generation of any new initial data group.

3. The device according to claim 1, wherein the first physically unclonable functional module comprises: A first set of non-volatile memory cells, each non-volatile memory cell having a select transistor buried in a semiconductor substrate and a state transistor having a control gate and a floating gate, the state transistor having a corresponding effective threshold voltage belonging to a common random distribution, and The read module is configured to transmit the initial data set based on the effective threshold voltage of the state transistor of the storage cell of the first set.

4. The device according to claim 3, The first set of non-volatile memory cells is organized into two first matrix subsets arranged symmetrically with respect to the read module, all lines of the first two matrix subsets being parallel, and The read module is configured to perform differential reads of the effective threshold voltages of the state transistors of the symmetric memory cell pairs, which are located on the same source column of the first two subsets, respectively.

5. The device of claim 4, wherein the management module is configured to program or erase the storage units of a subset of the two subsets after the initial data group is read, so as to prevent any new generation of the initial data group.

6. The device according to claim 1, The initial data set includes G initial data points, and The management module includes a non-volatile memory device, which comprises: The memory plane comprises D memory regions, each memory region being configured to store N consecutive data including the G initial data, where N is greater than or equal to G; as well as The first processing module is configured as follows: The N consecutive data are continuously extracted from the D memory regions; as well as During the extraction of the corresponding N consecutive data, at least a portion of the contents of the corresponding memory region is destroyed.

7. The device of claim 6, wherein each memory region comprises a memory cell matrix having two rows and N columns, each memory cell comprising a state transistor having a control gate and a floating gate, the state transistor being selectable by a vertically selected transistor buried in a substrate, the vertically selected transistor including a buried select gate, each memory cell column comprising a twin memory cell pair, the two select transistors in the twin memory cell pair having a common select gate, and wherein the first processing module is configured to store N consecutive bits in the memory region such that, except for the last consecutive bit, the current consecutive bit is stored in two memory cells located in the same row and two adjacent columns, and the current bit and the next bit are stored in two twin cells respectively.

8. The device of claim 7, wherein the first processing module is configured to, in order to read the bits stored in the first twin unit, first replace the bits stored in the second twin unit with a reference bit having a reference value selected to allow the correct recovery of the value of the bits stored in the first twin unit.

9. The device of claim 8, wherein the first processing module is further configured to sequentially read the N consecutive bits and, before being able to read the next consecutive bit, replace the current bit already read in the information segment with the reference bit to destroy the current bit during the extraction of the next bit.

10. The device of claim 6, wherein the memory cell matrix of each memory region comprises: Each column has a single bit line, which is connected to the drain of the state transistor of the twin pair in the corresponding column; And a gate control line for each memory cell row, the gate control line being connected to all control gates of the state transistor of the corresponding memory cell in the row.

11. The device of claim 6, wherein the first processing module includes a column decoder configured to individually select two bit lines associated with two columns located at opposite ends of the memory region, and simultaneously select two adjacent bit lines for storing N consecutive bits and pre-reading and replacing both of these bits.

12. The device of claim 6, wherein the output data group comprises the N consecutive bits.

13. The device according to claim 1, wherein the management module comprises: The second physically unclonable functional module is configured to generate additional data sets, and The development module is configured to develop the output data set based on at least the initial data set and at least the additional data set.

14. The device of claim 13, wherein the management module is further configured to transmit the additional data set on a second output interface of the device.

15. The device of claim 13, wherein the second physically unclonable functional module comprises: A second set of non-volatile memory cells, each of the second set having a selection transistor buried in a semiconductor substrate and a depletion-type state transistor having an electrically connected control gate and a floating gate, the state transistor having a corresponding effective threshold voltage belonging to a common random distribution, and The second processing module is configured to transmit additional data groups based on the reading of the effective threshold voltage of the state transistor of the storage cell of the second set.

16. The device according to claim 15, The second processing module includes a second reading module configured to perform reading. The second set of non-volatile memory cells is organized into two second matrix subsets arranged symmetrically with respect to the second read module, all lines of the second two matrix subsets being parallel, and The second read module is configured to perform differential reads of the effective threshold voltage of the state transistor of the symmetric memory cell pair, and the symmetric memory cell pair is located on the same column of the second two subsets respectively.

17. The device of claim 15, wherein the second processing module comprises a third set of memory cells, each memory cell of the third set having a selection transistor buried in a semiconductor substrate and a state transistor having a control gate and a floating gate, the memory cells of the third set being intended to contain a reliability information segment representing the reliability or unreliability of the contents of the memory cell pair of the second set.

18. The device of claim 17, wherein the third set comprises a matrix arrangement of memory cells that shares the same columns as the matrix arrangement of memory cells in the second set.

19. A method for integrating a device, comprising: A unique, unpredictable code is automatically generated at the first output interface of the device according to claim 1. The only unpredictable code mentioned above is the output data set. The device includes at least one read of a memory region of a non-volatile memory device.

20. The method of claim 19, wherein the first physically unclonable functional module comprises a first set of non-volatile memory cells, the method further comprising: The initial data set is generated during the testing phase; The device stores information segments of N data in D memory regions; After generating the initial data set, some storage units of the first set are programmed or deleted; and Generate and store reliability information fragments.

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