Miniaturized multi-channel high-speed interface protocol control board based on VPX architecture

Abstract

The miniaturized multi-channel high-speed interface protocol control board based on the VPX architecture of the present invention comprises a protocol control module, a high-speed data interface module and a VPX connector; the VPX connector is plugged into the VPX connector of the VPX backplane; the protocol control module, the high-speed data interface module and the VPX connector are connected in sequence; the high-speed data interface module comprises an SRIO interface, a PCIe interface, an Ethernet interface and a 1553B interface; the protocol control module interacts with the network board on the VPX backplane through the PCIe interface and the VPX connector; the protocol control module interacts with the baseband board on the VPX backplane through the SRIO interface and the VPX connector; the protocol control module interacts with the test host computer through the Ethernet interface and the VPX connector; the protocol control module interacts with the network board on the VPX backplane through the 1553B interface and the VPX connector. The present invention solves the problem of real-time processing of high-speed and high-flow data under the self-organizing network protocol function.

Description

Technical Field

[0001] The invention relates to a data link networking system, and in particular to a miniaturized multi-channel high-speed interface protocol control board based on a VPX architecture. Background Art

[0002] With the rapid development of information networks and the increasing interconnectivity of information systems, digital information is showing an explosive growth trend. In the field of industry applications, signals are densely intertwined and the signal forms are becoming more and more complex. The development of high-speed and large-capacity storage array devices is very necessary. Differential serial transmission technology with advantages such as high speed and anti-interference has replaced traditional single-ended parallel interface technology and become the mainstream of high-speed interface technology. Summary of the invention

[0003] The purpose of the present invention is to provide a miniaturized multi-channel high-speed interface protocol control board based on the VPX architecture to solve the problem of real-time processing of high-speed and large-flow data under the self-organizing network protocol function.

[0004] In order to achieve the above-mentioned purpose, the present invention provides a miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, comprising a protocol control module, a high-speed data interface module and a VPX connector; the VPX connector is plugged into the VPX connector of the VPX backplane; the protocol control module, the high-speed data interface module and the VPX connector are connected in sequence; the high-speed data interface module comprises an SRIO interface, a PCIe interface, an Ethernet interface and a 1553B interface; the protocol control module interacts with the network board on the VPX backplane through the PCIe interface and the VPX connector; the protocol control module interacts with the baseband board on the VPX backplane through the SRIO interface and the VPX connector; the protocol control module interacts with the test host computer through the Ethernet interface and the VPX connector; the protocol control module interacts with the network board on the VPX backplane through the 1553B interface and the VPX connector.

[0005] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control module receives instructions from the network board through the PCIe interface, and feeds back the instruction execution status and current network status to the network board through the PCIe interface; the protocol control board receives user data from the network board through the PCIe interface, and uploads the user data received and correctly parsed from the wireless channel to the network board through the PCIe interface; the protocol control module transmits image data with the network board through the 1553B interface.

[0006] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control module transmits user data and self-organizing network protocol control data to the baseband board through the SRIO interface, and receives user data and self-organizing network protocol control data demodulated by the baseband board through the SRIO interface.

[0007] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control module transmits test business data and test instruction data with the test host computer through the Ethernet interface.

[0008] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control board also includes an external storage module, which is connected to the protocol control module and is used to store protocol control programs and high-speed data.

[0009] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the external storage module includes a parallel FLASH supporting BPI mode and configured with a bit width of 16 bits and a DDR3L memory with a capacity of 4Gb.

[0010] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control board also includes a clock management module, the clock management module includes an active crystal oscillator and a programmable crystal oscillator, the active crystal oscillator provides a 50M reference clock as the reference clock of the protocol control module, and the programmable crystal oscillator configures two 125M clocks as the reference clock of the SRIO interface; the clock management module also obtains the 100M reference clock provided by the external clock source of the protocol control board through the VPX connector as the reference clock of the PCIe interface.

[0011] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control board also includes a power conversion module, which converts the working voltage of the protocol control board into the working voltage of each functional module in the protocol control board to supply power to each functional module.

[0012] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the power conversion module includes a series of high-performance DC step-down voltage regulator modules and linear power supply modules.

[0013] The above-mentioned miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, wherein the protocol control module adopts FPGA chip, which is used to realize self-organizing network function, control, generate and process protocol control data of transmission protocol, and the protocol control module includes high-speed transceiver and ARM processor.

[0014] Compared with the prior art, the beneficial technical effects of the present invention are:

[0015] (1) The present invention integrates multiple high-speed interfaces to solve the problem of real-time data processing at high speed and large flow rate;

[0016] (2) The protocol control module of the present invention adopts an ARM processor, which can flexibly configure the working mode, working frequency, and information rate of the transceiver channel in conjunction with the host computer, which is conducive to the universal design of the product and the software-defined radio design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The miniaturized multi-channel high-speed interface protocol control board based on the VPX architecture of the present invention is provided by the following embodiments and drawings.

[0018] Figure 1 Schematic diagram of a self-organizing network in a preferred embodiment of the present invention.

[0019] Figure 2 The block diagram of the protocol control board of the preferred embodiment of the present invention.

[0020] Figure 3 Schematic diagram of a high-speed data interface module in a preferred embodiment of the present invention.

[0021] Figure 4 FIG. 1 is a schematic diagram of a power conversion module in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined Figure 1 to Figure 4 The miniaturized multi-channel high-speed interface protocol control board based on the VPX architecture of the present invention is further described in detail.

[0023] The present invention proposes a design scheme integrating multiple high-speed interfaces based on the original single high-speed interface, providing good support for the functional expansion and application of high-speed information transmission. The present invention is based on the VPX architecture, which is a connector standard based on a high-speed serial bus. The high-speed interfaces involved in the present invention include: 1553B interface, which is an information transmission bus standard; high-speed serial interface, Serial rapid I / O (hereinafter referred to as SRIO); PCIe interface, Peripheral component interconnect express (hereinafter referred to as PCIe) is a high-speed serial computer expansion bus standard; Ethernet interface.

[0024] Figure 1 Shown is a schematic diagram of a self-organizing network in a preferred embodiment of the present invention.

[0025] See also Figure 1, after the protocol control board of this embodiment is inserted into a chassis supporting the VPX standard, it is connected to the VPX backplane, and a network board, a baseband board, a radio frequency processing board and a power board are connected to the VPX backplane;

[0026] The protocol control board interacts with the network board via a 1553B interface to transmit image data;

[0027] The protocol control board interacts with the network board through the PCIe interface; the protocol control board receives instructions from the network board through the PCIe interface, and feeds back instruction execution status and current network status to the network board through the PCIe interface; the protocol control board receives user data from the network board through the PCIe interface, and uploads user data received from the wireless channel and correctly parsed to the network board through the PCIe interface;

[0028] The protocol control board interacts with the baseband board through the SRIO interface; the protocol control board transmits user data and self-organizing network protocol control data to the baseband board through the SRIO interface, and receives user data and self-organizing network protocol control data demodulated by the baseband board through the SRIO interface;

[0029] The protocol control board interacts with the test host computer through the Ethernet interface; the protocol control board transmits some key data and signals to the host computer through the Ethernet interface for debugging;

[0030] The protocol control board obtains the 5V operating voltage provided by the power board through the power interface.

[0031] Figure 2 Shown is a block diagram of a protocol control board according to a preferred embodiment of the present invention.

[0032] like Figure 2 As shown, the protocol control board of this implementation includes a protocol control module, a high-speed data interface module, a VPX connector, an external storage module, a clock management module and a power conversion module;

[0033] The protocol control module uses an FPGA chip to realize the self-organizing network function, control of the transmission protocol, generation and processing of protocol control data. The protocol control module includes a high-speed transceiver and an ARM processor;

[0034] The VPX connector is plugged into the VPX connector of the VPX backplane, that is, the protocol control board of this embodiment is connected to the VPX backplane through its VPX connector;

[0035] The protocol control module, the high-speed data interface module and the VPX connector are connected in sequence; the protocol control module performs high-speed data transmission with the network board, baseband board and radio frequency processing board on the VPX backplane through the high-speed data interface module and the VPX connector;

[0036] The external storage module is used to store the protocol control program and a large amount of high-speed data; the external storage module is connected to the protocol control module;

[0037] The clock management module is connected to the protocol control module;

[0038] The external power board provides a 5V operating voltage to the protocol control board of this embodiment through the VPX connector, and the power conversion module converts the 5V operating voltage into the operating voltage of each functional module in the protocol control board of this embodiment to supply power to each functional module.

[0039] Figure 3 Shown is a schematic diagram of a high-speed data interface module in a preferred embodiment of the present invention.

[0040] like Figure 3 The high-speed data interface module is divided into an internal interface and an external interface. The internal interface refers to the SRIO interface and the PCIe interface, and the external interface refers to the Ethernet interface and the 1553B interface. The detailed description is as follows:

[0041] The protocol control board of this embodiment adopts a 4×4 SRIO interface with a rate of 3.125 Gbps to achieve real-time high-speed transmission of large-capacity data between the protocol control module of the protocol control board of this embodiment and the baseband board;

[0042] The protocol control board of this embodiment adopts a 1×4-channel PCIe interface with a rate of 2.5 Gbps to realize real-time interaction of high-speed application data, instruction data, network status data, etc. between the protocol control module of the protocol control board of this embodiment and the network board;

[0043] The protocol control board of this embodiment adopts a 10M / 100M / 1000M Ethernet interface to realize real-time interaction of large-capacity test service data and test instruction data between the protocol control module of the protocol control board of this embodiment and the test host computer;

[0044] The protocol control board of this embodiment adopts a 1553B interface with a rate of more than 1Mbps to achieve real-time interaction of large-capacity image data between the protocol control module of the protocol control board of this embodiment and the network board; the 1553B interface is integrated with a 1553B transformer, supports 1553B direct coupling and AC coupling, supports 1Mbps communication rate, and the 1553B interface supports 3.3V single power supply, which is directly connected to the protocol control module and is suitable for space-constrained application environments such as protocol control modules.

[0045] The external storage module includes a parallel FLASH with a configuration bit width of 16 bits and a DDR3L memory with a capacity of 4Gb, see Figure 2 .

[0046] The clock management module obtains the reference clock of each functional module in the protocol control board of this embodiment, including:

[0047] Get the reference clock of the protocol control module and use the 50M reference clock provided by the active crystal oscillator to drive the work;

[0048] Get the reference clock of the SRIO interface. The reference clock of the SRIO interface uses a programmable crystal oscillator. Configure two 125M clocks according to the pins to drive the high-speed transceiver inside the protocol control module to complete the SRIO protocol transmission.

[0049] Obtain the reference clock of the PCIe interface. The reference clock of the PCIe interface is provided by the external clock source of the protocol control board through the VPX connector to provide a 100M reference clock to complete data transmission.

[0050] Figure 4 FIG. 2 is a schematic diagram of a power conversion module in a preferred embodiment of the present invention.

[0051] The power conversion module converts the input voltage of the protocol control board of this embodiment into the working voltage of each functional module in the protocol control board, where the protocol control board adopts a single +5V power supply with a maximum power of 25W. The power conversion module adopts a series of high-performance DC step-down voltage regulator modules and linear power supply modules to convert the +5V voltage into the voltage used for the normal operation of each functional module. Figure 4 , +5V is input from the power board, and the +5V is converted into 1V, 1.35V, 1.8V, 2.5V, and 3.3V through the DC step-down voltage regulator module (LMZ10505 chip). Among them, 1.35V, 1.8V, and 2.5V can be further generated into 1V, 1.2V, and 1.8V through the linear power module (TPS74401 chip). That is, the power conversion module can provide five voltages of 1V, 1.35V, 1.8V, 2.5V, 3.3V, and 1.2V.

Claims

1. A miniaturized multi-channel high-speed interface protocol control board based on VPX architecture, characterized in that: Includes protocol control module, high-speed data interface module and VPX connector; The VPX connector is plugged into the VPX connector of the VPX backplane; The protocol control module, the high-speed data interface module and the VPX connector are connected in sequence; The high-speed data interface module includes an SRIO interface, a PCIe interface, an Ethernet interface and a 1553B interface; the protocol control module interacts with the network board on the VPX backplane through the PCIe interface and the VPX connector; the protocol control module interacts with the baseband board on the VPX backplane through the SRIO interface and the VPX connector; the protocol control module interacts with the test host computer through the Ethernet interface and the VPX connector; the protocol control module interacts with the network board on the VPX backplane through the 1553B interface and the VPX connector.

2. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control module receives instructions from the network board through the PCIe interface, and feeds back instruction execution status and current network status to the network board through the PCIe interface; the protocol control board receives user data from the network board through the PCIe interface, and uploads user data received from the wireless channel and correctly parsed to the network board through the PCIe interface; the protocol control module transmits image data with the network board through the 1553B interface.

3. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control module transmits the user data and the self-organizing network protocol control data to the baseband board through the SRIO interface, and receives the user data and the self-organizing network protocol control data demodulated by the baseband board through the SRIO interface.

4. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control module transmits test service data and test instruction data to the test host computer through the Ethernet interface.

5. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control board also includes an external storage module, which is connected to the protocol control module and is used to store protocol control programs and high-speed data.

6. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 5, characterized in that: The external storage module includes a parallel FLASH supporting the BPI mode and having a configuration bit width of 16 bits and a DDR3L memory with a capacity of 4Gb.

7. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control board also includes a clock management module, which includes an active crystal oscillator and a programmable crystal oscillator. The active crystal oscillator provides a 50M reference clock as the reference clock of the protocol control module, and the programmable crystal oscillator configures two 125M clocks as the reference clock of the SRIO interface; the clock management module also obtains the 100M reference clock provided by the external clock source of the protocol control board through the VPX connector as the reference clock of the PCIe interface.

8. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control board also includes a power conversion module, which converts the working voltage of the protocol control board into the working voltage of each functional module in the protocol control board to provide power for each functional module.

9. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 8, characterized in that: The power conversion module includes a series of high-performance DC step-down voltage regulator modules and linear power supply modules.

10. The miniaturized multi-channel high-speed interface protocol control board based on VPX architecture as claimed in claim 1, characterized in that: The protocol control module adopts FPGA chip to realize the self-organizing network function, control of transmission protocol, generation and processing of protocol control data. The protocol control module includes a high-speed transceiver and an ARM processor.

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