FPGA-based airborne data transmission board and transmission method

Abstract

The application discloses a kind of based on FPGA's airborne data transmission board, including FPGA SOC chip, DDR3 memory, first Ethernet physical layer chip, second Ethernet physical layer chip, PCIe channel and protection circuit, SATA channel and protection circuit and external connector, wherein FPGA SOC chip uses DDR3 memory as the data cache of high-speed data;First Ethernet physical layer chip, second Ethernet physical layer chip pass through external connector and receive Ethernet data input FPGA SOC chip;PCIe channel and protection circuit pass through external connector and receive high-speed data input FPGA SOC chip;SATA channel and protection circuit pack high-speed data in memory and Ethernet data on FPGA SOC chip after, and store into hard disk by external connector.The application has high self-controllability and security, satisfies the product demand in industry.

Description

TECHNICAL

[0001] The application belongs to the field of data transmission and storage, and relates to an airborne data transmission board based on FPGA and a transmission method. BACKGROUND

[0002] In recent years, the airborne avionics system technology in China has developed rapidly, and the airborne avionics communication equipment undoubtedly occupies an important position in the airborne avionics system. In recent years, the airborne avionics communication equipment through the airborne avionics full-duplex communication system Ethernet switch (AFDX) based on the data exchange protocol of IEEE802.3 and ARINC664 Party standard, the rate is about 100Mb / s, which is greatly improved compared with the earlier airborne avionics communication rate. However, with the application of SATA, PCIe and other technologies in the field of airborne communication and the increasing demand of the system for data transmission rate, the original AFDX communication technology hinders the improvement of the rate and storage capacity of airborne data transmission. In recent years, through a series of measures such as independent semiconductor research and development development planning, at present, many domestic companies have released a few listed independent chip solutions which are in urgent need of verification and application. SUMMARY

[0003] The application aims to provide an airborne data transmission board based on FPGA and a transmission method of the airborne data transmission board, which can effectively improve the airborne communication rate and realize the controllability of data transmission.

[0004] The application achieves the application purpose through the following technical scheme.

[0005] An airborne data transmission board based on FPGA, comprising a FPGA SOC chip, a FLASH chip, an NVRAM chip, a DDR3 memory, a first Ethernet physical layer chip, a second Ethernet physical layer chip, a PCIe channel and protection circuit, a SATA channel and protection circuit and an external connector:

[0006] The FLASH chip is electrically connected to the PS end of the FPGA SOC chip to store a Linux system startup loader; the NVRAM chip is electrically connected to the PS end of the FPGA SOC chip to record board self-checking data and abnormal error data; part of the DDR3 memory is electrically connected to the PS end of the FPGA SOC chip to form a 32bit DDR used for system cache, and part of the DDR3 memory is electrically connected to the PL end of the FPGA SOC chip to be used as a high-speed data cache;

[0007] The FPGA SOC chip has 2 ETH ports, PCIe core ports, SATA core ports, data output ends of a first Ethernet physical layer chip and a second Ethernet physical layer chip are electrically connected with 1 ETH port respectively, data input ports are electrically connected with an external connector for receiving Ethernet data; data output ports of a PCIe channel and a protection circuit are electrically connected with a PCIe core port, data input ports are electrically connected with an external connector for receiving high-speed data; data input ports of a SATA channel and a protection circuit are electrically connected with a SATA core port, data output ports are electrically connected with an external connector for storing high-speed data in the memory and Ethernet data in the FPGA SOC chip into a hard disk after being packed.

[0008] Preferably, the first Ethernet physical layer chip is electrically connected to a PS end MIO Ethernet controller of the FPGA SOC chip, and the first Ethernet physical layer chip is electrically connected to an external connector through a network transformer in an RGMII mode.

[0009] Preferably, the FLASH chip is electrically connected to a PS end of the FPGA SOC chip in a Queued SPI mode. Part of DDR3 memories electrically connected to the PS end of the FPGA SOC chip are electrically connected to the PS end of the FPGA SOC chip in a FLY-BY topology structure.

[0010] Preferably, the airborne data transmission board card further comprises an input and output discrete quantity protection circuit, the FPGA SOC chip further comprises a PL-IO core port, a data output end of the input and output discrete quantity protection circuit is connected with the PL-IO core port, and a data input end is connected with an external connector; the FPGA SOC chip has two working states of a system working state and a monitoring working state, after the FPGA SOC chip is powered on, a system image file is started, different application programs are selected and executed according to the state of external switch discrete signals received by the input and output discrete quantity protection circuit, the system working state executes upper product application software and related driving programs, and the monitoring working state only initializes the operating system to perform board-level debugging and verification on the airborne data transmission board card.

[0011] Preferably, the airborne data transmission board card further comprises an input power conversion circuit, the input power conversion circuit is electrically connected with an external connector, converts input +12V DC power into 3.3V, 2.5V, 1.8V, 1.5V and 1.0V power signals respectively, and thus provides voltage required by the data transmission board card and working voltage of a CFast card.

[0012] Preferably, the on-board data transmission board card further comprises a JTAG plug-in electrically connected to the PS end special JTAG pin port of the FPGA SOC chip for burning system files and online debugging.

[0013] Preferably, the model of the FPGA SOC chip is FMQL45T900, the model of the FLASH chip is JFM25F128A, the model of the DDR3 memory is SM41J128M16M, the model of the JTAG plug-in is LMD-107-02-G-D, and the model of the first and second Ethernet physical layer chips is JEM88E1111HV.

[0014] According to the transmission method of the on-board data transmission board card based on the FPGA, the required high-speed data to be interacted is entered into the data transmission board card through the external connector, enters the FPGA SOC chip through the PCIe channel and the protection circuit, the PCIe controller in the FPGA SOC chip parses the message according to the PCIe interface protocol, stores the parsed data from the PL end of the FPGA SOC chip into the DDR3 memory, and then the SATA controller of the PL end packs the data stored on the DDR3 memory into SATA data according to the SATA protocol, and outputs the SATA data to the external SATA hard disk through the external connector and the SATA channel and the protection circuit; wherein the driving software on the FPGA SOC chip should configure the SATA IP address space and realize the SATA IP driving program.

[0015] According to the transmission method of the on-board data transmission board card based on the FPGA, the required high-speed data to be interacted is entered into the data transmission board card through the external connector, enters the FPGA SOC chip through the PCIe channel and the protection circuit, the PCIe controller in the FPGA SOC chip parses the message according to the PCIe interface protocol, stores the parsed data from the PL end of the FPGA SOC chip into the DDR3 memory, and then the SATA controller of the PL end packs the data stored on the DDR3 memory into SATA data according to the SATA protocol, and outputs the SATA data to the external SATA hard disk through the external connector and the SATA channel and the protection circuit; wherein the driving software on the FPGA SOC chip should configure the SATA IP address space and realize the SATA IP driving program.

[0016] The present application has the following advantages:

[0017] The present application uses the PL end high-speed IO port of the FPGA to realize the data obtained through PCIe communication and Ethernet communication of the PS end to be packed and stored on the disk through the SATA2.0 protocol, the data flow is clear, and the rate is as high as 6Gbps, and the present application uses domestic devices, has high self-controllability and safety, and meets the product demand in special industries. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating the structure of an airborne data transmission board based on an FPGA, as shown in the embodiment. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0021] This embodiment illustrates an airborne data transmission board based on an FPGA, such as... Figure 1 As shown, it includes FPGA SOC chip 1, FLASH chip 2, NVRAM chip 3, DDR3 memory 4, JTAG plug-in 5, first Ethernet physical layer chip 6, second Ethernet physical layer chip 7, PCIe channel and protection circuit 8, SATA channel and protection circuit 9, input / output discrete quantity protection circuit 10, input power conversion circuit 11, and external connector 12, etc.

[0022] As an example, in this embodiment, the FPGA SOC chip is model FMQL45T900, the FLASH chip is model JFM25F128A, the DDR3 memory is model SM41J128M16M, the JTAG plug-in is model LMD-107-02-GD, and the first Ethernet physical layer chip and the second Ethernet physical layer chip are model JEM88E1111HV.

[0023] The FPGA SOC chip includes a PS terminal and a PL terminal. The PS terminal is used for system initialization, system status monitoring, and Ethernet communication, while the PL terminal is used for PCIe, SATA, and IO port control.

[0024] The FLASH chip is electrically connected to the PS end of the FPGA SOC chip to store a Linux system startup loader. The NVRAM chip is electrically connected to the PS end of the FPGA SOC chip to record board self-check data and abnormal error data. The four DDR3 memories are electrically connected to the PS end of the FPGA SOC chip to form a 32-bit DDR for system caching, and two of the four DDR3 memories are independently electrically connected to the PL end of the FPGA SOC chip to be used as flexible high-speed signal data caching.

[0025] Preferably, the FLASH chip is electrically connected to the PS end of the FPGA SOC chip in a Queued SPI mode. The two DDR3 memories electrically connected to the PS end of the FPGA SOC chip are electrically connected to the PS end of the FPGA SOC chip in a FLY-BY topology.

[0026] The JTAG plug-in is electrically connected to the PS end of the FPGA SOC chip to burn system files and perform online debugging.

[0027] The FPGA SOC chip has two ETH ports, PCIe core ports, SATA core ports and PL-IO core ports. The data output ends of the first and second Ethernet physical layer chips are electrically connected to one ETH port, respectively, and the data input ports are electrically connected to an external connector for receiving Ethernet data. The data output ports of the PCIe channel and protection circuit are electrically connected to the PCIe core port, and the data input ports are electrically connected to an external connector for receiving high-speed data. The data input ports of the SATA channel and protection circuit are electrically connected to the SATA core port, and the data output ports are electrically connected to an external connector for storing high-speed data in the memory and Ethernet data on the FPGA SOC chip into a hard disk after packaging.

[0028] Preferably, the first Ethernet physical layer chip is electrically connected to the PS end MIO Ethernet controller of the FPGA SOC chip, and the first Ethernet physical layer chip is electrically connected to an external connector through a network transformer in an RGMII mode to realize the physical layer of the board Ethernet.

[0029] The PL-IO core port is connected to an input and output discrete quantity protection circuit. The driving design of the FPGA SOC chip has two working states: a system working state and a monitoring working state, and the two working states share the same operating system image file, and the operating system image file is started after the FPGA SOC chip is powered on, and the operating system selects to execute different application programs according to the state of the external switch discrete quantity signal, the system working state executes the upper-layer product application software and the related driving program, and the monitoring working state does not execute the upper-layer application software and the related driving program, and only initializes the operating system, so as to facilitate the board-level debugging and verification of the onboard data transmission board card and the like.

[0030] In some exemplary embodiments, the input power conversion circuit is electrically connected to the external connector, and converts the input +12V DC power into 3.3V, 2.5V, 1.8V, 1.5V, 1.0V and the like power signals respectively, so as to provide the voltage required by the data transmission board card and the working voltage of the CFast card.

[0031] Based on the above data transmission board card, the data transmission method is:

[0032] The required interactive high-speed data enters the data transmission board card through the external connector, enters the FPGA SOC chip through the PCIe channel and the protection circuit, the PCIe controller in the FPGA SOC chip analyzes the message according to the PCIe interface protocol, stores the analyzed data from the PL end of the FPGA SOC chip into the DDR3 memory, and then the SATA controller of the PL end packs the data stored on the DDR3 memory into SATA data according to the SATA protocol, and outputs the SATA data to the external SATA hard disk through the external connector, the SATA channel and the protection circuit, wherein the driving software on the FPGA SOC chip should configure the SATA IP address space, and implement the SATA IP driving program, including the comfort, BLK layer read / write and the like interface.

[0033] The required interactive Ethernet data enters the FPGA SOC chip from the external connector through the first Ethernet physical layer chip and the second Ethernet physical layer chip, wherein a low-capacitance TVS array should be used between the electrical paths of the external Ethernet signal entering the Ethernet PHY chip to cope with the phenomena of electrostatic discharge, pulse and voltage change, and then the data is analyzed by the PS end MIO controller and sent to the SATA controller through the on-chip bus, the SATA controller packs the data into SATA data according to the SATA protocol, and outputs the SATA data to the external SATA hard disk through the external connector, the SATA channel and the protection circuit.

[0034] The contents not described in detail in the present application belong to the known technology of those skilled in the art.

[0035] It can be understood that, for those ordinary skilled in the art, equivalent replacements or changes can be made according to the technical solutions and the inventive concept of the present application, and all the changes or replacements shall fall within the protection scope of the appended claims of the present application.

Claims

1. An airborne data transmission board based on FPGA, comprising an FPGA SOC chip, a FLASH chip, an NVRAM chip, DDR3 memory, a first Ethernet physical layer chip, a second Ethernet physical layer chip, a PCIe channel and protection circuit, a SATA channel and protection circuit, and an external connector, characterized in that: The FLASH chip is electrically connected to the PS terminal of the FPGA SOC chip to store the Linux system boot loading program; The NVRAM chip is electrically connected to the PS terminal of the FPGA SOC chip to record board self-test data and abnormal error data; In the DDR3 memory, a portion of the memory is electrically connected to the PS terminal of the FPGA SOC chip to form a 32-bit DDR for system cache, and a portion of the memory is electrically connected to the PL terminal of the FPGA SOC chip for high-speed data cache. The FPGA SOC chip has two ETH ports, a PCIe core port, and a SATA core port. The data output terminals of the first Ethernet physical layer chip and the second Ethernet physical layer chip are each electrically connected to one ETH port, and the data input port is electrically connected to an external connector for receiving Ethernet data. The data output port of the PCIe channel and protection circuit is electrically connected to the PCIe core port, and the data input port is electrically connected to the external connector for receiving high-speed data. The data input port of the SATA channel and protection circuit is electrically connected to the SATA core port, and the data output port is electrically connected to the external connector. It is used to package high-speed data in memory and Ethernet data on the FPGA SOC chip and store them on the hard drive. The high-speed data required for interaction enters the data transmission board through the external connector, then enters the FPGA SOC chip through the PCIe channel and protection circuit. The PCIe controller inside the FPGA SOC chip parses the message according to the PCIe interface protocol, stores the parsed data from the PL end of the FPGA SOC chip into the DDR3 memory, and then the SATA controller on the PL end packages the data stored on the DDR3 memory into SATA data according to the SATA protocol. The data is then output to the external SATA hard drive through the external connector via the SATA channel and protection circuit. The driver software on the FPGA SOC chip should configure the SATA IP address space and implement the SATA IP driver. The required Ethernet data for interaction enters the FPGA SOC chip through the external connector via the first Ethernet physical layer chip and the second Ethernet physical layer chip. Then, the PS-side MIO controller parses the data and sends it to the SATA controller via the on-chip bus. The SATA controller packages the data into SATA data according to the SATA protocol and outputs it to the external SATA hard drive through the external connector via the SATA channel and protection circuit. A low-capacitance TVS array should be used between the electrical paths of the external Ethernet signal entering the Ethernet PHY chip to provide overvoltage protection against electrostatic discharge, pulse, and transient voltage phenomena.

2. The airborne data transmission board based on FPGA according to claim 1, characterized in that... The first Ethernet physical layer chip is electrically connected to the PS-side MIO Ethernet controller of the FPGA SOC chip, and the first Ethernet physical layer chip is electrically connected to the external connector via a network transformer using the RGMII method.

3. The airborne data transmission board based on FPGA according to claim 1, characterized in that... The FLASH chip is electrically connected to the PS terminal of the FPGA SOC chip using the Queued SPI method; the DDR3 memory partially connected to the PS terminal of the FPGA SOC chip is electrically connected to the PS terminal of the FPGA SOC chip using a FLY-BY topology.

4. The airborne data transmission board based on FPGA according to claim 1, characterized in that... The airborne data transmission board also includes an input / output discrete quantity protection circuit, and the FPGA SOC chip also includes a PL-IO core port. The data output terminal of the input / output discrete quantity protection circuit is connected to the PL-IO core port, and the data input terminal is connected to the external connector. The FPGA SOC chip has two working states: system working state and monitoring working state. After the FPGA SOC chip is powered on, the operating system image file is started. The operating system selects to execute different applications according to the state of the external switch discrete quantity signals received by the input / output discrete quantity protection circuit. In the system working state, the upper-layer product application software and related drivers are executed. In the monitoring working state, only the operating system is initialized, and board-level debugging and verification of the airborne data transmission board are performed.

5. An airborne data transmission board based on FPGA according to claim 1, characterized in that... The airborne data transmission board also includes an input power conversion circuit, which is electrically connected to an external connector to convert the input +12V DC power supply into 3.3V, 2.5V, 1.8V, 1.5V, and 1.0V power signals, thereby providing the voltage required by the data transmission board and the operating voltage of the CFast card.

6. The airborne data transmission board based on FPGA according to claim 1, characterized in that... The airborne data transmission board also includes a JTAG plug-in, which is electrically connected to the dedicated JTAG pin port on the PS side of the FPGA SOC chip for programming system files and online debugging.

7. An airborne data transmission board based on FPGA according to claim 6, characterized in that... The FPGA SOC chip is model FMQL45T900, the FLASH chip is model JFM25F128A, the DDR3 memory is model SM41J128M16M, the JTAG plug-in is model LMD-107-02-GD, and the first Ethernet physical layer chip and the second Ethernet physical layer chip are model JEM88E1111HV.

Images