Display panel and display device

Abstract

The present invention discloses a display panel and a display device, which relate to the field of display technology. The display panel comprises a plurality of data lines arranged along a first direction and extending along a second direction, wherein n adjacent data lines constitute a data line group; a multiplexer circuit, wherein the multiplexer circuit comprises n output terminals, wherein n is a positive integer greater than or equal to 2; wherein one end of a data line in the data line group is electrically connected to an output terminal of the multiplexer circuit, and the other end is connected to a capacitor. The display panel of the present invention improves the crosstalk problem between data lines electrically connected to the same multiplexer circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] At present, display technology has penetrated into every aspect of people's daily life. Accordingly, more and more materials and technologies are used in display screens. As an important component of a display device, a display panel is used to realize the display function of the display device. Today, the mainstream display screens mainly include liquid crystal display panels and organic light-emitting diode (OLED).

[0003] As a current-type light-emitting device, organic light-emitting diodes have been increasingly used in high-performance displays. OLED display panels have many excellent characteristics, such as self-luminescence, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panel, rich colors, flexible display, and wide operating temperature range. Therefore, they are hailed as the next generation of "star" flat panel display technology. OLED display panels include an anode and a cathode, as well as a hole transport layer, an organic light-emitting layer, and an electron transport layer arranged between the anode and the cathode. The anode provides hole injection, and the cathode provides electron injection. Driven by external voltage, the holes and electrons injected by the cathode and the anode recombine in the organic light-emitting layer to form electron-hole pairs (i.e., excitons) at a bound energy level. The excitons radiate and de-excite to emit photons, generating visible light.

[0004] In the prior art, a display panel is provided with a plurality of data lines, and each data line is connected to a driver IC (integrated circuit) after merging at a step of the display panel. In order to reduce the number of lines at the step, a multiplexer design is usually adopted. The multiplexer can receive a data signal through one line and output the data signal to a plurality of data lines in a time-sharing manner. However, there is a serious problem of lateral crosstalk between the multiple data lines connected to the same multiplexer, which affects the display.

[0005] In view of this, there is an urgent need to provide a display panel and a display device that can improve the lateral crosstalk problem. Summary of the invention

[0006] In view of this, the present invention provides a display panel and a display device for improving the lateral crosstalk problem.

[0007] In one aspect, the present invention provides a display panel, comprising:

[0008] A plurality of data lines arranged along the first direction and extending along the second direction, wherein n adjacent data lines constitute a data line group;

[0009] A multiplexer circuit, wherein the multiplexer circuit comprises n output terminals, where n is a positive integer greater than or equal to 2;

[0010] Wherein, one end of the data line in the data line group is electrically connected to one of the output ends of the multi-way selection circuit, and the other end is connected to a capacitor.

[0011] In another aspect, the present invention provides a display device, comprising the above display panel.

[0012] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0013] In the present invention, multiple data lines in the data line group are electrically connected to the output end of the multi-way selection circuit in a one-to-one correspondence, the other end of each data line is connected to a capacitor, and each data line is loaded with multiple sub-pixels. The display panel is also provided with a first power signal line for providing high-potential signals to the sub-pixels. The n output ends of the multi-way selection circuit respectively output data voltages to multiple data lines. When the line charging of one of the data lines is completed, the data line is in a floating state. When the signal is written to another data line, the signal on the first power signal line will fluctuate due to the coupling effect, and the signal fluctuation on the first power signal line will couple the data line in the floating state. In the prior art, the coupling jump of the charged data line is ΔV'=C10 / C20, where C10 is the total capacitance of the charged data line and the first power signal line, and C20 is the total capacitance of the charged data line. After the present invention adds capacitance at the other end of the data line, the coupling jump of the charged data line is ΔV=C10 / (C20+C), where C10 is the total capacitance of the charged data line and the first power signal line, C20 is the total capacitance of the charged data line, and C is the capacitance added on the data line. Compared with the coupling jump ΔV' of the related art, after adding capacitance, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention is reduced, thereby improving lateral crosstalk and display performance.

[0014] Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0015] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0017] Figure 1 is a schematic diagram of a planar structure of a display panel in the related art;

[0018] Figure 2 is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0019] Figure 3 It is a pixel driving circuit diagram provided by the present invention;

[0020] Figure 4 is a cross-sectional view of a pixel in the present invention;

[0021] Figure 5 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0022] Figure 6 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0023] Figure 7 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0024] Figure 8 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0025] Fig. 9 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0026] Fig.10 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0027] Fig.11 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0028] Fig.12 It is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0030] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0031] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0032] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0033] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0034] In view of the fact that in the organic self-luminous display panel of the related art, the multiplexer receives the data signal through one line and outputs the data signal to multiple data lines in a time-sharing manner, but there is a serious problem of lateral crosstalk between the multiple data lines connected to the same multiplexer, the inventors have conducted the following research on the related art, referring to Figure 1 , Figure 1 is a schematic diagram of a planar structure of a display panel in the related art, Figure 1 The display panel 00 includes a display area AA' and a non-display area BB' surrounding the display area AA'. The lower frame of the non-display area BB' has a driver chip IC', which provides a display signal. The lower frame also has a multiplexer circuit 1'. The input end of the multiplexer circuit 1' is electrically connected to the driver chip IC'. The multiplexer circuit 1' has two output ends, each of which is electrically connected to a data line DATA'. Each data line DATA' carries multiple sub-pixels 2'. After using the multiplexer circuit 1', its charging method is changed from direct charging to line charging, that is, the data line DATA' is first written with a signal, and then the data line DATA' writes a signal to the sub-pixel. For each sub-pixel 2' of the organic self-luminous display panel, its driving circuit also requires a high-potential signal line PVDD'. Figure 1 There are two data lines DATA1' and data line DATA2' electrically connected to the same multiplexer circuit 1'. Of course, the display panel 00 also has scan lines (not shown in the figure). When displaying, the scan lines are scanned line by line, and the driver chip IC' sends the data voltage to the multiplexer circuit 1'. The two output ends of the multiplexer circuit 1' output the data voltage to the data line DATA1' and the data line DATA2' respectively. After the line charging of the data line DATA1' is completed, the data line DATA1' is in a floating state. When the data line DATA2' is written with a signal, the signal fluctuation on the high-potential signal line PVDD' will be caused by the coupling effect. The signal fluctuation on the high-potential signal line PVDD' will be coupled to the data line DATA1' in the floating state, which leads to a serious lateral crosstalk problem between the multiple data lines connected to the same multiplexer.

[0035] In view of this, the present invention provides a display panel and a display device to improve the problem of severe lateral crosstalk between multiple data lines connected to the same multiplexer. The specific embodiments of the display panel will be described in detail below.

[0036] Reference Figure 2 , Figure 3 and Figure 4 , Figure 2 is a schematic diagram of a planar structure of a display panel provided by the present invention, Figure 3 is a pixel driving circuit diagram provided by the present invention, Figure 4 is a cross-sectional view of a pixel in the present invention. Figure 2 The display panel 000 includes: a plurality of data lines 300 arranged along a first direction X and extending along a second direction Y, wherein n adjacent data lines 300 constitute a data line group 30; a multiplexer circuit 100, wherein the multiplexer circuit 100 includes n output terminals, where n is a positive integer greater than or equal to 2; wherein one end of the data line 300 in the data line group 30 is electrically connected to an output terminal of the multiplexer circuit 100, and the other end is connected to a capacitor C.

[0037] Specifically, Figure 2 The display panel 000 includes a display area AA and a non-display area BB surrounding the display area AA. Figure 2 Only the case where the non-display area BB completely surrounds the display area AA is shown. Of course, the non-display area BB can also partially surround the display area AA, such as a water drop screen, which is not specifically limited here. The non-display area BB includes an upper frame and a lower frame that are relatively arranged along the second direction Y. The lower frame is usually bound with a driver chip IC, which provides a signal for display. The lower frame also has a multiplexer circuit 100, and the input end of the multiplexer circuit 100 is electrically connected to the driver chip IC. Figure 2 Schematically shows a situation where the multiplexer circuit 100 has one input terminal and two output terminals, that is, the ratio of the input terminal to the output terminal is 1:2, each output terminal is electrically connected to a data line 300, and a plurality of data lines 300 are arranged along a first direction X and extend along a second direction Y. Figure 2 Two adjacent data lines 300 in the data line group 30 constitute a data line group 30, each data line 300 carries a plurality of sub-pixels 200, one end of the data line 300 in the data line group 30 is electrically connected to an output end of the multiplexer circuit 100, and the other end is connected to a capacitor C. Figure 2 The data line group 30 in the embodiment includes a data line 3001 and a data line 3002. Of course, the multiplexer circuit 100 may have one input terminal and four output terminals, that is, the ratio of the input terminal to the output terminal is 1:4, or the multiplexer circuit 100 may have one input terminal and six output terminals, that is, the ratio of the input terminal to the output terminal is 1:6.

[0038] It is understandable that the display panel 000 also has scan lines extending from the first direction X to the second direction Y, which are not shown in the figure. The scan lines and the data lines 300 intersect to define the area of ​​the sub-pixel 200 .

[0039] For the pixel driving circuit of each sub-pixel 200, each sub-pixel 200 in the display area AA of the display panel 000 includes a pixel circuit, which can be referred to Figure 3 , Figure 3 : is a pixel circuit structure diagram provided by the present invention, and the pixel circuit can be 7T1C, including: a transistor M1, a control end of which is electrically connected to a light emitting signal input end, a first end of which is electrically connected to a first power signal end PVDD, and a second end of which is electrically connected to a first end of a driving transistor M; a transistor M2, a control end of which is electrically connected to a second scanning signal input end S2, a first end of which is electrically connected to a data signal input end Vdata, and a second end of which is electrically connected to a first end of the driving transistor M; a driving transistor M, a control end of which is electrically connected to a second end of a transistor M4, and a first end of which is electrically connected to a second end of the transistor M1 and a second end of the transistor M2; a transistor M3, a control end of which is electrically connected to a second scanning signal input end S2, a first end of which is electrically connected to a second end of the transistor M4 and a second end of a storage capacitor Cst, and a second end of which is electrically connected to a second end of the driving transistor M and a first end of a transistor M5; a transistor M4, a control end of which is electrically connected to a first scanning signal input end S2, a first end of which is electrically connected to a second end of the transistor M4 and a second end of a storage capacitor Cst, and a second end of which is electrically connected to a second end of the driving transistor M and a first end of a transistor M5; A scan signal input terminal S1 is electrically connected, a first terminal is electrically connected to a reference voltage signal input terminal Vref, and a second terminal is electrically connected to a control terminal of a driving transistor M; a transistor M5, a control terminal of which is electrically connected to a light emitting signal input terminal Emit, a first terminal is electrically connected to a second terminal of the driving transistor M and a second terminal of the transistor M3, and a second terminal is electrically connected to an anode of the light emitting element O; a transistor M6, a control terminal of which is electrically connected to a second scan signal input terminal, a first terminal is electrically connected to a reference voltage signal input terminal Vref, and a second terminal is electrically connected to a first terminal of the light emitting element O; a light emitting element O, a first terminal of which is electrically connected to a second terminal of the transistor M5 and a second terminal of the transistor M6, and a second terminal is electrically connected to a second power signal terminal PVEE; a storage capacitor Cst, a first terminal of which is electrically connected to a first power signal terminal PVDD, and a second terminal of which is electrically connected to a control terminal of the driving transistor M, a first terminal of the transistor M3, and a second terminal of the transistor M4. Here, the first power signal terminal PVDD is electrically connected to the first power signal terminal PVDD. Figure 2 The first power signal line 400 is electrically connected to the first power signal line 400 in the pixel circuit, and the first power signal line 400 extends along the second direction Y and is arranged in the first direction X to transmit a high potential signal to each pixel circuit.

[0040] The display panel 000 of this embodiment may be an organic light-emitting display panel, which includes an anode and a cathode, and a light-emitting layer disposed between the anode and the cathode. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. The anode provides hole injection, and the cathode provides electron injection. Driven by an external voltage, the holes and electrons injected by the cathode and the anode recombine in the organic light-emitting layer to form electron-hole pairs (i.e., excitons) at a bound energy level. The excitons radiate and de-excite to emit photons, generating visible light. It should be noted that Figure 4 The sub-pixel 200 is the sub-pixel 200 closest to the upper frame, Figure 4 The cross-sectional view in FIG. 1 also shows the capacitor C. In this embodiment, the display panel 000 includes: a substrate 91; a thin film transistor 20 located on one side of the substrate 91; a light emitting device 30A located on the side of the thin film transistor 20 away from the substrate 91; the light emitting device 30A includes an anode layer 310, a light emitting layer 320 located on the side of the anode away from the substrate 91, and a cathode 330 located on the side of the light emitting layer 320 away from the substrate 91. The thin film transistor 20 drives the light emitting device 30A to emit light for display. Figure 4 The figure also shows a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a planarization layer 97, and a pixel definition layer 98. The thin film transistor 20 includes a second metal layer M12 (source and drain), and a first metal layer M13 is provided between the anode layer 310 and the second metal layer M12. Optionally, the thin film transistor is located on the buffer layer 92. Figure 4 In the structure description, only the top-gate thin film transistor is used as an example. The thin film transistor 20 includes a semiconductor active layer 201 located on the buffer layer 92, and the semiconductor active layer 201 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions. The region between the source region and the drain region is a channel region in which impurities are not doped. The semiconductor active layer 201 can be formed by changing amorphous silicon into polycrystalline silicon by crystallization of amorphous silicon. In order to crystallize amorphous silicon. The first metal layer M11 (gate) is located on the gate insulating layer, and the gate may include a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo) or chromium (Cr), or an alloy such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy. The first metal layer M12 has a source and a drain, and the source and the drain are electrically connected (or coupled) to the source region and the drain region of the active layer 201 respectively through contact holes, and the contact holes are formed by selectively removing the insulating layer. Figure 4Also shown is the encapsulation layer 50 located on the side of the light emitting device 30A away from the base substrate 91. The optional encapsulation layer 50 is a laminated structure of an inorganic encapsulation layer, an organic encapsulation layer and an inorganic encapsulation layer. Of course, the specific structure of the encapsulation layer 50 is not limited in the present invention. The encapsulation layer 50 can have multiple inorganic encapsulation layers and multiple organic encapsulation layers, so as to be able to provide good protection for the light emitting device 30A in the display area AA. In the present invention, a capacitor C is connected to the other end of the data line 300. Optionally, one of the two plates of the capacitor C can be set in the first metal layer M13, that is, the same layer as the data line 300. In this way, when making the data line 300, the first plate C001 of the capacitor C can be obtained by extending the length of the data line 300. The second plate C002 of the capacitor C can be set in the capacitor metal layer MC, which is the same layer as the capacitor metal layer MC, which is convenient for manufacturing.

[0041] It is understandable that after the multiplexer circuit 100 is used, the charging method is changed from direct charging to line charging, that is, the signal is first written to the data line 300, and then the data line 300 writes the signal to the sub-pixel 200. For each sub-pixel 200 of the organic self-luminous display panel 000, its driving circuit also needs a high-potential signal line. Figure 2 In the figure, there are two data lines 3001 and 3002 electrically connected to the same multiplexer circuit 100. When displaying, the scan lines are scanned line by line, and the driver chip IC sends the data voltage to the multiplexer circuit 100. The two output ends of the multiplexer circuit 100 output the data voltage to the data lines 3001 and 3002 respectively. After the data line 3001 is charged, the data line 3001 is in a floating state. When the data line 3002 is written with a signal, the coupling effect will cause the signal fluctuation on the first power signal line 400, and the signal fluctuation on the first power signal line 400 will be coupled to the data line 3001 in the floating state. In the present invention, a capacitor C is connected to the other end of the data line 300. In the related art, the coupling jump of the charged data line DATA' is ΔV'=C10 / C20, where C10 is the total capacitance C of the charged data line DATA' and the first power signal line PVDD', and C20 is the total capacitance of the charged data line DATA'. In the present invention, after the other end of the data line 300 is electrically connected to the capacitor C, the coupling jump of the charged data line 300 is ΔV=C10 / (C20+C), where C10 is the total capacitance of the charged data line 300 and the first power signal line 400, C20 is the total capacitance of the charged data line 300, and C is the capacitor C added to the data line 300. Compared with the coupling jump ΔV' of the related art, after adding the capacitor C, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention is reduced, thereby improving the lateral crosstalk and the display performance.

[0042] In some optional embodiments, continue to refer to Figure 2 , the capacitors C connected to different data lines 300 are equal.

[0043] It is understandable that in the same data line group 30, the end of each data line 300 (the end away from the multiplexer circuit 100) is connected to a capacitor C. Figure 4 One of the two plates of the capacitor C can be set in the first metal layer M13, that is, in the same layer as the data line 300. In this way, when manufacturing the data line 300, the first plate C001 of the capacitor C can be obtained by simply extending the length of the data line 300. The second plate C002 of the capacitor C can be set in the capacitor metal layer MC, in the same layer as the capacitor metal layer MC, which is convenient for manufacturing. In this embodiment, the capacitors C connected to different data lines 300 are all equal. Optionally, the sizes of the two plates of the capacitor C can be set to be the same. In this way, the two plates of the capacitor C can be etched out using the same process during manufacturing, which is convenient for manufacturing.

[0044] In some optional embodiments, referring to Figure 5 , Figure 5 3 is a schematic diagram of a planar structure of another display panel provided by the present invention. The first plate C001 of the capacitor C is connected to the data line 300 , and the second plate C002 of the capacitor C is connected to the fixed potential V.

[0045] It is understandable that the first plate C001 of the capacitor C can be directly electrically connected to the data line 300 by extending the data line 300, while the second plate C002 of the capacitor C needs to be connected to a fixed potential V. Figure 5 The second plate C002 of the capacitor C connected to different data lines 300 is respectively connected to fixed potential V01, fixed potential V02, fixed potential V03...fixed potential V08. It can be understood that the larger the capacity of the capacitor C, the smaller the coupling jump ΔV=C10 / (C20+C) of the charged data line 300, and the better it can maintain its potential holding ability. When there is a data voltage on the data line 300, the role of the fixed potential V is to maintain the potential of the data line.

[0046] In some optional embodiments, referring to Figure 6 , Figure 6 It is a schematic diagram of the planar structure of another display panel provided by the present invention, each multiplexer circuit 100 includes 1st to nth output terminals, and the capacitors C corresponding to the i-th output terminals of different multiplexer circuits 100 are connected to the same fixed potential V, where i is a positive integer greater than 1 and less than n.

[0047] Optionally, n can be a positive integer such as 2, 4, 6, etc., and the number of n is not specifically limited here. Figure 6In the example, each multiplexer circuit 100 includes the first and second output terminals. The first output terminal is electrically connected to the first data line 3001, and the other end of the first data line 3001 is connected to the first capacitor C1. The second output terminal is electrically connected to the second data line 3002, and the other end of the second data line 3002 is connected to the second capacitor C2. Each multiplexer circuit 100 includes the 1st to nth output terminals, and the capacitors C corresponding to the i-th output terminals of different multiplexer circuits 100 are connected to the same fixed potential V. The capacitors C corresponding to the 1st output terminals of multiple multiplexer circuits 100 are all connected to the same fixed potential V, and the capacitors C corresponding to the second output terminals of multiple multiplexer circuits 100 are all connected to the same fixed potential V… The capacitors C corresponding to the i-th output terminals of multiple multiplexer circuits 100 are all connected to the same fixed potential V. This can reduce the number of fixed potentials V, that is, reduce the number of signal lines transmitting the fixed potential V in the upper frame. On the one hand, it can reduce the material cost and production cost caused by setting the signal lines, and also reduce the space occupied by the signal lines in the upper frame to meet the requirements of a narrow frame.

[0048] In some optional embodiments, continue to refer to Figure 6 , n=2, the multiplexer circuit 100 includes a first output terminal and a second output terminal, the capacitors C corresponding to the first output terminals of different multiplexer circuits 100 are connected to a first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexer circuits 100 are connected to a second fixed potential V2; V1=V2.

[0049] Figure 6 The capacitors C corresponding to the first output terminals of the four multiplexer circuits 100 are all connected to the first fixed potential V1, and the capacitors C corresponding to the second output terminals of the four multiplexer circuits 100 are all connected to the second fixed potential V2, so that the number of fixed potentials V is only 2, which greatly reduces the number of signal lines transmitting the fixed potential V in the upper frame. Reducing the number of signal lines to 2 can reduce the material cost and production cost caused by setting up the signal lines, and there are only 2 signal lines, which can reduce the space occupied by the signal lines in the upper frame and meet the requirements of the narrow frame.

[0050] It can be understood that the capacitor C corresponding to the first output terminal of different multiplexer circuits 100 is connected to the first fixed potential V1, and the capacitor C corresponding to the second output terminal of different multiplexer circuits 100 is connected to the second fixed potential V2, and V1=V2, where the first fixed potential V1 and the second fixed potential V2 function to stabilize the potential of the data line 3001 and the data line 3002. It should be noted that the capacitance of the first capacitor C1 and the second capacitor C2 affects the effect of lateral crosstalk, and whether the first fixed potential V1 and the second fixed potential V2 are equal does not affect the effect of lateral crosstalk. In this embodiment, V1=V2, which can reduce the number of potentials transmitted to the signal line.

[0051] In some optional embodiments, continue to refer to Figure 6 , n=2, the multiplexer circuit 100 includes a first output terminal and a second output terminal, the capacitors C corresponding to the first output terminals of different multiplexer circuits 100 are connected to a first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexer circuits 100 are connected to a second fixed potential V2; V1≠V2.

[0052] Figure 6 The capacitors C corresponding to the first output terminals of the four multiplexer circuits 100 are all connected to the first fixed potential V1, and the capacitors C corresponding to the second output terminals of the four multiplexer circuits 100 are all connected to the second fixed potential V2, so that the number of fixed potentials V is only 2, which greatly reduces the number of signal lines transmitting the fixed potential V in the upper frame. Reducing the number of signal lines to 2 can reduce the material cost and production cost caused by setting up the signal lines, and there are only 2 signal lines, which can reduce the space occupied by the signal lines in the upper frame and meet the requirements of the narrow frame.

[0053] It can be understood that the capacitor C corresponding to the first output terminal of different multiplexer circuits 100 is connected to the first fixed potential V1, and the capacitor C corresponding to the second output terminal of different multiplexer circuits 100 is connected to the second fixed potential V2, and V1=V2, where the first fixed potential V1 and the second fixed potential V2 function to stabilize the potential of the data line 3001 and the data line 3002. It should be noted that the capacitance of the first capacitor C1 and the second capacitor C2 affects the effect of lateral crosstalk, and whether the first fixed potential V1 and the second fixed potential V2 are equal does not affect the effect of lateral crosstalk. In this embodiment, V1 is not equal to V2, which can further stabilize the potential of the data line 3001 and the data line 3002.

[0054] In some optional embodiments, referring to Figure 7 , Figure 7It is a schematic diagram of the planar structure of another display panel provided by the present invention. The multi-way selection circuit 100 includes a first transistor T1 and a second transistor T2, wherein the control end of the first transistor T1 is electrically connected to the first signal line CHK1, the first electrode of the first transistor T1 is electrically connected to the data signal end S, and the second electrode of the first transistor T1 is electrically connected to the first data line 3001 in the data line group 30; the control end of the second transistor T2 is electrically connected to the second signal line CHK2, the first electrode of the second transistor T2 is electrically connected to the data signal end S, and the second electrode of the second transistor T2 is electrically connected to the second data line 3002 in the data line group 30.

[0055] Specifically, each multiplexer circuit 100 has a first transistor T1 and a second transistor T2, the first electrodes (i.e., source electrodes) of the first transistor T1 and the second transistor T2 are both connected to the same data signal terminal S, i.e., the input terminal of the multiplexer circuit 100, and the control terminal (i.e., gate electrode) of the first transistor T1 is electrically connected to the first signal line CHK1, the second electrode (i.e., drain electrode) of the first transistor T1 is electrically connected to the first data line 3001 in the data line group 30, the control terminal (i.e., gate electrode) of the second transistor T2 is electrically connected to the second signal line CHK2, and the second electrode of the second transistor T2 is electrically connected to the second data line 3002 in the data line group 30, that is, the control terminals of the first transistor T1 and the second transistor T2 are connected to the first signal line CHK1 and the second signal line CHK2. 2 respectively control whether to be turned on or not. For example, when data needs to be written into the data line 3001, the first signal line CHK1 controls the gate of the first transistor T1 to be turned on, and the data voltage is written into the data line 3001. At this time, the second signal line CHK2 controls the gate of the second transistor T2 to be turned off, and no data voltage is written into the data line 3002. Similarly, when data needs to be written into the data line 3002, the second signal line CHK2 controls the gate of the second transistor T2 to be turned on, and the data voltage is written into the data line 3002. At this time, the first signal line CHK1 controls the gate of the first transistor T1 to be turned off, and no data voltage is written into the data line 3001. The present invention realizes that the data lines 300 in the data line group 30 are respectively written with the multiplexer circuit 100, and the number of pads on the driver chip IC can be reduced.

[0056] In some optional embodiments, referring to Figure 8 , Figure 8It is a schematic diagram of the planar structure of another display panel provided by the present invention, n=4, the multiplexer circuit 100 includes the first to fourth output terminals, the capacitor C corresponding to the first output terminal of different multiplexer circuits 100 is connected to the third fixed potential V3, the capacitor C corresponding to the second output terminal of different multiplexer circuits 100 is connected to the fourth fixed potential V4, the capacitor C corresponding to the third output terminal of different multiplexer circuits 100 is connected to the fifth fixed potential V5, and the capacitor C corresponding to the fourth output terminal of different multiplexer circuits 100 is connected to the sixth fixed potential V6; V3=V4=V5=V6.

[0057] In this embodiment, the ratio of the number of input terminals to the number of output terminals of the multiplexer circuit 100 is 1:4, that is, one input has four outputs, and can be electrically connected to four adjacent data lines 300. The capacitors C connected to the four data lines 300 are respectively a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The capacities of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be equal or unequal, which will not be described in detail here.

[0058] Figure 8 Only two multiplexer circuits 100 are schematically shown. The first capacitors C1 corresponding to the first output terminals of the two multiplexer circuits 100 are connected to the first fixed potential V1, the second capacitors C2 corresponding to the second output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V2, the third capacitors C3 corresponding to the third output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V3, and the fourth capacitors C4 corresponding to the fourth output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V4. In this way, the number of fixed potentials V is only 4, which greatly reduces the number of signal lines transmitting the fixed potential V in the upper frame. Reducing the number of signal lines to 4 can reduce the material cost and production cost caused by setting the signal lines. In addition, since there are only 4 signal lines, the space occupied by the signal lines in the upper frame can be reduced to meet the requirements of a narrow frame.

[0059] It can be understood that the first capacitor C1 corresponding to the first output terminal of different multiplexer circuits 100 is connected to the third fixed potential V3, the second capacitor C2 corresponding to the second output terminal of different multiplexer circuits 100 is connected to the fourth fixed potential V4, the third capacitor C3 corresponding to the third output terminal of different multiplexer circuits 100 is connected to the fifth fixed potential V5, and the fourth capacitor C4 corresponding to the fourth output terminal of different multiplexer circuits 100 is connected to the sixth fixed potential V6. Here, the function of the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5 and the sixth fixed potential V6 is to stabilize the potentials of the first data line 3001, the second data line 3002, the third data line 3003 and the fourth data line 3004. It should be noted that what affects the lateral crosstalk effect is the capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. Whether the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are equal has no effect on the lateral crosstalk effect. In this embodiment, V3=V4=V5=V6, which can reduce the number of potentials transmitted to the signal line.

[0060] In some optional embodiments, continue to refer to Figure 8 , n=4, the multiplexer circuit 100 includes the 1st to 4th output terminals, the capacitor corresponding to the 1st output terminal of different multiplexer circuits 100 is connected to the third fixed potential V3, the capacitor corresponding to the 2nd output terminal of different multiplexer circuits 100 is connected to the fourth fixed potential V4, the capacitor corresponding to the 3rd output terminal of different multiplexer circuits 100 is connected to the fifth fixed potential V5, and the capacitor corresponding to the 4th output terminal of different multiplexer circuits 100 is connected to the sixth fixed potential V6; at least two of V3, V4, V5 and V6 are not equal.

[0061] Figure 8 Only two multiplexer circuits 100 are schematically shown. The first capacitors C1 corresponding to the first output terminals of the two multiplexer circuits 100 are connected to the first fixed potential V1, the second capacitors C2 corresponding to the second output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V2, the third capacitors C3 corresponding to the third output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V3, and the fourth capacitors C4 corresponding to the fourth output terminals of the two multiplexer circuits 100 are connected to the second fixed potential V4. In this way, the number of fixed potentials V is only 4, which greatly reduces the number of signal lines transmitting the fixed potential V in the upper frame. Reducing the number of signal lines to 4 can reduce the material cost and production cost caused by setting the signal lines. In addition, since there are only 4 signal lines, the space occupied by the signal lines in the upper frame can be reduced to meet the requirements of a narrow frame.

[0062] It can be understood that the first capacitor C1 corresponding to the first output terminal of different multiplexer circuits 100 is connected to the third fixed potential V3, the second capacitor C2 corresponding to the second output terminal of different multiplexer circuits 100 is connected to the fourth fixed potential V4, the third capacitor C3 corresponding to the third output terminal of different multiplexer circuits 100 is connected to the fifth fixed potential V5, and the fourth capacitor C4 corresponding to the fourth output terminal of different multiplexer circuits 100 is connected to the sixth fixed potential V6. Here, the function of the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5 and the sixth fixed potential V6 is to stabilize the potentials of the first data line 3001, the second data line 3002, the third data line 3003 and the fourth data line 3004. It should be noted that the capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 affects the effect of lateral crosstalk. Whether the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are equal has no effect on the effect of lateral crosstalk. In this embodiment, at least two of V3, V4, V5, and V6 are not equal. Optionally, V3≠V4=V5=V6, or V3=V4≠V5=V6, or V3=V4=V5≠V6, or V3≠V4≠V5=V6, or V3=V4=V5≠V6, or V3≠V4≠V5≠V6. It will not be repeated here. In this embodiment, at least two of V3, V4, V5, and V6 are not equal, which can stabilize the potentials of data lines 3001, 3002, 3003, and 3004.

[0063] In some optional embodiments, referring to Fig. 9 , Fig. 9 is a schematic diagram of a planar structure of another display panel provided by the present invention, Fig. 9The multiplexer circuit 100 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, wherein the control end of the third transistor T3 is electrically connected to the third signal line CHK3, the first electrode of the third transistor T3 is electrically connected to the data signal end S, and the second electrode of the third transistor T3 is electrically connected to the first data line 3001 in the data line group 30; the control end of the fourth transistor T4 is electrically connected to the fourth signal line CHK4, the first electrode of the fourth transistor T4 is electrically connected to the data signal end S, and the second electrode of the fourth transistor T4 is electrically connected to the first data line 3001 in the data line group 30; The first electrode of the fifth transistor T5 is electrically connected to the data signal terminal S, and the second electrode of the fifth transistor T5 is electrically connected to the third data line 3003 in the data line group 30; the control end of the sixth transistor T6 is electrically connected to the sixth signal line CHK6, the first electrode of the sixth transistor T6 is electrically connected to the data signal terminal S, and the second electrode of the sixth transistor T6 is electrically connected to the fourth data line 3004 in the data line group 30.

[0064] Fig. 9 In the embodiment, the ratio of the number of input terminals to the number of output terminals of the multiplexer circuit 100 is 1:4, that is, one input has four outputs, and can be electrically connected to four adjacent data lines 300. The capacitors C connected to the four data lines 300 are respectively a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The capacities of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be equal or unequal, which will not be described in detail here.

[0065] Specifically, each multiplexer circuit 100 has a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, the first electrodes (i.e., sources) of the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all connected to the same data signal terminal S, i.e., the input terminal of the multiplexer circuit 100, and the control terminal (i.e., gate) of the third transistor T3 is electrically connected to the third signal line CHK3, the second electrode (i.e., drain) of the third transistor T3 is electrically connected to the first data line 3001 in the data line group 30, and the control terminal (gate) of the fourth transistor T4 is electrically connected to the fourth signal line CHK 4, the second electrode (drain) of the fourth transistor T4 is electrically connected to the second data line 3002 in the data line group 30, that is, the control ends of the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are respectively controlled to be turned on or off by the third signal line CHK3, the fourth signal line CHK4, the fifth signal line CHK5 and the sixth signal line CHK6. For example, when data needs to be written to the data line 3001, the third signal line CHK3 controls the gate of the third transistor T3 to be turned on, and the data voltage is written to the data line 3001. At this time, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to be turned off, and the fourth signal line CHK5 controls the gate of the fourth transistor T4 to be turned on. The fifth signal line CHK5 controls the fifth transistor T5 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off, and no data voltage is written into the data line 3002, no data voltage is written into the data line 3003, and no data voltage is written into the data line 3004; similarly, when data line 3002 needs to be written, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to be turned on, and the data voltage is written into the data line 3002. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fifth signal line CHK5 controls the fifth transistor T5 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3003, and no data voltage is written to the data line 3004; when data needs to be written to the data line 3003, the fifth signal line CHK5 controls the gate of the fifth transistor T5 to be turned on, and the data voltage is written to the data line 3003. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fourth signal line CHK4 controls the fourth transistor T4 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off, and no data voltage is written to the data line 3001, no data voltage is written to the data line 3002, and no data voltage is written to the data line 3004;When data needs to be written to the data line 3004, the sixth signal line CHK6 controls the gate of the sixth transistor T6 to be turned on, and the data voltage is written to the data line 3004. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fourth signal line CHK4 controls the fourth transistor T4 to be turned off, and the fifth signal line CHK5 controls the fifth transistor T5 to be turned off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3002, and no data voltage is written to the data line 3003. The present invention realizes data writing to the data lines 300 in the data line group 30 respectively through the multiplexer circuit 100, and can reduce the number of pads on the driver chip IC. ;

[0066] In some optional embodiments, continue to refer to Fig. 9 , Fig. 9 The display panel 000 also includes a plurality of sub-pixels 200 arranged in an array. In each data line group 30, the first data line 3001 and the third data line 3003 are electrically connected to the sub-pixels 200 in odd columns, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in even columns.

[0067] Specifically, each data line 300 is electrically connected to the sub-pixels 200 in the same column to transmit data voltages to the sub-pixels 200 in the column.

[0068] Fig. 9When data needs to be written to the data line 3001, the third signal line CHK3 controls the gate of the third transistor T3 to be turned on, the data voltage is written to the data line 3001, and the sub-pixels 200 in the first column are charged. At this time, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to be turned off, the fifth signal line CHK5 controls the fifth transistor T5 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off. No data voltage is written to the data line 3002, no data voltage is written to the data line 3003, and no data voltage is written to the data line 3004. The sub-pixels 200 in the second to fourth columns are not charged. Similarly, the data line 3002 needs to be turned on. When data is written, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to be turned on, the data voltage is written into the data line 3002, and the second column of sub-pixels 200 are charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fifth signal line CHK5 controls the fifth transistor T5 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off. No data voltage is written into the data line 3001, no data voltage is written into the data line 3003, and no data voltage is written into the data line 3004. The first column of sub-pixels 200, the third column of sub-pixels 200, and the fourth column of sub-pixels 200 are not charged. The data line 300 When data needs to be written, the fifth signal line CHK5 controls the gate of the fifth transistor T5 to be turned on, the data voltage is written into the data line 3003, and the sub-pixel 200 in the third column is charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fourth signal line CHK4 controls the fourth transistor T4 to be turned off, and the sixth signal line CHK6 controls the sixth transistor T6 to be turned off. No data voltage is written into the data line 3001, no data voltage is written into the data line 3002, and no data voltage is written into the data line 3004. The sub-pixels 200 in the first column, the sub-pixels 200 in the second column, and the sub-pixels 200 in the fourth column are not charged. When data needs to be written to data line 3004, the sixth signal line CHK6 controls the gate of the sixth transistor T6 to be turned on, the data voltage is written to the data line 3004, and the fourth column of sub-pixels 200 is charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to be turned off, the fourth signal line CHK4 controls the fourth transistor T4 to be turned off, and the fifth signal line CHK5 controls the fifth transistor T5 to be turned off. No data voltage is written to data line 3001, no data voltage is written to data line 3002, and no data voltage is written to data line 3003. The first column of sub-pixels 200, the second column of sub-pixels 200, and the third column of sub-pixels 200 are not charged.

[0069] In some optional embodiments, referring to Fig.10 and Fig.11 , Fig.10 is a schematic diagram of a planar structure of another display panel provided by the present invention, Fig.11is a schematic diagram of a planar structure of another display panel provided by the present invention, Fig.10 and Fig.11 The display panel 000 also includes a plurality of sub-pixels 200 arranged in an array, and the first data line 3001 and the second data line 3002 of each data line group 30 are electrically connected to the sub-pixels 200 in the same column, and the third data line 3003 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the same column, and the first data line 3001 and the third data line 3003 are electrically connected to the sub-pixels 200 in odd rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in even rows; or the first data line 3001 and the third data line 300 in each data line group 30 are electrically connected to the sub-pixels 200 in even rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in odd rows.

[0070] In this embodiment, Fig.10 and Fig.11 In the embodiment, the ratio of the number of input terminals to the number of output terminals of the multiplexer circuit 100 is 1:4, that is, one input has four outputs, and can be electrically connected to four adjacent data lines 300. The capacitors C connected to the four data lines 300 are respectively the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. The capacities of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be equal or unequal, which will not be described in detail here. In this embodiment, a dual-gate arrangement design is adopted at the same time. Fig.10 In the example, in each data line group 30, the first data line 3001 and the second data line 3002 are electrically connected to the sub-pixels 200 in the same column, the third data line 3003 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the same column, and the first data line 3001 and the third data line 3003 are electrically connected to the sub-pixels 200 in odd rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in even rows. The same data line 300 only transmits data voltage to the sub-pixels 200 in odd rows or even rows, which can increase the charging time of the sub-pixels 200 and improve the display performance. Fig.11 In each data line group 30, the first data line 3001 and the third data line 300 are electrically connected to the sub-pixels 200 in the even rows, the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the odd rows, and the same data line 300 only transmits data voltage to the sub-pixels 200 in the odd rows or the even rows, which can increase the charging time of the sub-pixels 200 and improve the display performance.

[0071] In some optional embodiments, continue to refer to Figure 2, the input terminals of different multiplexer circuits 100 are connected to different data signal terminals S.

[0072] Figure 2 The four multiplexer circuits 100 are respectively connected to the data signal terminal S1, the data signal terminal S2, the data signal terminal S3 and the data signal terminal S4. The four data signal terminals S can be four pads on the driver chip IC. Different data voltages are provided to the multiple multiplexer circuits 100 through the driver chip IC, thereby realizing displays with different brightness.

[0073] In some alternative embodiments, please refer to Fig.12 , Fig.12 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 0000 provided in this embodiment includes the display panel 000 provided in the above embodiment. Fig.12 The embodiment only takes a mobile phone as an example to illustrate the display device 0000. It can be understood that the display device 0000 provided in the embodiment of the present invention can be a computer, a television, a car display device or other display device 0000 with a display function, and the present invention does not specifically limit this. The display device 0000 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0074] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0075] In the present invention, multiple data lines in the data line group are electrically connected to the output end of the multi-way selection circuit in a one-to-one correspondence, the other end of each data line is connected to a capacitor, and each data line is loaded with multiple sub-pixels. The display panel is also provided with a first power signal line for providing a high-potential signal to the sub-pixels. The n output ends of the multi-way selection circuit respectively output data voltages to multiple data lines. When the line charging of one of the data lines is completed, the data line is in a floating state. When the signal is written to another data line, the signal on the first power signal line will fluctuate due to the coupling effect, and the signal fluctuation on the first power signal line will be coupled to the data line in the floating state. In the prior art, the coupling jump of the charged data line is ΔV'=C10 / C20, where C10 is the total capacitance of the charged data line and the first power signal line, and C20 is the total capacitance of the charged data line. After the present invention adds capacitance at the other end of the data line, the coupling jump of the charged data line is ΔV=C10 / (C20+C), where C10 is the total capacitance of the charged data line and the first power signal line, C20 is the total capacitance of the charged data line, and C is the capacitance added on the data line. Compared with the coupling jump ΔV' of the related art, after adding capacitance, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention is reduced, thereby improving lateral crosstalk and display performance.

[0076] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of data lines arranged along the first direction and extending along the second direction, wherein n adjacent data lines constitute a data line group; A multiplexer circuit, wherein the multiplexer circuit comprises n output terminals, where n is a positive integer greater than or equal to 2; One end of the data line in the data line group is electrically connected to one of the output ends of the multi-way selection circuit, and the other end is connected to a capacitor; the first plate of the capacitor is connected to the data line, and the second plate of the capacitor is connected to a fixed potential; Each multiplexer circuit includes 1st to nth output terminals, and capacitors corresponding to i-th output terminals of different multiplexer circuits are connected to the same fixed potential, where i is a positive integer greater than 1 and less than n.

2. The display panel according to claim 1, characterized in that: The capacitances connected to different data lines are equal.

3. The display panel according to claim 1, characterized in that: n=2, the multiplexer circuit includes a first output terminal and a second output terminal, the capacitors corresponding to the first output terminals of different multiplexer circuits are connected to a first fixed potential V1, and the capacitors corresponding to the second output terminals of different multiplexer circuits are connected to a second fixed potential V2; V1=V2.

4. The display panel according to claim 1, characterized in that: n=2, the multiplexer circuit includes a first output terminal and a second output terminal, the capacitors corresponding to the first output terminals of different multiplexer circuits are connected to a first fixed potential V1, and the capacitors corresponding to the second output terminals of different multiplexer circuits are connected to a second fixed potential V2; V1≠V2.

5. The display panel according to claim 3 or 4, characterized in that: The multiplexer circuit includes a first transistor and a second transistor, wherein: The control end of the first transistor is electrically connected to the first signal line, the first electrode of the first transistor is electrically connected to the data signal end, and the second electrode of the first transistor is electrically connected to the first data line in the data line group; The control terminal of the second transistor is electrically connected to the second signal line, the first electrode of the second transistor is electrically connected to the data signal terminal, and the second electrode of the second transistor is electrically connected to the second data line in the data line group.

6. The display panel according to claim 1, characterized in that: n=4, the multiplexer circuit includes the first to fourth output terminals, the capacitors corresponding to the first output terminals of different multiplexer circuits are connected to the third fixed potential V3, the capacitors corresponding to the second output terminals of different multiplexer circuits are connected to the fourth fixed potential V4, the capacitors corresponding to the third output terminals of different multiplexer circuits are connected to the fifth fixed potential V5, and the capacitors corresponding to the fourth output terminals of different multiplexer circuits are connected to the sixth fixed potential V6; V3=V4=V5=V6.

7. The display panel according to claim 1, characterized in that: n=4, the multiplexer circuit includes the first to fourth output terminals, the capacitors corresponding to the first output terminals of different multiplexer circuits are connected to the third fixed potential V3, the capacitors corresponding to the second output terminals of different multiplexer circuits are connected to the fourth fixed potential V4, the capacitors corresponding to the third output terminals of different multiplexer circuits are connected to the fifth fixed potential V5, and the capacitors corresponding to the fourth output terminals of different multiplexer circuits are connected to the sixth fixed potential V6; At least two of V3, V4, V5 and V6 are not equal.

8. The display panel according to claim 7, characterized in that: The multi-way gating circuit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein: The control terminal of the third transistor is electrically connected to the third signal line, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third transistor is electrically connected to the first data line in the data line group; The control terminal of the fourth transistor is electrically connected to the fourth signal line, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second data line in the data line group; The control terminal of the fifth transistor is electrically connected to the fifth signal line, the first electrode of the fifth transistor is electrically connected to the data signal terminal, and the second electrode of the fifth transistor is electrically connected to the third data line in the data line group; The control terminal of the fifth transistor is electrically connected to the sixth signal line, the first electrode of the sixth transistor is electrically connected to the data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fourth data line in the data line group.

9. The display panel according to claim 8, characterized in that: The display panel also includes a plurality of sub-pixels arranged in an array. The first and third data lines in each data line group are electrically connected to the sub-pixels in odd columns, and the second and fourth data lines are electrically connected to the sub-pixels in even columns.

10. The display panel according to claim 8, characterized in that: The display panel also includes a plurality of sub-pixels arranged in an array, wherein the first data line and the second data line of each data line group are electrically connected to the sub-pixels in the same column, the third data line and the fourth data line are electrically connected to the sub-pixels in the same column, and the first data line and the third data line are electrically connected to the sub-pixels in odd rows, and the second data line and the fourth data line are electrically connected to the sub-pixels in even rows; or the first data line and the third data line of each data line group are electrically connected to the sub-pixels in even rows, and the second data line and the fourth data line are electrically connected to the sub-pixels in odd rows.

11. The display panel according to claim 1, characterized in that: The input terminals of different multiplexer circuits are connected to different data signal terminals.

12. A display device, characterized in that: A display panel comprising any one of claims 1 to 11.

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