A method of generating a static optimal voltage value table

Abstract

The application discloses a method for generating a static optimal voltage value table, which summarizes all factors affecting NAND from the initial stage to the end of the service life of SSD, accelerates the wear of multiple SSDs to observe the changes experienced by NAND from the initial stage to the end of the service life of SSD, mixes other influencing factors at a certain service life period, reads all page data in each block using different NAND voltages, and uniformly analyzes the optimal voltage value under the condition. The above process is repeated to find the optimal voltage value under any condition. The application obtains an optimal voltage value table through simulating the actual running environment of the SSD and collecting a large amount of data in the block, and the SSD looks up the corresponding voltage value in the static table according to the current environment to perform error correction processing, reduces the system resource demand, simplifies the firmware operation process, and improves the system read performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a method for generating a static optimal voltage value table. BACKGROUND

[0002] NAND Flash will generate more error bits due to voltage offset when reading in different environments because of its own storage unit characteristics, so using appropriate voltage reading becomes a method to eliminate the impact. Static generation of appropriate voltage table is beneficial to reduce CPU resources and software design.

[0003] The static generation method forms a voltage value table that can be searched according to the influence conditions according to the optimal voltage value of NAND Flash in various environments of SSD, which is represented as a multi-dimensional array in the program. The voltage value of this method is suitable for most blocks and is easy to use, which is beneficial to improve the reading performance of SSD; but it requires accurate simulation environment, enough Block testing, and multiple verifications. SUMMARY

[0004] The technical problem to be solved by the present application is to improve a method for generating a static optimal voltage value table. Based on the method, a voltage value table suitable for most blocks under various influence factors is generated, system resource consumption is reduced, and reading performance is improved.

[0005] To solve the technical problem, the technical solution adopted by the present application is: a method for generating a static optimal voltage value table, comprising the following steps:

[0006] S01), wear a plurality of SSDs, and apply other factors affecting nand at each life stage of each SSD;

[0007] S02), read all blocks at different voltages of NAND using shift read command under each life stage and other influence factors; count the total number of data 0, the total number of data 1, the total number of data 0 to data 1, and the total number of errors in each page of data, to obtain all data information of the block;

[0008] S03), uniformly analyze all data information of the block obtained in step S02), specifically analyze the number of data 0 to data 1 and the total number of errors, and find the total number of data 0 to data 1 and the total number of data 1 to data 0 according to the voltage change, when both are flat, it is the best voltage value suitable for the block;

[0009] S04), analyze all block data by step S03) to obtain the best voltage value of each block under various influence factors at each life stage;

[0010] S05), aggregate the best voltage value of all blocks in each condition of each life stage, find the best voltage value that fits all blocks, so as to obtain the best voltage value under the condition;

[0011] S06), draw a two-dimensional table by combining each influencing factor of each life stage and the best voltage value found in S05), with the abscissa being the life stage and the ordinate being other influencing factors, to generate an optimal voltage value table.

[0012] Further, in step S02), the voltage of the read block is determined according to the chip manual.

[0013] Further, the voltage of the read block is ±32.

[0014] Further, the optimal voltage value table is a universal voltage value table.

[0015] Further, it further includes step S07): sampling verification, randomly selects a block under a certain simulation environment within the current test data, and verifies whether the finally selected voltage value meets the requirements.

[0016] Further, it further includes step S07): complete verification, reselects multiple blocks to perform environmental simulation again, uses the selected voltage value for reading after reaching the specified conditions, checks whether the number of error bits meets the requirements, and finally performs real disk verification in the SSD.

[0017] Further, the other influencing factors include data residence time, read-write interference, and temperature span.

[0018] The present application has the following advantages: through the method described in the patent, the optimal voltage value table can be obtained through a large number of block data collection in the simulation of the actual running environment of the SSD, the corresponding voltage value in the static table is found according to the current environment in the SSD for error correction processing, the system resource demand is reduced, the firmware operation process is simplified, and the system read performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Flowchart for the method described in Example 1;

[0020] Figure 2 Schematic diagram of the static voltage value table generated in Example 1. DETAILED DESCRIPTION

[0021] The present application will be further described below in conjunction with the drawings and specific embodiments.

[0022] Example 1

[0023] This embodiment discloses a method for generating a static optimal voltage value table, as shown inFigure 1 As shown, comprising the following steps:

[0024] S01), wear a plurality of SSDs, at each life stage of each SSD, other factors affecting nand are applied;

[0025] S02), at each life stage (every thousand times of wear or finer granularity) and other influencing factors, use shiftread command to read all blocks at different NAND voltages; Count the total number of data 0, the total number of data 1, the total number of data 0 to data 1, and the total number of errors in each page of data, so as to obtain all data information of the block;

[0026] The data unit 4KB is also used to collect data in this step, but the data volume will be 4 times the page unit.

[0027] S03), uniformly analyze all data information of the block obtained in step S02), specifically analyze the number of data 0 to data 1 and the total number of errors, find the total number of data 0 to data 1 and the total number of data 1 to data 0 according to the voltage change, and when the two are balanced, it is the best voltage value suitable for the block;

[0028] S04), analyze all block data in step S03) to obtain the best voltage value of each block under various influencing factors at each life stage;

[0029] S05), summarize the best voltage value of all blocks under each condition at each life stage, find the best voltage value suitable for all blocks, and thus obtain the best voltage value under the condition;

[0030] S06), combine each life stage and the best voltage value found in S05) with each influencing factor to draw a two-dimensional table, with the horizontal coordinate being the life stage and the vertical coordinate being the other influencing factors, to generate an optimal voltage value table.

[0031] As Figure 2 shown, a schematic diagram of the static optimal voltage value table generated by the present embodiment, with the horizontal coordinate being the life and the vertical coordinate being the data residence time. According to the actual test conditions, it can be listed as a three-dimensional table or other more complex data forms. When used, the best voltage value can be obtained by directly looking up the table according to the environment of the SSD to read.

[0032] In the present embodiment, the voltage for reading the block is determined according to the chip manual, which can be taken as ±32.

[0033] In this embodiment, the generated optimal voltage value table is a universal voltage value table, which is a voltage value table that is applicable to multiple NAND chips and meets at least 99.99% of the total number of data units (4KB is generally used as a data unit in an SSD) and is the optimal voltage value table. This requirement is to reduce the number of times of entering soft resolution to improve the read performance.

[0034] In this embodiment, other influencing factors include data residence time, read-write interference, and temperature span, and the universal voltage table needs to meet all these conditions.

[0035] The method also includes a system verification step, which includes sampling verification and complete verification. The sampling verification is to randomly select a Block under a certain simulation environment in the current test data to verify whether the finally selected voltage value meets the requirements. The complete verification is to select a large number of Blocks again to perform environment simulation, and after reaching the specified conditions, read using the selected voltage value to check whether the number of error bits meets the requirements, and finally perform real disk verification in the SSD.

[0036] In this embodiment, the complete verification method is used, that is, according to step S01), environment simulation is performed again, and the optimal voltage value set found is used to read data at each sampling point to verify whether the number of error bits caused by each optimal voltage value meets the system error correction requirement. If not, the values close to the optimal voltage value are offset to obtain new voltage values. It is suggested to perform 2 to 3 verification processes to obtain the final optimal voltage value table.

[0037] The above description is only the basic principle and preferred embodiment of the present application, and the improvements and substitutions made by those skilled in the art based on the present application belong to the protection scope of the present application.

Claims

1. A method of generating a static optimal voltage value table, characterized by: Comprising the following steps: S01), wear a plurality of SSDs, at each life stage of each SSD, other factors affecting nand are applied; S02), under each life stage and other influencing factors, use shift read command to read all blocks at different NAND voltages; count the total number of data 0, the total number of data 1, the total number of data 0 to data 1, and the total number of errors in each page of data, so as to obtain all data information of the block; S03), uniformly analyze all data information of the block obtained in step S02), specifically analyze the number of data 0 to data 1 and the total number of errors, find the total number of data 0 to data 1 and the total number of data 1 to data 0 according to the change of voltage, and when the two are equal, it is the best voltage value suitable for the block; S04), analyze all block data in step S03) to obtain the best voltage value of each block under various influencing factors at each life stage; S05), summarize the best voltage value of all blocks under each condition at each life stage, find the best voltage value suitable for all blocks, so as to obtain the best voltage value under the condition; S06), combine each life stage and each influencing factor with the best voltage value found in S05) to draw a two-dimensional table, with the horizontal coordinate being the life stage and the vertical coordinate being the other influencing factors, to generate an optimal voltage value table.

2. The method of claim 1, wherein: In step S02), the voltage for reading the block is determined according to the chip manual.

3. The method of claim 2, wherein: The voltage for reading the block is ±32.

4. The method of claim 1, wherein: The optimal voltage value table is a universal voltage value table.

5. The method of claim 1, wherein: It also includes step S07): sampling verification, randomly select a block under a certain simulation environment in the current test data to verify whether the finally selected voltage value meets the requirements.

6. The method of claim 1, wherein: It also includes step S07): complete verification, select a plurality of blocks again to simulate the environment, and use the selected voltage value to read after reaching the specified conditions to check whether the number of error bits meets the requirements, and finally perform real disk verification in the SSD.

7. The method of claim 1, wherein: Other influencing factors include data residence time, read-write interference, and temperature span.

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