SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation and preparation method and application thereof

Abstract

A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation and its preparation method and application. The present application belongs to the technical field of multifunctional optoelectronic transistors. The purpose of the present application is to solve the technical problem that the heat-activated carriers of the existing tunneling field effect transistor are greatly affected by the environment and have a short service life. The tunneling field effect transistor of the present application uses graphene nanosheet / h-BN nanosheet as the top gate, SiO2 / Si as the bottom gate, and SnS2 / MoSe2 as the heterojunction. Method: First, obtain SnS2, MoSe2, h-BN, graphene nanosheet on the bottom gate by mechanical exfoliation method; then transfer MoSe2, h-BN, graphene nanosheet onto SnS2 nanosheet in sequence by dry transfer method; then evaporate metal bonding layer / Au electrode layer to obtain gate, drain and source, and obtain tunneling field effect transistor after annealing. It is applied to the field of logic circuit components.

Description

Technical Field

[0001] This invention belongs to the field of multifunctional electronic transistor technology, specifically relating to a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control, its fabrication method, and its application. Background Technology

[0002] With the rapid development of information technology, electronic products have come into our view, and people have increasingly higher requirements for the informatization, intelligence, and integration of electronic products. Integrated circuit products have become indispensable items in our daily lives. With the continuous miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs), various electronic products are becoming smaller, faster, and more precise.

[0003] MOSFETs have matured significantly in the semiconductor field, but their high leakage current and subthreshold swing limit their performance in energy saving and low power consumption. Furthermore, according to Moore's Law, the number of transistors that can be placed on an integrated circuit roughly doubles every 18-24 months. The International Semiconductor Technology Roadmap predicts that MOSFET miniaturization will continue until 2026, meaning MOSFETs are approaching the limits of Moore's Law. Therefore, there is an urgent need for a replacement for MOSFETs, and tunneling field-effect transistors (TENTs) have emerged to meet this need.

[0004] Tunneling field-effect transistors (TFETs) have attracted widespread attention as novel devices due to their band-to-band tunneling mechanism. When the device is turned on, charge carriers are transported through band-to-band tunneling, and the current is primarily tunneling current. Band-to-band tunneling refers to the tunneling of electrons between the valence band of the source region and the conduction band of the channel region. For N-type TFETs, electron tunneling is inter-band tunneling, unaffected by hot electron emission, and without the Fermi tail effect. Therefore, the subthreshold swing can be less than 60 mV / dec. Furthermore, the TFET structure is similar to that of a MOSFET, belonging to the field-effect transistor family, and can be fabricated using some traditional processes, making it significant for research and offering broad prospects.

[0005] Quantum tunneling-based field-effect transistors (FETs) bypass traditional thermally excited current conduction, utilizing tunneling current to avoid the energy loss required for carriers to overcome potential barriers. By reducing the amplitude of the energy barrier, enhancing and utilizing quantum effects becomes possible, thus significantly reducing the energy required for electrons to cross the barrier and consequently reducing transistor power consumption. Tunneling field-effect transistors (TFETs) developed using the quantum tunneling effect promise to reduce chip power consumption to one percent (1 / 10). However, traditional single-gate controlled TFETs face limitations in material selection due to their singular control methods, hindering research in traditional semiconductors. The search for more suitable band structures necessitates the emergence of newer materials, thus significantly impeding the development of tunneling transistors.

[0006] Two-dimensional transition metal dichalcogenides (TMDs) constitute a large branch of the two-dimensional materials family [ACCNano, 2014, 8(2): 1102-1120.]. These materials can be broadly classified into semiconductor materials and metallic materials, represented by SnS2 and MoSe2, respectively. MoSe2 is a typical TMD material with a layered structure, where layers are loosely bonded and stacked together by van der Waals forces, exhibiting an indirect bandgap. Its bandgap changes with the number and thickness of the layers; when thinned from a bulk state to a single layer, it transitions from an indirect bandgap structure to a direct bandgap structure. For example, MoS2, WS2, and WSe2 are direct bandgap semiconductors in their single-layer state, while they exhibit indirect bandgap characteristics in their multilayer or bulk states. This unique electronic property makes it a promising candidate for applications in the semiconductor device field.

[0007] Group IV two-dimensional metal monosulfides have a similar structure to black phosphorus, but their stability is significantly higher. Group IV two-dimensional metal monosulfides MXs (M=Ge, Sn; X=S, Se) have shown great application potential in recent years, attracting interest from engineering, materials science, and physics. MXs are a class of semiconductor two-dimensional materials with a wrinkled honeycomb structure similar to black phosphorus (band gap range of 1.3-2.4 eV) and possess many excellent properties [Journal of Applied Physics, 2015, 117(6): 065103][Physical Review B, 2015, 92(11):115202][Nature, 2014, 508(7496): 373]. In addition to their excellent performance in optoelectronics, photovoltaics, and piezoelectric fields, MXs, as sensor materials, also have ultra-high thermoelectric figure of merit and the possibility of realizing topological crystalline insulators, and can also carry in-plane ferroelectricity in ultrathin layered materials. Furthermore, MXs also hold great promise for applications in solar cells and energy storage materials. MXs have become one of the most popular research topics in condensed matter physics, chemistry, materials science, and nanotechnology.

[0008] In current social science research, TFET transistors based on dual-gate control are existing methods and strategies. For example, patent CN201910518172.0 discloses a lightly doped tunneling field-effect transistor and its fabrication method based on germanium-silicon heterojunction and dual-gate technology. It is based on first-generation semiconductor germanium-silicon. Due to its own semiconductor properties, thermally excited carriers are greatly affected by the environment and have a short lifespan. Therefore, it has great limitations in the practical application of field transistors. Summary of the Invention

[0009] The purpose of this invention is to solve the technical problems of existing tunneling field-effect transistors (TSTs) where thermally excited carriers are greatly affected by the environment and the lifespan is short. The invention provides a tunneling field-effect transistor based on a dual-gate controlled SnS2 / MoSe2 heterojunction, its fabrication method, and its application.

[0010] The present invention discloses a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control, which uses graphene nanosheets / h-BN nanosheets as the top gate and SiO2 / Si as the bottom gate. The SnS2 / MoSe2 heterojunction is located between h-BN and SiO2. In the heterojunction, the SnS2 nanosheets and MoSe2 nanosheets partially overlap, and the overlapping area is the depletion region.

[0011] Further specified, the thickness of SnS2 nanosheets is 5-300 nm, the thickness of MoSe2 nanosheets is 10-70 nm, the thickness of h-BN nanosheets is 10-150 nm, and the thickness of graphene nanosheets is 5-70 nm.

[0012] Further specifying, the graphene nanosheets have a gate electrode, the SnS2 nanosheets in the non-depletion region have a drain electrode, and the MoSe2 nanosheets in the non-depletion region have a source electrode.

[0013] Furthermore, the gate, drain, and source electrodes are made of the same material, which is a metal bonding layer / Au electrode layer.

[0014] Furthermore, the metal bonding layer is made of Cr or Ti.

[0015] Furthermore, the thickness of the metal bonding layer is 3-10 nm, and the thickness of the Au electrode layer is 20-100 nm.

[0016] The fabrication method of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control according to the present invention is carried out according to the following steps:

[0017] Step 1: SnS2 nanosheets, MoSe2 nanosheets, h-BN nanosheets, and graphene nanosheets were obtained on the cleaned SiO2 / Si substrate by mechanical exfoliation.

[0018] Step 2: Using a dry transfer method, MoSe2 nanosheets are transferred onto SnS2 nanosheets, so that the MoSe2 nanosheets and SnS2 nanosheets partially overlap. The mixture is then annealed under an inert gas atmosphere to form a SnS2 / MoSe2 heterojunction.

[0019] Step 3: Using a dry transfer method, h-BN nanosheets and graphene nanosheets are sequentially transferred onto the SnS2 / MoSe2 heterojunction, and then annealed under inert gas protection to form the top gate.

[0020] Step 4: The gate, drain, and source are obtained by vapor deposition on graphene nanosheets, SnS2 nanosheets in the non-depletion region, and MoSe2 nanosheets in the non-depletion region, respectively. After annealing under inert gas protection, a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control is obtained.

[0021] Further specify the cleaning process in step 1: sonicate with acetone, isopropanol, and deionized water for 10 minutes each, and then dry with nitrogen.

[0022] Further specifying, in step 1, mechanical peeling is performed using adhesive tape, and after completion, the residue is removed by soaking in acetone.

[0023] Further specify that the annealing temperature in steps 2-3 is 100-150 ℃ and the time is 0.3-2 h.

[0024] Further specifying, the annealing temperature in step 4 is 150-300 ℃, and the time is 0.3-2 h.

[0025] Further specifying, the inert gas in steps 2-4 is N2 or Ar.

[0026] The present invention relates to a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control, which is applied in the field of logic circuit components.

[0027] The significant advantages of this invention compared to existing technologies are:

[0028] This application utilizes two different group IV-VI compound field-effect transistors, exhibiting a typical type III band structure. It overcomes the limitations inherent in first-generation semiconductors, and through the action of tunneling carriers, avoids the instability of device current caused by changes in external ambient temperature. This results in higher carrier mobility and a wider range of applications. Specific advantages are as follows:

[0029] 1) This invention relates to a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control. This device features low-bias control and utilizes ultrathin graphene nanosheets and h-BN nanosheets to maintain significant control while ensuring the device's transparency. It represents a novel van der Waals heterojunction tunneling field-effect transistor structure that addresses key scientific issues in this field, such as the limited control methods in the single-gate control process, which imposes strict requirements on the band alignment of the two materials (typically considered to have a conduction band to valence band difference of around 0.2 eV). Dual-gate control is proposed, adding top-gate control to the existing bottom-gate control. The top and bottom gates work together to generate a larger band shift in the semiconductor material, thus reducing the limitations on band requirements and allowing for greater material selection.

[0030] 2) This invention uses graphene nanosheets and h-BN nanosheets as top gates and SiO2 / Si-based as bottom gates, enabling TFET structure devices to have both macroscopic and microscopic control methods, expanding the bandgap control range and reducing the inherent limitations of bandgap matching caused by the construction of TFET devices.

[0031] 3) The tunneling field-effect transistor based on the dual-gate control SnS2 / MoSe2 heterojunction of the present invention belongs to the type II band control type III band arrangement, which maintains the inherent high electron mobility and gate voltage controllability of MoSe2, and can also realize two charge transport mechanisms: direct tunneling and Fowler-Nordheim tunneling. Attached Figure Description

[0032] Figure 1 af is a flowchart and overall planar structure diagram of the tunneling field-effect transistor based on the dual-gate control SnS2 / MoSe2 heterojunction in Example 1; wherein 1-Si, 2-SiO2, 3-SnS2, 4-MoSe2, 5-h-BN, 6-graphene, 7-metal bonding layer / Au electrode layer.

[0033] Figure 2 An optical microscope image of the tunneling field-effect transistor based on a dual-gate controlled SnS2 / MoSe2 heterojunction in Example 1.

[0034] Figure 3 The image shows the Raman characterization of the junction region of the tunneling field-effect transistor based on the dual-gate controlled SnS2 / MoSe2 heterojunction in Example 1, measured under a 532 nm laser.

[0035] Figure 4 The output curve of the tunneling field-effect transistor based on the dual-gate controlled SnS2 / MoSe2 heterojunction in Example 1 is shown in the fitting of the FNT and DT tunneling formulas.

[0036] Figure 5a This is the energy band diagram of the device when both the top and bottom gate biases are 0.

[0037] Figure 5b The top gate voltage V TG <0 V and bottom gate voltage V BG Device band structure diagram at >0 V;

[0038] Figure 5c The top gate voltage V peak1 >V TG >0 V and bottom gate voltage V peak2 <V BG Device band structure diagram at <0 V;

[0039] Figure 5d The top gate voltage V TG >V peak1 With bottom gate voltage V BG <V peak2 The device's band structure schematic at that time;

[0040] Figure 6 The curves show the device current transfer as the bottom gate changes under different top gate voltages when the source-drain voltage V=2 V.

[0041] Figure 7a The top gate voltage V TGOutput curves showing the device current versus source-drain voltage at different bottom gate voltages when the gate voltage is 1.5 V;

[0042] Figure 7b The bottom gate voltage V BG Output curves showing the variation of device current with source-drain at different top gate voltages when the voltage is 40 V. Detailed Implementation

[0043] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0044] Specific Implementation Method 1: In this implementation method, a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control uses graphene nanosheets / h-BN nanosheets as the top gate and SiO2 / Si as the bottom gate. The SnS2 / MoSe2 heterojunction is located between h-BN and SiO2. In the heterojunction, the SnS2 nanosheets and MoSe2 nanosheets partially overlap, and the overlapping area is the depletion region. The gate is provided on the graphene nanosheets, the drain is provided on the SnS2 nanosheets in the non-depletion region, and the source is provided on the MoSe2 nanosheets in the non-depletion region.

[0045] The SnS2 nanosheets have a thickness of 5-300 nm, the MoSe2 nanosheets have a thickness of 10-70 nm, the h-BN nanosheets have a thickness of 10-150 nm, and the graphene nanosheets have a thickness of 5-70 nm.

[0046] The gate, drain, and source electrodes are made of the same material, namely a metal bonding layer / Au electrode layer. The metal bonding layer is made of Cr or Ti and has a thickness of 3-10 nm. The Au electrode layer has a thickness of 20-100 nm.

[0047] The method for fabricating the above-mentioned SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control is carried out according to the following steps:

[0048] Step 1: Place the SiO2 / Si substrate (e.g., Figure 1 (As shown in a) SnS2 nanosheets were sequentially ultrasonicated with acetone, isopropanol, and deionized water for 10 minutes each, then dried with a nitrogen gun, and finally mechanically peeled off with adhesive tape to obtain SnS2 nanosheets on the cleaned SiO2 / Si substrate. Figure 1 (as shown in b) MoSe2 nanosheets, h-BN nanosheets, and graphene nanosheets were then immersed in acetone to remove residual adhesive. SnS2 nanosheets with a thickness of 5-300 nm, MoSe2 nanosheets with a thickness of 10-70 nm, h-BN nanosheets with a thickness of 10-150 nm, and graphene nanosheets with a thickness of 5-70 nm were selected using an optical microscope.

[0049] Step 2: MoSe2 nanosheets are transferred onto SnS2 nanosheets using a three-dimensional micro-region transfer platform and PVA method, resulting in partial overlap between the MoSe2 and SnS2 nanosheets. The nanosheets are then annealed at 150 °C for 0.5 h under nitrogen or argon protection to enhance the contact between them and remove small molecules and other impurities at the interface, forming a SnS2 / MoSe2 van der Waals heterostructure (e.g., ...). Figure 1 (as described in c)

[0050] Step 3: h-BN nanosheets and graphene nanosheets were sequentially transferred onto the SnS2 / MoSe2 heterojunction using a three-dimensional micro-region transfer platform and PVA method. Annealing was performed at 150 °C for 0.5 h under nitrogen or argon protection to enhance the contact between the two nanosheets and remove small molecules and other impurities at the interface, forming the top gate (e.g., ...). Figure 1 (as shown in de);

[0051] Step 4: Using a maskless ultraviolet lithography system, a metal bond layer / Au electrode layer is deposited on graphene nanosheets to obtain the gate electrode, on SnS2 nanosheets in the non-depletion region to obtain the drain electrode, and on MoSe2 nanosheets in the non-depletion region to obtain the source electrode. Annealing is then performed at 150 °C for 0.5 h under nitrogen or argon protection to improve the contact quality between the electrodes and the graphene, SnS2, and MoSe2 van der Waals heterojunctions and reduce the contact barrier, resulting in a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control (e.g., Figure 1 (as shown in f).

[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0053] Unless otherwise specified, the experimental methods used in the following examples are conventional methods. Unless otherwise specified, the materials, reagents, methods, and instruments used are all conventional materials, reagents, methods, and instruments in the art, and can be obtained commercially by those skilled in the art.

[0054] The terms “comprising,” “including,” “having,” “containing,” or any other variations thereof, as used in the following embodiments, are intended to cover a non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such a composition, step, method, article, or apparatus.

[0055] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1 to 5” is disclosed, the described range should be interpreted as including ranges “1 to 4”, “1 to 3”, “1 to 2”, “1 to 2 and 4 to 5”, “1 to 3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range. In this specification and claims, range definitions may be combined and / or interchanged, unless otherwise stated, these ranges include all subranges contained therein.

[0056] The indefinite articles “a” and “an” preceding an element or component of this invention do not impose any limitation on the quantity (i.e., number of times) of the element or component. Therefore, “an” or “a” should be interpreted as including one or at least one, and the singular form of an element or component also includes the plural form, unless the quantity clearly refers only to the singular form.

[0057] Example 1: Combination Figure 1 and Figure 2 In this embodiment, a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control uses graphene nanosheets / h-BN nanosheets as the top gate and SiO2 / Si as the bottom gate. The SnS2 / MoSe2 heterojunction is located between h-BN and SiO2. In the heterojunction, SnS2 nanosheets and MoSe2 nanosheets partially overlap, and the overlapping area is the depletion region. The gate is provided on the graphene nanosheets, the drain is provided on the SnS2 nanosheets in the non-depletion region, and the source is provided on the MoSe2 nanosheets in the non-depletion region.

[0058] The SnS2 nanosheets have a thickness of 15 nm, the MoSe2 nanosheets have a thickness of 15 nm, the h-BN nanosheets have a thickness of 30 nm, and the graphene nanosheets have a thickness of 10 nm.

[0059] The gate, drain, and source electrodes are made of the same material, namely a metal Cr bonding layer / Au electrode layer, with a metal Cr bonding layer thickness of 10 nm and an Au electrode layer thickness of 50 nm.

[0060] The method for fabricating the above-mentioned SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control is carried out according to the following steps:

[0061] Step 1: Place the SiO2 / Si substrate (e.g., Figure 1(As shown in a) SnS2 nanosheets were sequentially ultrasonicated with acetone, isopropanol, and deionized water for 10 minutes each, then dried with a nitrogen gun, and finally mechanically peeled off with adhesive tape to obtain SnS2 nanosheets on the cleaned SiO2 / Si substrate. Figure 1 (as shown in b), MoSe2 nanosheets, h-BN nanosheets, and graphene nanosheets were then immersed in acetone to remove residual adhesive. 15 nm thick SnS2 nanosheets, 15 nm thick MoSe2 nanosheets, 30 nm thick h-BN nanosheets, and 10 nm thick graphene nanosheets were selected using an optical microscope.

[0062] Step 2: MoSe2 nanosheets were transferred onto SnS2 nanosheets using a three-dimensional micro-region transfer platform and PVA method, resulting in partial overlap between the MoSe2 and SnS2 nanosheets. The nanosheets were then annealed at 150 °C for 0.5 h under nitrogen protection to enhance the contact between the two nanosheets and remove small molecules and other impurities at the interface, forming a SnS2 / MoSe2 van der Waals heterostructure (e.g., ...). Figure 1 (as described in c)

[0063] Step 3: h-BN nanosheets and graphene nanosheets were sequentially transferred onto the SnS2 / MoSe2 heterojunction using a three-dimensional micro-region transfer platform and PVA method. Under nitrogen protection, the nanosheets were annealed at 150 °C for 0.5 h to enhance the contact between the two layers and remove small molecules and other impurities at the interface, forming the top gate (e.g., ...). Figure 1 (as shown in de);

[0064] Step 4: Using a maskless ultraviolet lithography system, a metal Cr bond layer / Au electrode layer is deposited on graphene nanosheets to obtain the gate electrode, a metal Cr bond layer / Au electrode layer is deposited on SnS2 nanosheets in the non-depletion region to obtain the drain electrode, and a metal Cr bond layer / Au electrode layer is deposited on MoSe2 nanosheets in the non-depletion region to obtain the source electrode. Under nitrogen protection, the electrodes are annealed at 150 °C for 0.5 h to improve the contact quality between the electrodes and the graphene, SnS2, and MoSe2 van der Waals heterojunction and to reduce the contact barrier, thus obtaining a SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control (e.g., Figure 1 (as shown in f).

[0065] Figure 1 The flowchart and planar structure diagram of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control prepared in Example 1 are shown.

[0066] Figure 2 An optical microscope image of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor fabricated for Example 1, based on dual-gate control. From... Figure 2It can be seen that different materials are held together by van der Waals forces, and the order from bottom to top is as follows: SnS2 nanosheets, MoSe2 nanosheets, h-BN nanosheets, and graphene nanosheets.

[0067] Figure 3 The junction region of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control prepared in Example 1 was characterized by Raman spectroscopy measurements using a 532 nm laser. It can be seen that Raman peaks of MoSe2, SnS2, SiO2, graphene, and h-BN were measured sequentially in the junction region.

[0068] Figure 4 This is a comparison chart showing the fitted IV characteristic curves of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control prepared in Example 1. The fitting formulas are as follows:

[0069] (1)

[0070] (2)

[0071] Figure 5 is a device band diagram of the SnS2 / MoSe2 heterojunction tunneling field-effect transistor based on dual-gate control prepared in Example 1. Figure 5a This is the energy band diagram of the device when both the top and bottom gate biases are 0. Figure 5b The top gate voltage V TG <0 V and bottom gate voltage V BG Device band structure schematic at >0 V Figure 5c The top gate voltage V peak1 >V TG >0 V and bottom gate voltage V peak2 <V BG Device band structure schematic at <0 V Figure 5d The top gate voltage V TG >V peak1 With bottom gate voltage V BG <V peak2 The device's energy band structure is shown in Figure 5. As can be seen from Figure 5, this invention utilizes the energy band structure of SnS2 and MoSe2 to construct band-to-band tunneling and form a tunneling current.

[0072] Figure 6 This is the device current transfer curve as a function of the bottom gate at different top gate voltages when the source-drain voltage V = 2 V. Figure 6 It can be seen that the device has different threshold voltages under different top gate control, and when the top gate is fixed, the device has good bottom gate control effect.

[0073] Figure 7a The top gate voltage V TGAt a voltage of 1.5 V, the output curves showing the device current versus source-drain voltage at different gate bottom voltages reveal significant changes in current due to varying gate bottom voltages. Furthermore, when the gate bottom voltage V... TG When the current is -40 V, it can be seen that the current first increases and then decreases, which is consistent with the band diagram analyzed in Figure 5.

[0074] Figure 7b The bottom gate voltage V BG At 40 V, the output curves showing the changes in device current with source-drain variation under different top gate voltages show that the device has different current magnitudes at the same voltage under different top gate voltages. As the top gate voltage increases, the device current decreases, demonstrating good control performance.

[0075] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on dual-gate regulation, characterized in that, The transistor is top-gated with graphene nanosheet / h-BN nanosheet, bottom-gated with SiO2 / Si, and has SnS2 / MoSe2 heterojunction between h-BN and SiO2, with the SnS2 nanosheet and MoSe2 nanosheet partially overlapping in the heterojunction, and the overlapping part being a depletion region. 2.The SnS 2 / MoSe 2 heterojunction tunneling field effect transistor based on double-gate regulation according to claim 1, wherein The thickness of the SnS2 nanosheet is 5-300 nm, the thickness of the MoSe2 nanosheet is 10-70 nm, the thickness of the h-BN nanosheet is 10-150 nm, and the thickness of the graphene nanosheet is 5-70 nm. 3.The SnS 2 / MoSe 2 heterojunction tunneling field effect transistor based on double-gate regulation according to claim 1, wherein The graphene nanosheet is provided with a gate electrode, the SnS2 nanosheet in the non-depletion region is provided with a drain electrode, and the MoSe2 nanosheet in the non-depletion region is provided with a source electrode, and the gate electrode, the drain electrode and the source electrode are made of the same material, which is a metal adhesive layer / Au electrode layer. 4.The SnS 2 / MoSe 2 heterojunction tunneling field effect transistor based on double-gate regulation according to claim 3, wherein, The metal adhesive layer is made of Cr or Ti. 5.The SnS 2 / MoSe 2 heterojunction tunneling field effect transistor based on double-gate regulation according to claim 3, wherein, The thickness of the metal adhesive layer is 3-10 nm, and the thickness of the Au electrode layer is 20-100 nm.

6. The preparation method of a double-gate regulated SnS2 / MoSe2 heterojunction tunneling field effect transistor according to any one of claims 1-5, characterized in that, The method is performed according to the following steps: Step 1: Obtain SnS2 nanosheet, MoSe2 nanosheet, h-BN nanosheet and graphene nanosheet on the cleaned SiO2 / Si substrate by mechanical exfoliation; Step 2: Transfer the MoSe2 nanosheet to the SnS2 nanosheet by dry transfer, so that the MoSe2 nanosheet and the SnS2 nanosheet partially overlap, and then anneal under inert gas protection to form a SnS2 / MoSe2 heterojunction; Step 3: Transfer the h-BN nanosheet and the graphene nanosheet to the SnS2 / MoSe2 heterojunction in sequence by dry transfer, and then anneal under inert gas protection to form a top gate; Step 4: Obtain a gate electrode, a drain electrode and a source electrode on the graphene nanosheet, the SnS2 nanosheet in the non-depletion region and the MoSe2 nanosheet in the non-depletion region respectively by evaporation, and then anneal under inert gas protection to obtain a SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation.

7. The method for preparing a dual-gate regulated SnS2 / MoSe2 heterojunction tunneling field effect transistor according to claim 6, wherein, The cleaning process in step 1: ultrasonic cleaning with acetone, isopropanol and deionized water for 10 min each, and then nitrogen blowing.

8. The method for preparing a dual-gate regulated SnS2 / MoSe2 heterojunction tunneling field effect transistor according to claim 6, wherein, Mechanical exfoliation is performed by using adhesive tape in step 1, and acetone is used for soaking after completion to remove residual adhesive.

9. The method for preparing a dual-gate regulated SnS2 / MoSe2 heterojunction tunneling field effect transistor according to claim 6, wherein, The annealing temperature in steps 2-3 is 100-150 ℃, the time is 0.3-2 h, the annealing temperature in step 4 is 150-300 ℃, the time is 0.3-2 h, and the inert gas in steps 2-4 is N2 or Ar.

10. A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation according to any one of claims 1-5 is applied to the field of logic circuit components.

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