A method, unit and security chip circuit for controlling encryption and decryption speed

Abstract

The present application discloses an encryption and decryption speed control method, unit, and security chip circuit. The method first obtains a preset number of computing clock cycles N required to complete a ghash function multiplication operation; then, based on the data length L of the multiplier X and the multiplicand Y involved in the ghash function multiplication operation and the number of computing clock cycles N, obtains the number of parallel computing bits M required when performing the ghash function multiplication operation in parallel, and the value P of the number of MUX stages required for the parallel computing bit M; finally, the MUX with the value of the stage P is set to complete the ghash function multiplication operation of the multiplier X and the multiplicand Y to obtain the product Z. Because the ghash function multiplication operation is performed in parallel, the speed of the ghash function multiplication operation is controllable, thereby achieving controllable encryption and decryption speed.

Description

Technical Field

[0001] The present invention relates to the field of information security and integrated circuit technology, and in particular to an encryption and decryption speed control method, unit and security chip circuit. Background Art

[0002] With the rapid development of security chip technology, its application areas are expanding, gradually integrating into people's daily lives. Providing differentiated and personalized services to users has become a key research direction for security chip manufacturers. For example, manufacturers need to set different security encryption and decryption processing speeds based on user levels, just as mobile operators set different data transmission speeds based on customer wireless data usage.

[0003] Current data encryption technology can be divided into private key encryption (symmetric encryption) and public key encryption (asymmetric encryption) based on the type of encryption key. Symmetric encryption algorithms are a more traditional encryption system, in which both communicating parties use a single shared key for encryption and decryption. Due to their algorithmic simplicity and high encryption speed, they remain one of the mainstream cryptographic systems. Block ciphers within symmetric encryption are characterized by high speed, ease of standardization, and ease of hardware and software implementation. They are often the core system for implementing data encryption, digital signatures, authentication, and key management in information and network security, and are widely used in computer communications and information system security. GCM is a block cipher algorithm that uses universal hashing to provide authenticated encryption in any binary Galois field. GCM includes two basic operations: authenticated encryption and authenticated decryption, which constitute its entire functionality. The key to implementing the GCM encryption algorithm lies in the design and implementation of the AES algorithm and the GHASH function. Therefore, the GHASH function is the most important component of the GCM encryption algorithm. The main research direction of this application is to control the data encryption and decryption speed through hardware implementation of the GHASH function. Summary of the Invention

[0004] The main technical problem solved by the present invention is how to control the encryption and decryption speed based on the hardware implementation of ghash function operation.

[0005] According to the first aspect, an embodiment provides an encryption and decryption speed control method, wherein the encryption and decryption method is implemented based on ghash function calculations, and the encryption and decryption speed control method includes:

[0006] Get the preset number of computing clock cycles N required to complete a multiplication operation of the ghash function;

[0007] Obtaining, based on the data length L of the multiplier X and the multiplicand Y involved in the multiplication operation of the ghash function and the number N of calculation clock cycles, a number M of parallel calculation bits required for performing the ghash function multiplication operation in a parallel manner;

[0008] Obtaining a value P of the number of MUX stages required to complete the ghash function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M;

[0009] The number of stages of the MUX used for the ghash function multiplication operation is set to a value P, and the ghash function multiplication operation of the multiplier X and the multiplicand Y is performed to obtain a product Z.

[0010] According to the second aspect, an embodiment provides a computer-readable storage medium, on which a program is stored. The program can be executed by a processor to implement the encryption and decryption speed control method as described in the first aspect.

[0011] According to the third aspect, an embodiment provides an encryption / decryption speed control unit, including:

[0012] A speed setting module, configured to set the number of computing clock cycles N required to complete a multiplication operation of a ghash function according to a preset encryption and decryption speed;

[0013] A bit number acquisition module is used to obtain the number of parallel calculation bits M required for performing the ghash function multiplication operation in parallel based on the data length L of the multiplier X and the multiplicand Y participating in the multiplication operation of the ghash function and the number of calculation clock cycles N;

[0014] A value setting module, configured to obtain a value P of the number of MUX stages required to complete the ghash function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M;

[0015] The encryption and decryption calculation module is used to select a MUX with a level of value P to complete the multiplication operation of the multiplier X and the multiplicand Y using the ghash function to obtain the product Z.

[0016] According to a fourth aspect, an embodiment provides a security chip circuit, comprising the encryption and decryption speed control unit described in the third aspect, wherein the encryption and decryption speed control unit is configured to control the speed at which the security chip circuit performs encryption and decryption calculations.

[0017] According to the security chip circuit of the above embodiment, the encryption and decryption calculation speed of the security chip circuit is controlled by controlling the number of computing clock cycles required for the multiplication operation of the GHASH function. Therefore, different encryption and decryption speeds can be corresponding to different encryption and decryption level information, thereby achieving the purpose of achieving different performance of the security chip circuit according to different user levels, thereby making it possible to provide users with differentiated personalized services. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a structural block diagram of a security chip circuit in one embodiment;

[0019] Figure 2 The figure is a flow chart of a method for controlling encryption and decryption speed in an embodiment. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0021] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0022] Component numbers used herein, such as "first" and "second," are used solely to distinguish the components being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" in this application, unless otherwise specified, include both direct and indirect connections (couplings).

[0023] The multiplication operation of the GHASH function is not a traditional multiplication operation, but only defines the shift and XOR operations as multiplication.

[0024] The multiplication operation of the GHASH function is defined as:

[0025] Z=X*Y;

[0026] Initial value: Z=0, V=X;

[0027] ;

[0028] ;

[0029] Where LSB (Vi) represents the rightmost end of Vi, R is a constant, ">>" represents right shift, and i<128.

[0030] According to the above formula, if single-bit serial calculation is used, then calculating the multiplication operation of the 128-bit Ghash function requires 128 computing clock cycles.

[0031] Currently, there's no solution to accelerate and optimize GHASH multiplication operations. For example, in AES-128, existing technologies require 128 clock cycles to complete a single GHASH multiplication operation. This can be considered a serial operation, meaning that the hardware implementation of GHASH multiplication requires 128 clock cycles to complete a single GHASH multiplication operation. This significantly limits the encryption and decryption speed of security chips, thereby reducing their performance.

[0032] In an embodiment of the present application, the multiplication operation of the GHASH function is designed to be implemented in a parallel operation mode instead of a serial operation mode, that is, a multiplication operation of the GHASH function is completed by simultaneously calculating multiple bits of data in a parallel manner within a small number of calculation clock cycles. Taking AES-128 as an example, it is set to calculate 16 bits of data in parallel within 8 calculation clock cycles to complete a multiplication operation of the Ghash function. The use of a parallel operation mode can not only greatly improve the speed of the multiplication operation of the GHASH function, but also make the number of calculation clock cycles required to complete a multiplication operation of the GHASH function adjustable. Based on the characteristic that the number of calculation clock cycles required for the multiplication operation of the GHASH function is adjustable, an encryption and decryption speed control method is also disclosed in an embodiment of the present application, which realizes the adjustable encryption and decryption speed of the security chip circuit by setting the number of calculation clock cycles required to complete a multiplication operation of the GHASH function.

[0033] Example 1:

[0034] Please refer to Figure 1, is a structural block diagram of a security chip circuit in an embodiment, which includes a level acquisition unit 10, an encryption speed setting unit 20, and an encryption / decryption speed control unit 30. The level acquisition unit 10 is used to obtain encryption / decryption level information from a preset cloud server and send the obtained encryption / decryption level information to the encryption speed setting unit 20. The encryption speed setting unit 20 is used to use the obtained encryption / decryption level information as the preset encryption / decryption level information, and then set the encryption / decryption calculation speed based on the preset encryption / decryption level information, and send the set encryption / decryption calculation speed value to the encryption / decryption speed control unit 30. Different encryption / decryption level information corresponds to different encryption / decryption calculation speeds. The encryption / decryption speed control unit 30 is used to control the speed at which the security chip circuit performs encryption / decryption calculations based on the encryption / decryption calculation speed set by the encryption speed setting unit 20.

[0035] In one embodiment, the encryption / decryption level information is obtained from the data to be encrypted / decrypted downloaded from the cloud server.

[0036] In one embodiment, obtaining encryption and decryption level information includes: first obtaining the ID information of the security chip circuit and sending the ID information to the cloud server; then receiving the encryption and decryption level information sent back by the cloud server, wherein the encryption and decryption level information is obtained by the cloud server based on the user level information corresponding to the ID information. The higher the user level, the higher the level of the encryption and decryption level information, and the higher the level of the encryption and decryption level information, the faster the set encryption and decryption calculation speed.

[0037] In an embodiment of the present application, the encryption / decryption speed control unit 30 controls the speed of encryption / decryption calculations performed by the security chip circuit by setting the number of computing clock cycles required to complete a GHASH function multiplication operation. In one embodiment, the encryption / decryption speed control unit 30 includes a speed setting module 31, a bit number acquisition module 32, a value setting module 33, and an encryption / decryption calculation module 34. The speed setting module 31 is configured to set the number of computing clock cycles N required to complete a GHASH function multiplication operation based on a preset encryption / decryption speed. The bit number acquisition module 32 is configured to determine the number of parallel computing bits M required for parallel GHASH function multiplication based on the data length L of the multiplier X and the multiplicand Y involved in the GHASH function multiplication operation and the number of computing clock cycles N. The value setting module 33 is configured to determine the number of MUX stages P required to complete the GHASH function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel computing bits M. The encryption / decryption calculation module 34 is configured to select a MUX with the number of stages P to complete the GHASH function multiplication operation of the multiplier X and the multiplicand Y, thereby obtaining the product Z. Among them, the preset number of computing clock cycles N required to complete a multiplication operation of the ghash function is negatively correlated with the encryption and decryption speed, that is, the faster the preset encryption and decryption speed, the smaller the set number of computing clock cycles N required. In one embodiment, the MUX is integrated on the security chip and is constructed in the form of a NAND gate on the security chip. The computing clock cycle required for the multiplication operation involving the ghash function can also be obtained in reverse according to the number of parallel calculation bits in the parallel calculation mode, that is, the number of computing clock cycles required for a multiplication operation is limited by setting the number of parallel calculation bits. The number of parallel calculation bits can be achieved by setting parameters and macro definitions on the security chip circuit to achieve the purpose of achieving the number of parallel calculation bits. Specifically, it can be constructed by the logic NAND gate circuit of the security chip.

[0038] Please refer to Figure 2 , is a flow chart of an encryption and decryption speed control method in an embodiment. This application also discloses a decryption speed control method applied to the security chip circuit described above. The encryption and decryption method of the security chip circuit is implemented based on ghash function calculations. The encryption and decryption speed control method includes:

[0039] Step 101: Obtain the number N of computing clock cycles.

[0040] A preset number of computing clock cycles N required to complete a multiplication operation of a ghash function is obtained. The preset number of computing clock cycles N required to complete a multiplication operation of a ghash function is negatively correlated with the encryption and decryption speed.

[0041] Step 102: Obtain the number of parallel computing bits M.

[0042] The number of parallel computation bits M required for performing the ghash function multiplication in parallel is obtained based on the data lengths L of the multiplier X and the multiplicand Y involved in the ghash function multiplication operation and the number of computation clock cycles N. In one embodiment, the number of parallel computation bits M is obtained based on a table comparing computation clock cycles to required parallel computation bits, wherein the table comparing computation clock cycles to required parallel computation bits is obtained based on a correspondence between the data lengths L of the multiplier X and the multiplicand Y and the number of parallel computation bits M when completing a single ghash function multiplication operation in parallel within a preset number of computation clock cycles N.

[0043] In one embodiment, the table comparing the calculation clock cycle and the number of bits required for parallelism is as follows:

[0044] Calculate the number of clock cycles N The number of parallel calculation bits M 128 1 64 2 32 4 16 8 8 16 4 32 2 64 1 128

[0045] Step 103: Obtain the value P of the MUX stage.

[0046] A value P of the number of MUX stages required to complete the ghash function multiplication operation is obtained based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M. In one embodiment, the value P of the number of MUX stages required to complete the ghash function multiplication operation is obtained based on a table comparing the number of parallel calculation bits and the number of stages, wherein the table comparing the number of parallel calculation bits and the number of stages is obtained based on a correspondence between the number of parallel calculation bits M and the number of MUX stages required to complete a ghash function multiplication operation in parallel within a preset number of calculation clock cycles N.

[0047] In one embodiment, the table comparing the number of parallel calculation bits and the number of levels is as follows:

[0048] The number of parallel calculation bits M The value P of the MUX stage 1 2 2 4 4 8 8 16 16 32 32 64 64 128 128 256

[0049] Step 104, completing the multiplication operation of the ghash function.

[0050] The number of stages of the MUX for the ghash function multiplication operation is set to a value P, and the ghash function multiplication operation of the multiplier X and the multiplicand Y is performed to obtain the product Z.

[0051] The security chip circuit disclosed in the embodiments of the present application includes a level acquisition unit, an encryption speed setting unit, and an encryption / decryption speed control unit. The level acquisition unit is used to obtain encryption / decryption level information, the encryption speed setting unit is used to set the encryption / decryption calculation speed based on the encryption / decryption level information, and the encryption / decryption speed control unit is used to set the number of calculation clock cycles required to complete a GHASH function multiplication operation, so as to enable the security chip circuit to perform encryption / decryption calculations at the set encryption / decryption calculation speed. By controlling the number of calculation clock cycles required for the GHASH function multiplication operation, the encryption / decryption calculation speed of the security chip circuit is controlled, and thus different encryption / decryption speeds corresponding to different encryption / decryption level information can be achieved, so as to achieve different performance of the security chip circuit according to different user levels.

[0052] The present application also discloses an encryption and decryption speed control method. First, a preset number of computing clock cycles N required to complete a ghash function multiplication operation is obtained. Then, based on the data length L of the multiplier X and the multiplicand Y involved in the ghash function multiplication operation and the number of computing clock cycles N, the number of parallel computing bits M required when performing the ghash function multiplication operation in parallel is obtained, as well as the value P of the number of MUX stages required for the parallel computing bit M. Finally, the MUX with the value P of the stage is set to complete the ghash function multiplication operation of the multiplier X and the multiplicand Y to obtain the product Z. Since the ghash function multiplication operation is performed in parallel, the speed of the ghash function multiplication operation is controllable, thereby achieving controllable encryption and decryption speed.

[0053] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer program. When all or part of the functions in the above embodiments are implemented by computer program, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above functions can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by computer program, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and saved in the memory of the local device by downloading or copying, or the system of the local device is updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be implemented.

[0054] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A method for controlling encryption and decryption speed, characterized in that: The encryption and decryption method is implemented based on ghash function operation, and the encryption and decryption speed control method includes: Get the preset number of computing clock cycles N required to complete a multiplication operation of the ghash function; Obtaining, based on the data length L of the multiplier X and the multiplicand Y involved in the multiplication operation of the ghash function and the number N of calculation clock cycles, a number M of parallel calculation bits required for performing the ghash function multiplication operation in a parallel manner; Obtaining a value P of the number of MUX stages required to complete the ghash function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M; The number of stages of the MUX used for the ghash function multiplication operation is set to a value P, and the ghash function multiplication operation of the multiplier X and the multiplicand Y is performed to obtain a product Z.

2. The encryption and decryption speed control method according to claim 1, characterized in that: The obtaining of the preset number N of computing clock cycles required to complete a multiplication operation of the ghash function includes: The preset number of computing clock cycles N required to complete a multiplication operation of the ghash function is negatively correlated with the encryption and decryption speed.

3. The encryption and decryption speed control method according to claim 1, characterized in that: The method of obtaining, based on the data length L of the multiplier X and the multiplicand Y involved in the multiplication operation of the ghash function and the number N of calculation clock cycles, a number M of parallel calculation bits required for performing the ghash function multiplication operation in a parallel manner includes: The parallel computing bit number M is obtained according to a comparison table between computing clock cycles and parallel required bit numbers; wherein the comparison table between computing clock cycles and parallel required bit numbers is obtained based on a correspondence between the data length L of the multiplier X and the multiplicand Y and the parallel computing bit number M when completing a multiplication operation of the ghash function in a parallel manner within a preset number of computing clock cycles N.

4. The encryption / decryption speed control method according to claim 1, wherein: The step of obtaining a value P of the number of MUX stages for completing the ghash function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M comprises: The value P of the number of MUX levels required to complete the ghash function multiplication operation is obtained according to the comparison table of the number of parallel calculation bits and the number of levels; wherein the comparison table of the number of parallel calculation bits and the number of levels is obtained based on the correspondence between the number of parallel calculation bits M and the number of MUX levels required to complete the ghash function multiplication operation when the ghash function multiplication operation is completed once in parallel within the preset number of calculation clock cycles N.

5. A computer-readable storage medium, characterized in that The medium stores a program, which can be executed by a processor to implement the encryption and decryption speed control method according to any one of claims 1 to 4.

6. An encryption and decryption speed control unit, characterized in that: include: A speed setting module, configured to set the number of computing clock cycles N required to complete a multiplication operation of a ghash function according to a preset encryption and decryption speed; A bit number acquisition module is used to obtain the number of parallel calculation bits M required for performing the ghash function multiplication operation in parallel based on the data length L of the multiplier X and the multiplicand Y participating in the multiplication operation of the ghash function and the number of calculation clock cycles N; A value setting module, configured to obtain a value P of the number of MUX stages required to complete the ghash function multiplication operation based on the data length L of the multiplier X and the multiplicand Y and the number of parallel calculation bits M; The encryption and decryption calculation module is used to select a MUX with a level of value P to complete the multiplication operation of the multiplier X and the multiplicand Y using the ghash function to obtain the product Z.

7. The encryption / decryption speed control unit according to claim 6, characterized in that: The preset number of computing clock cycles N required to complete a multiplication operation of the ghash function is negatively correlated with the encryption and decryption speed.

8. A security chip circuit, characterized in that: The method comprises an encryption / decryption speed control unit according to any one of claims 6 to 7, wherein the encryption / decryption speed control unit is used to control the speed at which the encryption / decryption calculations are performed on the security chip circuit.

9. The security chip circuit according to claim 8, characterized in that: Also includes: The encryption speed setting unit is used to set the encryption and decryption calculation speed according to the preset encryption and decryption level information; wherein different encryption and decryption level information corresponds to different encryption and decryption calculation speeds.

10. The security chip circuit according to claim 9, characterized in that: Also includes: The level query unit is used to obtain the encryption and decryption level information from a preset cloud server.

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