Phase change memory

Abstract

A phase change memory is disclosed. A method for fabricating a phase change memory includes the step of forming an array of phase change memory cells, each cell spaced a same first distance from an adjacent cell in a same row of the array and spaced a same first distance from an adjacent cell in a same column of the array. The method further includes etching one of N memory cells in each row or column, where N is at least equal to two.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and more particularly to phase change memory. BACKGROUND

[0002] A phase change material is a material that can switch between a crystalline phase and an amorphous phase upon heating. As the resistance of the amorphous material is significantly higher than the resistance of the crystalline material, this phenomenon can be used to define two storage states, for example 0 and 1, distinguished by the resistance measured through the phase change material. SUMMARY

[0003] At least one embodiment addresses all or some of the shortcomings of known phase change memory.

[0004] In at least one embodiment, the present disclosure provides a method for manufacturing a phase change memory, comprising: a) a step of forming an array of phase change memory cells, each cell being spaced by a first distance from an adjacent cell in a same row of the array and by the first distance from an adjacent cell in a same column of the array, and b) a step of etching one memory cell out of N memory cells in each row or column, where N is at least 2.

[0005] According to one embodiment, N is equal to 5.

[0006] According to one embodiment, the method comprises, before step a), a step of forming an array of conductive vias, each via being spaced by a second distance from an adjacent via in a same row of the array and by the second distance from an adjacent via in a same column of the array.

[0007] According to one embodiment, step a) comprises forming a stack on the array of vias, the stack comprising a layer of resistive material, a layer of phase change material and a conductive layer.

[0008] In one embodiment, step a) comprises etching the stack so as to delineate cells of the array, each cell comprising a portion of the layer of resistive material, a portion of the layer of phase change material and a portion of the conductive layer.

[0009] According to one embodiment, step b) comprises forming cavities, the cavities exposing the vias on which each etched cell is formed.

[0010] According to one embodiment, step b) comprises etching a row of cells, the etched row being spaced from each other by N-1 rows of unetched cells.

[0011] According to one embodiment, step b) comprises etching one cell out of N cells in each row and column.

[0012] According to one embodiment, the cells formed in step a) are identical.

[0013] Another embodiment provides a phase change memory comprising a plurality of phase change memory cells arranged in rows and columns, wherein each row or each column comprises a group of memory cells, the cells in the same group being spaced apart in pairs by a same first distance, the groups being spaced apart in pairs by a third distance.

[0014] According to one embodiment, the third distance is equal to the sum of twice the first distance and the size of a memory cell in the row or column direction.

[0015] Another embodiment provides a memory as described above, obtained by the method described above. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above features and advantages and other will be described in detail below with respect to specific embodiments given by way of illustration and not limitation, with reference to the following drawings, wherein:

[0017] Figure 1 An apparatus resulting from one step of an embodiment of a method for manufacturing a phase change memory is shown;

[0018] Figure 2 An apparatus resulting from another step of an embodiment of a method for manufacturing a phase change memory is shown;

[0019] Figure 3 An apparatus resulting from another step of an embodiment of a method for manufacturing a phase change memory is shown;

[0020] Figure 4 Several arrangements of cavities of embodiments of Figure 3 are schematically shown;

[0021] Figure 5 An apparatus resulting from another step of an embodiment of a method for manufacturing a phase change memory is shown; and

[0022] Figure 6 An apparatus resulting from an alternative step of a step of Figure 3 is shown. DETAILED DESCRIPTION

[0023] In the different drawings, the same features have been designated by the same reference signs. In particular, structural and / or functional features that are common to the various embodiments can have the same reference signs and can be provided with the same structural, dimensional and material properties.

[0024] For the sake of clarity, only the operations and elements useful for an understanding of the embodiments described herein have been detailed and described.

[0025] Unless otherwise stated, when two elements are referred to as being "connected" together, this means that there is a direct connection between the two elements, without any intermediate elements other than conductors, whereas when two elements are referred to as being "coupled" together, this means that the two elements can be connected, or they can be coupled through one or more other elements.

[0026] In the following disclosure, when referring to absolute position qualifiers, such as the terms "front", "back", "upper", "lower", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper portion", "lower portion", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures, unless otherwise indicated.

[0027] Unless otherwise stated, "about", "approximately", "substantially" and "of the order of" mean within 10%, preferably within 5%.

[0028] Figures 1-5 Steps, preferably successive steps, in one embodiment of a method for manufacturing a phase change memory are shown. The phase change memory comprises a plurality of memory cells, each memory cell being configured to store data, for example binary data. The memory cells are arranged in a cell array, the cell array comprising rows and columns. Figures 1-3 and Figure 5 For example, in the plane of a row of the array.

[0029] Figure 1 An apparatus resulting from the steps in one embodiment of a method for manufacturing a phase change memory is shown.

[0030] In this step, an insulating layer 10 is formed on a substrate 12. The substrate 12 is a semiconductor substrate, for example of silicon, or a semiconductor-on-insulator (SOI) substrate. The insulating layer or dielectric layer 10 is, for example, a single insulating layer, or a stack corresponding to an insulating layer. The insulating layer of the layer 10 is made of one or more dielectric materials, for example silicon oxide or silicon nitride. In the following description, it is for example assumed that the layer 10 comprises a single insulating layer.

[0031] Conductive vias 14 are formed through the layer 10. The vias 14 extend through the layer 10. In other words, the vias 14 extend from an upper side of the layer 10 to a lower side of the layer 10. The lower end of the vias is in contact with the substrate 12, for example. The upper end of the vias is preferably flush with the upper side of the layer 10.

[0032] The vias 14 are regularly, i.e. periodically, located in the layer 10. The vias 14 are located at memory cell locations. The vias 14 thus form an array and form rows and columns. For example, Figure 1 A row of the array is shown. Each via 14 is spaced by the same distance from an adjacent via belonging to the same row or column. Thus, each row or each column of the array comprises pairs of vias 14 spaced by the same distance.

[0033] Between the vias, e.g. selection elements 13 are formed. The selection elements are covered by the insulating layer 17. In the shown example, the selection elements are transistors formed in and on the substrate 12. The transistors are shown by their gates 15. Adjacent transistors in the same row, for example, have a common drain or source region. Thus, the transistors on the same row, for example, are connected in series by their drain and source regions. Figure 1 In the shown example, the selection elements are transistors formed in and on the substrate 12. The transistors are shown by their gates 15. Adjacent transistors in the same row, for example, have a common drain or source region. Thus, the transistors on the same row, for example, are connected in series by their drain and source regions.

[0034] The lower end of each via 14, for example, is in contact with a drain or source region of a transistor 13.

[0035] A layer 16 of resistive material is formed on the layer 10 and on the upper end of the vias 14. The layer 16 is made of, for example, an electrically conductive material, e.g. a metal. The layer 16 is formed on each row of the array, for example. Each layer 16 is preferably separated from the layers 16 on other rows by an insulating material, not shown. The assembly comprising the layers 16 and the insulating material separating them is preferably formed as a flat layer. Each layer 16 is in contact with the upper end of each via of the row. Each layer 16 is, for example, L-shaped in a plane orthogonal to the plane of the array. Figure 1 The layer 16 is, for example, L-shaped in a plane orthogonal to the plane of the array.

[0036] A layer 18 of phase change material is formed on the layer 16, e.g. on the assembly comprising the layers 16 and the insulating material separating them. The layer 18 is made of, for example, an alloy of germanium, antimony and tellurium (GeSbTe or GST). The material of the layer 18 is, for example, doped. In one variant, the material of the layer 18 is undoped. The layer 18 preferably extends over all layers 16. Preferably, the layer 18 extends continuously over the entire array.

[0037] A conductive layer 20 of, for example, a metal is formed on the layer 18. The conductive layer 20 covers the entire layer 18, for example.

[0038] Figure 2 An apparatus resulting from another step of one embodiment of a method for manufacturing a phase change memory is shown.

[0039] Figure 2 The step in the method of Fig. 2 comprises an etching step to delineate the memory cells 22. In this step, cavities 24 are formed through the layers 16, 18 and 20, and, for example, in the layer 10. The cavities 24 are located between the cells 22. The cavities 24 extend, for example, between cells of different rows in the direction of the rows of the array of memory cells, and between cells of different columns in the direction of the columns of the array of memory cells. Thus, the cavities 24 form a grid or grid-like shape. The cavities are located in the opposite portions of the layer 10 not comprising the vias 14, for example.

[0040] Each memory cell defined by the cavity 24 is located opposite the via 14. In other words, the cavity 24 combines portions of the layers 16, 18 and 20. Thus, from the via 14, each memory cell 22 comprises a stack comprising a portion of the layer 16 forming an electrically resistive element, a portion of the layer 18 forming an upper electrode and a portion of the layer 20 forming an upper electrode.

[0041] The array of memory cells 22 is thus formed. In other words, cells are formed arranged in rows and columns. The cells 22 are substantially identical, i.e. the cell size is substantially equal, two by two. More specifically, the memory cells are intended to be identical within the manufacturing dispersion. The cells 22 are regularly, i.e. periodically, located in each row or each column of the array of memory cells. For example, Figure 2 A row of the array is shown. Each cell 22 is spaced the same distance from each adjacent cell in the same row or column. In other words, the distance separating adjacent cells in the same row or column is substantially equal. Thus, each row or each column of the array comprises cells 22 spaced the same distance apart in pairs.

[0042] The structure thus resulting is covered with a protective layer 26 of, for example, insulating material, for example silicon nitride. In particular, the layer 26 covers the walls and the lower part of the cavity 24 and the upper side of the memory cells. In other words, the layer 26 covers the layer 10, the sides of the portions of the layers 16, 18 and 20, and the upper side of the portion of the layer 20.

[0043] The structure is covered with a protective layer 28 of, for example, insulating layer such as silicon oxide.

[0044] Figure 3 An apparatus resulting from another step in one embodiment of a method for manufacturing a phase change memory is shown.

[0045] This step comprises a step of etching certain memory cells. In other words, the vias 14 corresponding to the memory cells etched in this step are not covered by the etching step.

[0046] More specifically, cavities 30 are formed at certain memory cells of the array. Each cavity 30 opens on the upper side of the layer 28 and extends to the via 14. In particular, the portions of the layers 16, 18 and 20 of the cells etched in this step are completely removed. The etching is preferably stopped in the layer 10. Thus, the layer 26 of each cell is spaced from the layers 26 of the other cells by one of the cavities 30.

[0047] For example, the via 14 is not etched. In other words, the cavity exposes the via 14 without etching the via 14. For example, the layer 10 surrounding the via is not etched. For example, the via 14 is still surrounded by a portion of material of the layer 10 after the etching step.

[0048] For example, the cavity 30 does not extend over the whole height of the hole 14. In other words, for example, the cavity 30 extends partially over the height of the layer 10. For example, the selected elements are not etched. The cavity 30 does not reach the substrate 12.

[0049] In Figure 3 the illustrated example, one cell out of N cells is etched. The value N is equal to 5 in the example of Figure 3 . Thus, in the example of Figure 3 , every five memory cells are etched and replaced by a cavity 30. In other words, each row or column preferably comprises a group of N-1 cells, i.e. four cells here. Thus, each row comprises successively N-1 cells, a cavity 30, N-1 cells, a cavity 30, etc.

[0050] The cells of the same group are spaced two by two at the same distance LI. In other words, the distance between two adjacent cells located in the same row or column and in the same group is substantially equal. These groups are spaced from each other by a cavity 30. The size of the cavity 30 is less than the sum of twice the distance between two cells and the size of a cell in the same direction. The two adjacent groups of cells are spaced by the same distance L2. In other words, the cells of the two adjacent groups of cells that are closest to each other are spaced by a distance L2. The distance of the cells of the two adjacent groups of cells that are closest to each other is substantially equal to each other and substantially equal to the value L2. The distance L2 between two cells spaced only by a cavity 30 is equal to the sum of twice the distance between two cells and the size of a cell in the same direction.

[0051] Figure 4 Several example cavity arrangements are schematically illustrated for embodiments of Figure 3 . Figure 4 The views A and B each correspond to a possible arrangement of memory cells 22 and cavities 30.

[0052] Each view A and B schematically illustrates an array of memory cells. In each view A and B, the horizontal rows correspond to memory array rows and the vertical rows correspond to memory array columns. A memory cell is formed at each intersection of a row and a column. In Figure 3 the step of etching of the memory cells, the etched memory cells are illustrated as crosses at the corresponding intersections.

[0053] In the embodiment illustrated in view A, one cell out of N cells is etched in each column. The etched cells are part of the same row. Thus, the row of cells is etched. In other words, the array of cells comprises a row 37 in which all the memory cells are etched in the step of Figure 3 . The row 37 is spaced from N-1 rows in which no cell is etched in the step of Figure 3 .

[0054] The embodiment in view B differs from the embodiment in view A in that the etched unit is not part of the same row. In other words, one of the N units etched in each column is located in a different row than the etched units in at least one of the adjacent columns. For example, the etched unit in each column is offset by one row from the etched units in the adjacent columns, preferably in the same direction.

[0055] According to one embodiment, the memory cell array may include multiple regions, wherein at least some regions have different arrangements.

[0056] Figure 5 An apparatus produced by another step of an embodiment of a method for manufacturing a phase-change memory is shown.

[0057] In this step, cavity 30 is filled with insulating material 40, the material of which is the same as, for example, the material of layer material 28.

[0058] This step also includes forming vias. Vias 42 are formed as a portion of layer 20 reaching each memory cell. In other words, a via is formed relative to each cell. Thus, each cell contacts the via 42 through layer 20. Each via 42 extends from the top of layer 28, passes through layers 28 and 26, and reaches layer 20.

[0059] A via 44 is formed to reach a via 14 opposite to a cavity 30. In other words, a via 44 is formed in each cavity 30. The via 44 reaches and contacts the via 14, which is not covered by the cavity 30. Each via 44 extends from the upper side of the material 40 to the via 14.

[0060] Vias 42 and 44 are made of a conductive material such as copper or tungsten.

[0061] When a memory cell is programmed or read, current is generated between via 14 and via 42 of the cell. For example, current flows through the via 44 closest to the cell and the selection element between the cell and the via 44 to reach via 14.

[0062] Figure 6 It shows the result of Figure 3 A variant of the step that produces the device.

[0063] and Figure 3 The steps are the same as those in the previous step, which includes etching certain memory cells. Figure 6 The steps and Figure 3 The difference is that, for example, the cells are etched in groups of at least two cells (X cells), where X is an integer at least equal to 2. In other words, the memory cells form groups of N× cells, which are separated by cavities 50 created by the etching of the X memory cells.

[0064] The next step (not shown) corresponding to Figure 5 The difference with the next step (not shown) corresponding to

[0065] It is possible to form only the cells that one wishes to keep, and thus to form cavities separating groups of cells during the formation of the memory cells. However, this would lead to size differences between cells in the same group, in particular between cells located at the edge of the group and cells located within the group.

[0066] One advantage of the described embodiments is to reduce variations between different memory cells.

[0067] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these embodiments can be combined, and that other variants will readily occur to the person skilled in the art.

[0068] Finally, actual implementation of the embodiments and variants described herein is within the reach of the person skilled in the art, based on the functional description provided above.

[0069] A method for manufacturing a phase change memory can be summarized as: a) forming an array of phase change memory cells, each cell being spaced apart from an adjacent cell in the same row of the array by a first distance and from an adjacent cell in the same column of the array by a first distance; and b) etching one memory cell out of N memory cells in each row or column, where N is at least 2.

[0070] N is equal to 5.

[0071] A method can be summarized as comprising, before step A), forming an array of conductive vias, each via being spaced apart from an adjacent via in the same row of the array by a second distance and from an adjacent via in the same column by a second distance.

[0072] Step a) can comprise forming a stack on said array of vias, said stack comprising a layer of resistive material, a layer of phase change material and a layer of conductive material.

[0073] Step a) can comprise etching the stack so as to delineate cells of the array, each cell comprising a portion of the layer of resistive material, a portion of the layer of phase change material and a portion of the layer of conductive material.

[0074] Step b) can comprise forming cavities exposing the vias on which each etched cell is formed.

[0075] Step b) can comprise etching rows of cells, the etched rows being spaced apart from each other by N-1 rows of non-etched cells.

[0076] Step b) can comprise etching one cell on N cells in each row and each column.

[0077] The cells formed in step a) can be identical.

[0078] A phase change memory can be summarized as comprising a plurality of phase change memory cells arranged in rows and columns, wherein each row or each column comprises a group of memory cells, the cells in the same group are spaced apart by pairs of a first distance, the group pairs are spaced apart by a third distance.

[0079] The third distance can be equal to the sum of twice the first distance and the size of the memory cell in the row or column direction.

[0080] A memory can be obtained by the method.

[0081] These and other changes can be made to the embodiments in light of the above detailed description. The terms used in the appended claims should not be construed to limit the claims of the application to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments that can come within the scope of the claims, and the equivalents thereof. Accordingly, the claims are not limited to the above disclosed embodiments.

Claims

1. A method for manufacturing a phase change memory, comprising: forming an array of phase change memory cells, each cell being spaced a first distance from an adjacent cell in the same row of the array and from an adjacent cell in the same column of the array; and etching one memory cell out of N memory cells in each row or column, where N is at least 2.

2. The method of claim 1, wherein N is equal to 5.

3. The method of claim 1, comprising: forming an array of conductive vias, each via being spaced a second distance from an adjacent via in the same row of the array and from an adjacent via in the same column of the array.

4. The method of claim 3, wherein forming the array of conductive vias is performed prior to forming the array of phase change memory cells.

5. The method of claim 3, wherein forming the array of phase change memory cells comprises: forming a stack on the array of conductive vias, the stack comprising a layer of resistive material, a layer of phase change material, and a layer of conductive material.

6. The method of claim 5, wherein forming the array of phase change memory cells comprises: depicting cells of an array by etching the stack, each cell comprising a portion of the layer of resistive material, a portion of the layer of phase change material, and a portion of the layer of conductive material.

7. The method of claim 1, wherein etching one memory cell out of the N memory cells comprises forming a cavity, the cavity exposing a via, each etched cell being formed on the via.

8. The method of claim 1, wherein etching one memory cell out of the N memory cells comprises etching a row of cells, the etched row being spaced from N-1 rows of unetched cells to each other.

9. The method of claim 1, wherein etching one of the N memory cells comprises: etching one cell out of N cells in each row and column.

10. The method of claim 1, wherein the cells of the array of phase change memory cells are identical.

11. A phase change memory, comprising: a plurality of phase change memory cells arranged in rows and columns, wherein each row or column comprises a group of memory cells, the cells in the same group of memory cells being spaced pairwise by a same first distance, the groups being spaced pairwise by a second distance; wherein the second distance is equal to a sum of twice the first distance and a size of the memory cells in the row or column direction.

12. A phase change memory, comprising: a plurality of phase change memory cells arranged in rows and columns, wherein each row or column comprises a group of memory cells, the cells in the same group of memory cells being spaced pairwise by a same first distance, the groups being spaced pairwise by a second distance, the phase change memory being obtained by the method of claim 1.

13. The phase change memory of claim 12, wherein N is equal to 5.

14. The phase change memory of claim 12, the phase change memory being further obtained by: forming an array of conductive vias, each via being spaced a third distance from an adjacent via in the same row of the array and from an adjacent via in the same column of the array.

15. The phase change memory of claim 14, wherein forming the array of conductive vias is performed prior to forming the array of phase change memory cells.

16. The phase change memory of claim 14 wherein forming the array of phase change memory cells comprises: forming a stack on the array of conductive vias, the stack including a layer of resistive material, a layer of phase change material, and a layer of conductive material.

17. The phase change memory of claim 16 wherein forming the array of phase change memory cells comprises: defining cells of the array by etching the stack, each cell including a portion of the layer of resistive material, a portion of the layer of phase change material, and a portion of the layer of conductive material.

18. The phase change memory of claim 12, wherein etching one memory cell of N memory cells includes forming a cavity that exposes a via, each etched cell being formed on the via.

19. The phase change memory of claim 12, wherein etching one memory cell of N memory cells includes etching a row of cells, the etched row being spaced from each other by N-1 rows of unetched cells.

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