Phase change memory and method of making the same

Abstract

The embodiments of the present disclosure disclose a phase change memory and a manufacturing method of the phase change memory, the phase change memory comprising: a phase change memory cell; the phase change memory cell comprising at least a phase change memory layer; a thermal insulation structure; the thermal insulation structure at least partially covering a sidewall of the phase change memory layer, and the thermal insulation structure being used for slowing down heat dissipation of the phase change memory layer; a repair layer; the repair layer being located at least between the thermal insulation structure and the phase change memory cell, and the repair layer being used for repairing structural defects between the thermal insulation structure and the phase change memory cell.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a phase-change memory and a method for manufacturing a phase-change memory. Background Technology

[0002] Phase-change memory (PCM), as a new type of non-volatile memory, has significant advantages over flash memory in many aspects, such as read / write speed, read / write cycles, data retention time, cell area, and multi-value implementation.

[0003] However, with the development of phase change memory, there are still many problems in the formation of components in phase change memory cells. Summary of the Invention

[0004] This disclosure provides a phase-change memory and a method for manufacturing a phase-change memory.

[0005] According to a first aspect of the present disclosure, a phase-change memory is provided, comprising:

[0006] Phase-change memory unit; the phase-change memory unit includes at least a phase-change memory layer;

[0007] A thermal insulation structure; the thermal insulation structure at least partially covers the sidewall of the phase change storage layer, and the thermal insulation structure is used to mitigate heat dissipation of the phase change storage layer;

[0008] Repair layer; the repair layer is located at least between the thermal insulation structure and the phase change memory unit, and the repair layer is used to repair structural defects between the thermal insulation structure and the phase change memory unit.

[0009] In the above scheme, the material of the heat insulation structure includes silicon carbide, silicon germanide, silicon selenide, silicon sulfide, silicon telluride, and tin telluride; and / or, the material of the repair layer includes boron nitride.

[0010] In the above scheme, the phase-change memory unit further includes: a gating layer and at least three electrode layers; wherein,

[0011] The gate layer and the at least three electrode layers are stacked along a first direction perpendicular to the substrate. The gate layer is located between the first electrode layer and the second electrode layer among the at least three electrode layers, and the phase change storage layer is located between the second electrode layer and the third electrode layer among the at least three electrode layers.

[0012] In the above scheme, the phase-change memory further includes: an isolation structure;

[0013] The heat insulation structure covers the sidewalls of the three electrode layers, the sidewalls of the phase change storage layer, and the sidewalls of the gate layer, while the isolation structure covers the sidewalls of the heat insulation structure.

[0014] In the above scheme, the phase-change memory further includes: an isolation structure;

[0015] The heat insulation structure covers the sidewalls of the three electrode layers that are parallel to the third direction, the sidewalls of the phase change storage layer that are parallel to the third direction, and the sidewalls of the gate layer that are parallel to the third direction. The isolation structure covers the sidewalls of the heat insulation structure, and the isolation structure covers the sidewalls of the three electrode layers that are parallel to the second direction, the sidewalls of the phase change storage layer that are parallel to the second direction, and the sidewalls of the gate layer that are parallel to the second direction. The second direction and the third direction are both perpendicular to the first direction, and the second direction is perpendicular to the third direction.

[0016] In the above scheme, the heat insulation structure includes a first heat insulation layer and a second heat insulation layer;

[0017] The phase change memory further includes an isolation structure, which includes a first insulating layer and a second insulating layer; wherein the first heat insulation layer covers the sidewall of the phase change memory layer and the sidewall of the third electrode layer, the first insulating layer covers the sidewall of the first heat insulation layer, the second heat insulation layer covers the sidewall of the first insulating layer, the sidewall of the second electrode layer, the sidewall of the gate layer and the sidewall of the first electrode layer, and the second insulating layer covers the sidewall of the second heat insulation layer.

[0018] In the above scheme, the heat insulation structure includes a first heat insulation layer and a second heat insulation layer;

[0019] The phase-change memory further includes an isolation structure, which includes a first insulating layer, a second insulating layer, a first dielectric layer, and a second dielectric layer.

[0020] Wherein, the first heat insulation layer covers the sidewall of the phase change storage layer and the sidewall of the third electrode layer, the first dielectric layer covers the sidewall of the first heat insulation layer, the first insulating layer covers the sidewall of the first dielectric layer, the second heat insulation layer covers the sidewall of the first insulating layer, the sidewall of the second electrode layer, the sidewall of the gate layer and the sidewall of the first electrode layer; the second dielectric layer covers the sidewall of the second heat insulation layer, and the second insulating layer covers the sidewall of the second dielectric layer.

[0021] In the above scheme, the phase change memory further includes: a filling layer;

[0022] The filling layer covers the sidewall of the isolation structure away from the phase change memory cell.

[0023] In the above scheme, the repair layer includes a first sub-repair layer and a second sub-repair layer;

[0024] The first sub-repair layer is located between the thermal insulation structure and the phase change memory unit, and is used to repair structural defects between the thermal insulation structure and the phase change memory unit;

[0025] The second sub-repair layer is located between the filling layer and the isolation structure, and is used to repair structural defects between the filling layer and the isolation structure.

[0026] According to a second aspect of the present disclosure, a method for manufacturing a phase-change memory is provided, comprising:

[0027] A phase change memory cell is formed, wherein the phase change memory cell includes at least a phase change memory layer;

[0028] A heat insulation structure is formed; the heat insulation structure at least partially covers the sidewall of the phase change storage layer, and the heat insulation structure is used to reduce the heat dissipation of the phase change storage layer;

[0029] A repair layer is formed; the repair layer is located at least between the thermal insulation structure and the phase change memory unit, and the repair layer is used to repair structural defects between the thermal insulation structure and the phase change memory unit.

[0030] This disclosure provides a phase-change memory (PCM) and a method for manufacturing a PCM. The PCM includes: a PCM cell; the PCM cell includes at least a PCM layer; a thermal insulation structure; the thermal insulation structure at least partially covers the sidewall of the PCM layer and is used to mitigate heat dissipation of the PCM layer; and a repair layer; the repair layer is located at least between the thermal insulation structure and the PCM cell and is used to repair structural defects between the thermal insulation structure and the PCM cell. In this disclosure, by providing a thermal insulation structure at least on a portion of the sidewall of the PCM layer to mitigate heat dissipation, and by providing a repair layer between the PCM cell and the thermal insulation structure to repair structural defects, the PCM cell and the thermal insulation structure are more tightly integrated, further mitigating heat dissipation of the PCM layer. This improves the problem of low thermal efficiency of the PCM cell due to significant heat loss from the PCM layer, and the low performance of the PCM caused by thermal interference to adjacent unselected PCM cells due to heat loss. Attached Figure Description

[0031] Figure 1a This is a partial cross-sectional schematic diagram of a phase-change memory according to an embodiment of the present disclosure in the xoz axis plane;

[0032] Figure 1b This is a partial equivalent circuit diagram of a phase-change memory according to an embodiment of the present disclosure;

[0033] Figure 2a This is a schematic diagram of the heat distribution along the z-axis of a phase change memory according to an embodiment of the present disclosure;

[0034] Figure 2b This is a schematic diagram of the heat distribution along the x-axis of a phase change memory according to an embodiment of the present disclosure;

[0035] Figure 3a This is a partial cross-sectional schematic diagram of a phase change memory according to an embodiment of the present disclosure;

[0036] Figure 3b This is a partial cross-sectional schematic diagram of another phase change memory according to an embodiment of the present disclosure;

[0037] Figure 3c This is a partial cross-sectional schematic diagram of another phase change memory according to an embodiment of the present disclosure;

[0038] Figure 3d This is a partial cross-sectional schematic diagram of another phase change memory according to an embodiment of the present disclosure;

[0039] Figure 3e This is a partial cross-sectional schematic diagram of another phase change storage according to an embodiment of the present disclosure;

[0040] Figure 4 This is a schematic diagram illustrating the implementation flow of a phase-change memory fabrication method according to an embodiment of the present disclosure;

[0041] Figures 5a-5k This is a cross-sectional schematic diagram illustrating the implementation process of a phase-change memory fabrication method according to an embodiment of the present disclosure. Detailed Implementation

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0044] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Figure 1a This is a partial cross-sectional schematic diagram of a phase-change memory according to an embodiment of this disclosure in the xoz-axis plane. (Refer to...) Figure 1a As shown, the phase-change memory (PCM) includes a first address line 1010, a phase-change memory cell 1100, and a second address line 1050 stacked sequentially from bottom to top. The phase-change memory cell 1100 includes a first electrode layer 1020a, a gate layer 1030, a second electrode layer 1020b, a phase-change memory layer 1040, and a third electrode layer 1020c stacked sequentially from bottom to top. The PCM can utilize the heating and quenching of the phase-change memory layer 1040 to switch between an amorphous phase and a crystalline phase, thereby storing data based on the difference in resistivity between the amorphous phase and the crystalline phase.

[0049] from Figure 1a As can be seen, the phase-change memory further includes an isolation structure, which comprises a first insulating layer 1063, a second insulating layer 1065, a first dielectric layer 1062, and a second dielectric layer 1064. The first dielectric layer 1062 covers the sidewalls of the phase-change memory layer 1040 and the third electrode layer 1020c. The first insulating layer 1063 covers the sidewalls of the first dielectric layer 1062. The second dielectric layer 1064 covers the sidewalls of the first insulating layer 1063, the second electrode layer 1020b, the gate layer 1030, and the first electrode layer 1020a. The second insulating layer 1065 covers the sidewall of the second dielectric layer 1064. The phase-change memory further includes a fill layer 1067, which covers the sidewall of the isolation structure away from the phase-change memory cell 1100. In practical applications, the materials of the first dielectric layer 1062 and the second dielectric layer 1064 include silicon nitride, and the materials of the first insulating layer 1063 and the second insulating layer 1065 include silicon oxide. The phase-change memory provided in the above embodiments can encapsulate the phase-change memory cell 1100 using silicon nitride and silicon oxide, thereby protecting the phase-change memory cell 1100 and isolating adjacent phase-change memory cells 1100; while the filling layer 1067 can be used to alleviate thermal interference problems between adjacent phase-change memory cells 1100.

[0050] Figure 1b A partial equivalent circuit diagram of a phase-change memory is shown. (Refer to...) Figure 1b As shown, the phase-change memory includes a phase-change memory array composed of nine phase-change memory cells 1100, and three first address lines 1010 extending parallel to the y-direction. u1 1010 s and 1010 u2 And three second address lines 1050 extending parallel to the x-direction. u1 1050 s and 1050 u2In each phase-change memory cell 1100, the gating layer 1030 can be equivalent to a gating element, and the phase-change memory layer 1040 can be equivalent to a variable resistor. That is, each phase-change memory cell 1100 can be equivalent to a variable resistor and a gating element connected in series. The phase-change memory cell 1100 is electrically connected to a first address line 1010 through one end of the gating element and to a second address line 1050 through one end of the variable resistor.

[0051] When programming operation is required for phase-change memory cell S, but not for phase-change memory cells a, b, and c, phase-change memory cell S is the selected phase-change memory cell, and phase-change memory cells a, b, and c are the unselected phase-change memory cells. In this case, the first address line 1010 can be used... s Apply the first line voltage (V) to the phase change memory cell S ll ), and via the second address line 1050 s Apply the first word line voltage (V) to the phase change memory cell S hh This causes the voltage (V) applied to the phase-change memory cell S to... hh -V ll It is large enough to program the phase-change memory cell S.

[0052] At the same time, through the first address line 1010 u1 Or 1010 u2 A second bit line voltage (V) is applied to phase change memory cell a and phase change memory cell c. ub ), via the second address line 1050 u1 Or 1050 u2 A second word line voltage (V) is applied to phase change memory cell b and phase change memory cell c. uw The absolute value of the second bit line voltage is less than the absolute value of the first bit line voltage, and the absolute value of the second word line voltage is less than the absolute value of the first word line voltage.

[0053] It should be noted that, via the first address line 1010 s Apply the first line voltage (V) to the selected phase-change memory cell S ll At the same time, it will also send a signal to the first address line 1010. s The first line voltage (V) is applied to the series-connected phase change memory cell b. ll Similarly, via the second address line 1050 s Apply the first word line voltage (V) to the selected phase-change memory cell S hh At the same time, it will also send a signal to the second address line 1010. s The first word line voltage (V) is applied to the cascaded phase-change memory cell a. hh ).

[0054] Therefore, for Figure 1b The storage array corresponding to the partial equivalent circuit of the phase-change memory shown has the following voltages for phase-change memory cells S, a, b, and c, respectively:

[0055] V S =V hh -V ll (1)

[0056] V a =V hh -V ub (2)

[0057] V b =V uw -V ll (3)

[0058] V c =V uw -V ub (4)

[0059] Among them, V S V is the voltage of the phase-change memory cell S. a V is the voltage of phase change memory cell a. b V is the voltage of phase change memory cell b. c denoted as voltage of phase-change memory cell c.

[0060] It should be noted that in the xoz-axis plane and yoz-axis plane involved in the accompanying drawings of this disclosure, the x-axis and y-axis are parallel to the substrate, the z-axis is perpendicular to the substrate, and the x-axis, y-axis and z-axis are perpendicular to each other.

[0061] Figure 2a A schematic diagram of the heat distribution along the z-axis of a phase change memory according to an embodiment of the present disclosure is shown; Figure 2b A schematic diagram of the heat distribution along the x-axis of a phase-change memory according to an embodiment of this disclosure is shown. From Figure 2a As can be seen, the phase change storage layer in the phase change memory has the highest heat output; from Figure 2b As can be seen, the heat from the phase change storage layer dissipates to the filling layers on both sides and to the unselected phase change storage cells. For example... Figure 2bAs shown in the above embodiments of this disclosure, the phase-change memory cells of the phase-change memory have a serious problem of heat loss, and there is thermal crosstalk between adjacent phase-change memory cells. Research has found that the main reason for the aforementioned thermal crosstalk and serious heat loss is the relatively high thermal conductivity of silicon nitride. This leads to high heat dissipation in the memory cell layer. Due to the low thermal efficiency, the selected phase-change memory cells cannot be fully reset, resulting in a large distribution of reset resistance. Furthermore, the dissipated heat is conducted through the fill layer to adjacent unselected memory cells, causing these unselected phase-change memory cells to be interfered with by a high-temperature field.

[0062] To address the aforementioned problems, one embodiment of this disclosure provides a phase-change memory, such as... Figure 3a As shown, the phase-change memory includes:

[0063] Phase-change memory unit 1100; the phase-change memory unit 1100 includes at least a phase-change memory layer 1040;

[0064] Thermal insulation structure 1200; the thermal insulation structure 1200 at least partially covers the sidewall of the phase change storage layer 1040, and the thermal insulation structure 1200 is used to reduce the heat dissipation of the phase change storage layer 1040.

[0065] Repair layer 1068; the repair layer 1068 is located at least between the thermal insulation structure and the phase change memory unit, and the repair layer 1068 is used to repair structural defects between the thermal insulation structure and the phase change memory unit.

[0066] Here, the statement that the heat insulation structure 1200 at least partially covers the phase change storage layer 1040 can be understood as follows: the heat insulation structure 1200 may only cover the sidewall of the phase change storage layer 1040 that is parallel to the second direction, or it may only cover the sidewall of the phase change storage layer 1040 that is parallel to the third direction, or it may simultaneously cover the sidewall of the phase change storage layer 1040 that is parallel to both the second and third directions.

[0067] The term "coverage" here can be understood as coverage when viewed from the projection direction, while the thermal insulation structure 1200 and the phase change storage unit 1100 may not be in physical contact. Similarly, the term "coverage" in the following text is not limited to physical contact; it can also be understood as coverage when viewed from the projection direction.

[0068] Here, the constituent materials of the phase change memory layer 1040 may include, but are not limited to, chalcogenide-based alloys, such as GST (Ge-Sb-Te) alloys. The constituent materials of the phase change memory layer 1040 may also include any other suitable phase change materials. It should be noted that when a phase change occurs in the phase change memory layer 1040, the resistance of the phase change memory layer 1040 changes. The phase change memory can store data based on the change in resistance state of the phase change memory layer 1040.

[0069] Here, the heat insulation structure 1200 is used to reduce the heat dissipation of the phase change storage layer 1040, and the material of the heat insulation structure 1200 can be a material with a thermal conductivity less than a preset value.

[0070] It is understandable that the lower the thermal conductivity of the insulation structure 1200, the better the insulation effect of the insulation structure 1200 on the phase change storage layer 1040 of the phase change storage unit 1100. For example, the preset value here can be 0.8 W / mk, but the preset value is not limited to this. In practical applications, it can be set according to specific process requirements, as long as the material of the insulation structure 1200 can achieve the required insulation effect on the phase change storage unit 1100.

[0071] In some embodiments, the materials of the thermal insulation structure 1200 include, but are not limited to, silicon carbide, silicon germanide, silicon selenide, silicon sulfide, silicon telluride, and tin telluride.

[0072] Studies have found that silicon carbide has a density of 1.6 g / cm³. 3 At that time, the thermal conductivity was approximately 0.41 W / mK. When silicon carbide was used as a heat insulation material on the sidewall of the phase change storage layer 1040 of the phase change memory, it could effectively slow down heat loss in the phase change storage layer. Compared with some embodiments of this disclosure that use silicon nitride and silicon oxide as insulation structures to simultaneously provide heat insulation, silicon nitride, with a density of 2.38 g / cm³, has a better thermal conductivity. 3 The thermal conductivity of silicon carbide is approximately 1.0 W / mK. Since the thermal conductivity of silicon carbide is significantly lower than that of silicon nitride, using silicon carbide as a thermal insulation structure 1200 to insulate the phase change memory can effectively reduce heat loss in the phase change memory unit 1100 and also mitigate thermal interference to adjacent phase change memories caused by heat loss.

[0073] The materials of the thermal insulation structure 1200 mentioned in the above embodiments are merely illustrative examples. In practical applications, the materials of the thermal insulation structure 1200 are not limited to silicon carbide. The materials of the thermal insulation structure 1200 can also be other materials with characteristics such as structural stability, low thermal conductivity (i.e., thermal conductivity less than the aforementioned preset value), and high temperature resistance (at least able to withstand the temperatures of the phase change storage layer in both amorphous and crystalline states).

[0074] In some embodiments, the material of the repair layer 1068 includes boron nitride.

[0075] It is understood that boron nitride material has a planar two-dimensional structure with flat surface atoms and no dangling bonds or trapped charges, which can repair the defects between the phase change memory cell 1100 and the heat insulation structure 1200. In this embodiment of the present disclosure, by providing a repair layer 1068 between the memory cell 1100 and the heat insulation structure 1200, the gap between the memory cell 1100 and the heat insulation structure 1200 can be filled, making the memory cell layer 1100 and the heat insulation structure 1200 more tightly bonded, thereby further slowing down the heat loss in the memory cell layer.

[0076] In some embodiments, the phase-change memory unit 1100 further includes: a gate layer 1030 and at least three electrode layers; wherein,

[0077] The gate layer 1030 and the at least three electrode layers are stacked along a first direction perpendicular to the substrate 1001. The gate layer 1030 is located between the first electrode layer 1020a and the second electrode layer 1020b among the at least three electrode layers. The phase change storage layer 1040 is located between the second electrode layer 1020b and the third electrode layer 1020c among the at least three electrode layers.

[0078] Here, the first direction is perpendicular to the surface of the substrate 1001. In practical applications, the first direction can be understood as the z-axis direction shown in the accompanying drawings of this disclosure, but it is understood that the first direction is not limited to the z-axis direction. The second direction and the third direction described below are both parallel to the substrate. In practical applications, the second direction can be understood as the y-axis direction shown in the accompanying drawings of this disclosure, and the third direction can be understood as the x-axis direction shown in the accompanying drawings of this disclosure, but it is understood that the second direction is not limited to the y-axis direction, and the third direction is not limited to the x-axis direction.

[0079] Here, the constituent materials of the gate layer 1030 may include: an omonic threshold switching (OTS) material, such as zinc telluride (Zn). a Te b Germanium telluride (Ge) a Te b ), niobium oxide (Nb) a O b ) or silicon arsenide telluride (Si a As b Te c )wait.

[0080] Here, the constituent materials of the first electrode layer 1020a, the second electrode layer 1020b, and the third electrode layer 1020c include, but are not limited to, amorphous carbon, such as α-phase carbon.

[0081] Here, the location of the heat insulation structure 1200 can be configured in various ways. The heat insulation structure 1200 may include one or more layers, that is, the heat insulation structure 1200 may include at least one of a first heat insulation layer 1061 and a second heat insulation layer 1062; the heat insulation structure 1200 may fully cover the sidewalls of the phase change storage layer 1040 in the second direction and the third direction, or it may partially cover the sidewalls of the phase change storage layer 1040 only in the second direction or only in the third direction, that is, the heat insulation structure 1200 may include at least one of a first portion extending in the second direction and a second portion extending in the third direction; the heat insulation structure 1200 may be located between the phase change storage layer 1040 and the isolation structure, or between the isolation structure and the filling layer 1067, or even within the isolation structure; the heat insulation structure 1200 may even replace the material in the isolation structure, so that the heat insulation structure 1200 serves both a heat insulation function and an isolation and encapsulation function. The following are some specific examples. It should be noted that the following examples are not intended to limit the position of the thermal insulation structure 1200. The structures in the several embodiments provided in this disclosure can be arbitrarily combined to obtain new embodiments without conflict.

[0082] like Figure 3a As shown, in some embodiments, the phase-change memory further includes an isolation structure;

[0083] The heat insulation structure 1200 covers the sidewalls of the first electrode layer 1020a, the second electrode layer 1020b, the third electrode layer 1020c, the phase change storage layer 1040, and the gate layer 1030, and the isolation structure covers the sidewalls of the heat insulation structure 1200.

[0084] In some embodiments, the isolation structure includes a first insulating layer 1063 that covers the sidewall of the thermal insulation structure 1200, and the material of the first insulating layer 1063 includes, but is not limited to, silicon oxide.

[0085] refer to Figure 3b In some embodiments, the thermal insulation structure 1200 includes a first thermal insulation layer 1061 and a second thermal insulation layer 1066;

[0086] The phase change memory further includes an isolation structure, which includes a first insulating layer 1063 and a second insulating layer 1065; wherein the first heat insulation layer 1061 covers the sidewall of the phase change memory layer 1040 and the sidewall of the third electrode layer 1020c, the first insulating layer 1063 covers the sidewall of the first heat insulation layer 1061, the second heat insulation layer 1066 covers the sidewall of the first insulating layer 1063, the sidewall of the second electrode layer 1020b, the sidewall of the gate layer 1030 and the sidewall of the first electrode layer 1020a, and the second insulating layer 1065 covers the sidewall of the second heat insulation layer 1066.

[0087] Here, the constituent materials of the first insulating layer 1063 and the second insulating layer 1065 may include oxides, such as silicon oxide, but are not limited thereto. The materials of the first insulating layer 1063 and the second insulating layer 1065 may be the same or different.

[0088] In some embodiments, reference Figure 3c The heat insulation structure includes a first heat insulation layer 1061 and a second heat insulation layer 1066;

[0089] The phase-change memory further includes an isolation structure, which includes a first insulating layer 1063, a second insulating layer 1065, a first dielectric layer 1062, and a second dielectric layer 1064.

[0090] Wherein, the first heat insulation layer 1061 covers the sidewall of the phase change storage layer 1040 and the sidewall of the third electrode layer 1020c; the first dielectric layer 1062 covers the sidewall of the first heat insulation layer 1061; the first insulating layer 1063 covers the sidewall of the first dielectric layer 1062; the second heat insulation layer 1066 covers the sidewall of the first insulating layer 1063, the sidewall of the second electrode layer 1020b, the sidewall of the gate layer 1030, and the sidewall of the first electrode layer 1020a; the second dielectric layer 1064 covers the sidewall of the second heat insulation layer 1066; and the second insulating layer 1065 covers the sidewall of the second dielectric layer 1064.

[0091] In some embodiments, such as Figure 3b As shown, the phase change memory further includes a filling layer 1067;

[0092] The filling layer 1067 covers the sidewall of the isolation structure away from the phase change memory cell 1100.

[0093] In some embodiments, such as Figure 3b As shown, the repair layer 1068 includes a first sub-repair layer 1068-1 and a second sub-repair layer 1068-2;

[0094] The first sub-repair layer 1068-1 is located between the heat insulation structure 1200 and the phase change memory unit 1100, and is used to repair the structural defects between the heat insulation structure 1200 and the phase change memory unit 1100;

[0095] The second sub-repair layer 1068-2 is located between the filling layer 1067 and the isolation structure, and is used to repair structural defects between the filling layer 1067 and the isolation structure.

[0096] It should be noted that only Figure 3a as well as Figure 3b The image shows repair layer 1068. In practical applications, repair layer 1068 can also be set as... Figures 3a-3d At the corresponding position.

[0097] Understandably, boron nitride materials can form heterojunctions, which can enhance the bond energy between the 1067 filler layer and the isolation structure, thus avoiding voids in the 1067 filler layer and forming a better interface. In addition, boron nitride itself is relatively dense.

[0098] In this embodiment of the present disclosure, by providing a repair layer between the filling layer 1067 and the isolation structure, the filling layer 1067 and the isolation structure are more tightly bonded, thereby further mitigating the heat loss in the storage cell layer.

[0099] In some embodiments, reference Figure 3d as well as Figure 3e The phase-change memory further includes: an isolation structure;

[0100] The heat insulation structure covers the sidewalls of the three electrode layers that are parallel to the third direction, the sidewalls of the phase change storage layer 1040 that are parallel to the third direction, and the sidewalls of the gate layer 1030 that are parallel to the third direction. The isolation structure covers the sidewalls of the heat insulation structure, and the isolation structure covers the sidewalls of the three electrode layers that are parallel to the second direction, the sidewalls of the phase change storage layer 1040 that are parallel to the second direction, and the sidewalls of the gate layer 1030 that are parallel to the second direction. The second direction and the third direction are both perpendicular to the first direction, and the second direction is perpendicular to the third direction.

[0101] The thermal insulation structure here includes, for example Figure 3e The first insulation layer 1061 in the middle, the isolation structure includes as follows Figure 3d as well as Figure 3e The first dielectric layer 1062 and the first insulating layer 1063 are in the middle.

[0102] In this embodiment of the disclosure, firstly, silicon carbide has a density of 1.6 g / cm³. 3At that time, the thermal conductivity was approximately 0.41 W / mK, and silicon nitride had a density of 2.38 g / cm³. 3 The thermal conductivity of silicon carbide is approximately 1.0 W / mK. In some embodiments of this disclosure, replacing silicon nitride with silicon carbide can effectively mitigate heat loss in the phase-change memory cell. Secondly, the low-conductivity silicon carbide-based encapsulation structure provides enhanced thermal confinement, thereby achieving a more uniform amorphous structure in the phase-change memory cell, resulting in better thermal efficiency and less write interference during reset operations. Thirdly, silicon carbide has high structural strength, which is beneficial to structural stability during the fabrication process. Fourthly, silicon carbide has a stable structure, and particles are not easily diffused. During operation, particles in silicon carbide are less likely to diffuse into the phase-change memory cell, thus improving the reliability of the phase-change memory.

[0103] In this embodiment, thermal crosstalk sensitivity is an important parameter in phase change memory (PCH) cells. A process optimization path is provided through interface thermal resistance engineering between the PCH layer and the fill layer, and lateral thermal interface engineering between adjacent PCH cells, aiming to suppress thermal crosstalk. In PCH cells with added thermal insulation structures, the temperature distribution is more uniform, thereby achieving better programming efficiency, thermal crosstalk suppression, and an expanded read window budget.

[0104] This disclosure provides a phase-change memory (PCM) comprising: a PCM cell; the PCM cell including at least a PCM layer; a thermal insulation structure; the thermal insulation structure at least partially covering the sidewalls of the PCM layer, and the thermal insulation structure being used to mitigate heat dissipation of the PCM layer; and a repair layer; the repair layer being located at least between the thermal insulation structure and the PCM cell, and the repair layer being used to repair structural defects between the thermal insulation structure and the PCM cell. In this disclosure, by providing a thermal insulation structure at least on a portion of the sidewalls of the PCM layer, the thermal insulation structure mitigates heat dissipation of the PCM layer. Furthermore, by providing a repair layer between the PCM cell and the thermal insulation structure, structural defects between the PCM cell and the thermal insulation structure are repaired, resulting in a tighter bond between the PCM cell and the thermal insulation structure. This further mitigates heat dissipation of the PCM layer, thereby improving the problem of low thermal efficiency of the PCM cell due to significant heat loss from the PCM layer, and the low performance of the PCM caused by thermal interference to adjacent unselected PCM cells due to the lost heat.

[0105] Based on the above-described phase-change memory, this disclosure also provides a method for manufacturing a phase-change memory, such as... Figure 4 The implementation flow of the phase-change memory fabrication method shown includes:

[0106] Step 4001: Form a phase change memory cell 1100, wherein the phase change memory cell 1100 includes at least a phase change memory layer 1040;

[0107] Step 4002: Form a thermal insulation structure 1200; the thermal insulation structure 1200 at least partially covers the sidewall of the phase change storage layer 1040, and the thermal insulation structure 1200 is used to reduce the heat dissipation of the phase change storage layer 1040.

[0108] Step 4003: Form a repair layer; the repair layer is located at least between the thermal insulation structure and the phase change memory unit, and the repair layer is used to repair structural defects between the thermal insulation structure and the phase change memory unit.

[0109] In step 4001, a phase change memory cell 1100 can be formed on the substrate 1001 by thin film deposition and etching processes.

[0110] In step 4002, a thermal insulation structure 1200 can be formed on the sidewall of the phase change storage layer 1040 by processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0111] In step 4003, the repair layer 1068 can be formed by atomic layer deposition or molecular beam epitaxy (MBE). However, the method for forming the repair layer is not limited to these methods.

[0112] In some embodiments, the material of the thermal insulation structure 1200 includes silicon carbide.

[0113] In some embodiments, the phase-change memory cell 1100 further includes: a gate layer 1030 and at least three electrode layers; the method further includes:

[0114] Along a first direction perpendicular to the plane of the substrate 1001, a first electrode layer 1020a, a gate layer 1030, a second electrode layer 1020b, a phase change storage layer 1040, and a third electrode layer 1020c are formed in a stacked manner.

[0115] Here, a first electrode layer 1020a, a gate layer 1030, a second electrode layer 1020b, a phase change storage layer 1040, and a third electrode layer 1020c can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition (ALD).

[0116] In some embodiments, the method further includes: forming an isolation structure;

[0117] The heat insulation structure 1200 covers the sidewalls of the first electrode layer 1020a, the second electrode layer 1020b, the third electrode layer 1020c, the phase change storage layer 1040, and the gate layer 1030, and the isolation structure covers the sidewalls of the heat insulation structure 1200.

[0118] Here, methods for forming isolation structures include, but are not limited to, deposition processes.

[0119] In some embodiments, forming the thermal insulation structure 1200 includes forming a first thermal insulation layer 1061 and a second thermal insulation layer 1066;

[0120] The method further includes: forming an isolation structure, the isolation structure including: a first insulating layer 1063 and a second insulating layer 1065; wherein, the first heat insulation layer 1061 covers the sidewall of the phase change storage layer 1040 and the sidewall of the third electrode layer 1020c, the first insulating layer 1063 covers the sidewall of the first heat insulation layer 1061, the second heat insulation layer 1066 covers the sidewall of the first insulating layer 1063, the sidewall of the second electrode layer 1020b, the sidewall of the gate layer 1030 and the sidewall of the first electrode layer 1020a, and the second insulating layer 1065 covers the sidewall of the second heat insulation layer 1066.

[0121] In some embodiments, forming the thermal insulation structure 1200 includes forming a first thermal insulation layer 1061 and a second thermal insulation layer 1066;

[0122] The method further includes: forming an isolation structure, the isolation structure including: a first insulating layer 1063, a second insulating layer 1065, a first dielectric layer 1062 and a second dielectric layer 1064;

[0123] Wherein, the first heat insulation layer 1061 covers the sidewall of the phase change storage layer 1040 and the sidewall of the third electrode layer, the first dielectric layer 1062 covers the sidewall of the first heat insulation layer 1061, the first insulating layer 1063 covers the sidewall of the first dielectric layer 1062, the second dielectric layer 1064 covers the sidewall of the first insulating layer 1063, the sidewall of the second electrode layer 1020b, the sidewall of the gate layer 1030, and the sidewall of the first electrode layer 1020a; and the second insulating layer 1065 covers the sidewall of the second dielectric layer 1064.

[0124] In some embodiments, the method further includes: forming a fill layer 1067; wherein,

[0125] The filling layer 1067 covers the sidewall of the isolation structure away from the phase change memory cell 1100.

[0126] In some embodiments, forming the repair layer 1068 includes: forming a first sub-repair layer 1068-1 and a second sub-repair layer 1068-2;

[0127] The first sub-repair layer 1068-1 is located between the heat insulation structure 1200 and the phase change memory unit 1100, and is used to repair the structural defects between the heat insulation structure 1200 and the phase change memory unit 1100;

[0128] The second sub-repair layer 1068-2 is located between the filling layer 1067 and the isolation structure, and is used to repair structural defects between the filling layer 1067 and the isolation structure.

[0129] In some embodiments, the material of the repair layer 1068 includes boron nitride.

[0130] In some embodiments, the method further includes forming an isolation structure;

[0131] The heat insulation structure covers the sidewalls of the three electrode layers that are parallel to the third direction, the sidewalls of the phase change storage layer 1040 that are parallel to the third direction, and the sidewalls of the gate layer 1030 that are parallel to the third direction. The isolation structure covers the sidewalls of the heat insulation structure, and the isolation structure covers the sidewalls of the three electrode layers that are parallel to the second direction, the sidewalls of the phase change storage layer 1040 that are parallel to the second direction, and the sidewalls of the gate layer 1030 that are parallel to the second direction. The second direction and the third direction are both perpendicular to the first direction, and the second direction is perpendicular to the third direction.

[0132] The following provides specific examples in conjunction with any of the above embodiments:

[0133] Figures 5a to 5k This is a schematic diagram illustrating a method for manufacturing a phase-change memory according to an exemplary embodiment.

[0134] Reference Figures 5a to 5k The method may specifically include the following steps:

[0135] refer to Figure 5a A first conductive material layer 1010-1, a first electrode material layer 1020a-1, a gate material layer 1030-1, a second electrode material layer 1020b-1, and a first sacrificial layer 1070 are formed sequentially from bottom to top on the surface of the substrate 1001.

[0136] Here, the constituent materials of the substrate 1001 may include semiconductor materials, such as silicon, germanium, or gallium arsenide.

[0137] It should be noted that, in the embodiments of this disclosure, "from bottom to top" means from the direction close to the surface of the substrate 1001 to the direction away from the surface of the substrate 1001.

[0138] Here, the first conductive material layer 1010-1 is composed of conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polycrystalline silicon.

[0139] Here, the constituent materials of the first electrode material layer 1020a-1 and the second electrode material layer 1020b-1 include amorphous carbon, such as α-phase carbon.

[0140] Here, the first sacrificial layer 1070 may include a photoresist mask or a hard mask patterned based on a photolithography mask. For example, silicon nitride.

[0141] Here, a first conductive material layer 1010-1, a first electrode material layer 1020a-1, a gate material layer 1030-1, a second electrode material layer 1020b-1, and a first sacrificial layer 1070 can be sequentially formed on the surface of the substrate 1001 by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof.

[0142] like Figure 5b As shown, etching is first performed along a direction parallel to the z-axis to form a first trench 1081 penetrating the first conductive material layer 1010-1, the first electrode material layer 1020a-1, the gate material layer 1030-1, the second electrode material layer 1020b-1, and the first sacrificial layer 1070, wherein the bottom of the first trench 1081 exposes the substrate 1001. The first trench 1081 divides the first conductive material layer 1010-1, the first electrode material layer 1020a-1, the gate material layer 1030-1, the second electrode material layer 1020b-1, and the first sacrificial layer 1070 into a first address line 1010, a first electrode material strip 1020a-2, a gate material strip 1030-2, a second electrode material strip 1020b-2, and a first sacrificial strip 1070-1, respectively.

[0143] Here, the method for forming the first trench 1081 may include, but is not limited to, dry plasma etching.

[0144] In practical applications, the first trench 1081 may include one or more. The following explanation uses multiple trenches as an example. Figure 5b As shown, multiple first grooves 1081 are arranged side by side along a direction parallel to the x-axis.

[0145] After forming the first trench 1081, refer to Figure 5cAs shown, a repair layer 1068 is formed covering the sidewall of the first trench 1081, a first heat insulation layer 1061 is formed covering the repair layer 1068, a first dielectric layer 1062 is formed covering the first heat insulation layer 1061, a first insulating layer 1063 is formed covering the first dielectric layer 1062, and a filler layer 1067 is formed covering the first insulating layer 1063. The first insulating layer 1063 and the first dielectric layer 1062 together constitute an isolation structure; the first heat insulation layer 1061 constitutes a heat insulation structure.

[0146] In practical applications, the first thermal insulation layer 1061, the first dielectric layer 1062, the first insulating layer 1063, and the filler layer 1067 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof. The constituent material of the first thermal insulation layer 1061 may include carbides, such as silicon carbide, but is not limited thereto. The constituent material of the first dielectric layer 1062 may include nitrides, such as silicon nitride, but is not limited thereto. The constituent material of the first insulating layer 1063 may include oxides, such as silicon oxide, but is not limited thereto. The isolation structure can be used to encapsulate the covered first address line 1010, the first electrode material strip 1020a-2, the gate material strip 1030-2, and the second electrode material strip 1020b-2.

[0147] In practical applications, after forming the heat insulation structure, the isolation structure, and the filling layer 1067, the method further includes: removing the first heat insulation layer 1061, the first dielectric layer 1062, the first insulating layer 1063, and the filling layer 1067 covering the surface of the first sacrificial strip 1070-1, and exposing the first sacrificial strip 1070-1 (e.g., Figure 5c (As shown).

[0148] In practical applications, the first heat insulation layer 1061, the first dielectric layer 1062, the first insulating layer 1063, and the filler layer 1067 covering the surface of the first sacrificial strip 1070-1 can be removed by chemical mechanical polishing (CMP).

[0149] refer to Figure 5d Remove the first sacrificial strip 1070-1 to form the second groove 1082.

[0150] Here, the methods for removing the first sacrificial strip 1070-1 include, but are not limited to, wet etching and dry etching.

[0151] refer to Figure 5e A phase change storage material layer 1040-1 is formed in the second trench 1082.

[0152] In practical applications, the method for forming the phase change storage material layer 1040-1 is a deposition process, including but not limited to chemical vapor deposition and atomic layer deposition. Among them, chemical vapor deposition includes metal-organic chemical vapor deposition (MOCVD) and plasma-enhanced chemical vapor deposition (PECVD).

[0153] In practical applications, when depositing the phase change storage material layer 1040-1 into the second trench 1082, a portion of the material used to form the phase change storage material layer 1040-1 will also be formed on the second trench 1082, the isolation structure, the heat insulation structure, and the upper part of the filling layer 1067.

[0154] In practical applications, it is necessary to remove the material on top of the second trench 1082, the isolation structure, the thermal insulation structure, and the filling layer 1067 used to form the phase change storage material layer 1040-1, exposing the isolation structure, the thermal insulation structure, and the filling layer 1067. Methods for removing the material on top of the second trench 1082, the isolation structure, the thermal insulation structure, and the filling layer 1067 used to form the phase change storage material layer 1040-1 include, but are not limited to, CMP.

[0155] refer to Figure 5f A third electrode material layer 1020c-1, a second conductive material layer 1050-1, and a first mask layer 1090 are sequentially formed on the phase change storage material layer 1040-1.

[0156] In practical applications, the first mask layer 1090 may include a photoresist mask or a hard mask patterned based on a photolithography mask, such as silicon nitride. The material composition of the first mask layer 1090 and the first sacrificial layer 1070 may be the same or different.

[0157] Figure 5g It shows in Figure 5f The cross-sectional view of the AA' position in the zoy plane.

[0158] The following combination Figures 5h-5k The method for forming an isolation structure and a heat insulation structure that extends along the x-axis is explained.

[0159] like Figure 5hAs shown, a plurality of third trenches 1083 are formed along a direction parallel to the z-axis, penetrating the first mask layer 1090, the second conductive material layer 1050-1, the third electrode material layer 1020c-1, and the phase change storage material layer 1040-1; wherein the bottom of the third trenches 1083 exposes the second electrode material strips 1020b-2. The plurality of third trenches 1083 are arranged side by side along a direction parallel to the y-axis, and each third trench 1083 extends along a direction parallel to the x-axis. The third trenches 1083 divide the first mask layer 1090, the second conductive material layer 1050-1, the third electrode material layer 1020c-1, and the phase change storage material layer 1040-1 into the first mask strips 1090-1, the second address lines 1050, the third electrode layer 1020c, and the phase change storage layer 1040, wherein the plurality of second address lines 1050 are parallel to each other and extend along the x-axis.

[0160] like Figure 5i As shown, a first heat insulation layer 1061 is formed covering the sidewall of the third trench 1083, a first dielectric layer 1062 is formed covering the first heat insulation layer 1061, and a first insulating layer 1063 is formed covering the first dielectric layer 1062.

[0161] like Figure 5j Along a direction parallel to the z-axis, a fourth trench 1084 is formed by etching the second electrode material strip 1020b-2, the gate material strip 1030-2, and the first electrode material strip 1020a-2 from the bottom of the third trench 1083. The fourth trench 1084 penetrates the first mask layer 1090, the second conductive material layer 1050-1, the third electrode material layer 1020c-1, the phase change storage material layer 1040-1, the second electrode material strip 1020b-2, the gate material strip 1030-2, and the first electrode material strip 1020a-2. The bottom of the fourth trench 1084 exposes the first address line 1010. Multiple fourth trenches 1084 are arranged side-by-side along a direction parallel to the y-axis, and each fourth trench 1084 extends along a direction parallel to the x-axis. The fourth trench 1084 divides the second electrode material strip 1020b-2, the gate material strip 1030-2, and the first electrode material strip 1020a-2 into a second electrode layer 1020b, a gate layer 1030, and a first electrode layer 1020a.

[0162] like Figure 5k As shown, a second heat insulation layer 1066 is formed covering the sidewalls of the first insulating layer 1063, the sidewalls of the second electrode layer 1020b, the sidewalls of the gate layer 1030, and the sidewalls of the first electrode layer 1020a; a second dielectric layer 1064 is formed covering the second heat insulation layer 1066; a second insulating layer 1065 is formed covering the sidewalls of the second dielectric layer 1064; and a repair layer 1068 is formed covering the sidewalls of the second insulating layer 1065. Figure 5k(Not shown in the image), forming a filling layer 1067 covering the sidewalls of the repair layer 1068. The thermal insulation structure here is composed of a first thermal insulation layer 1061 and a second thermal insulation layer 1066. The isolation structure is composed of a first dielectric layer 1062, a first insulating layer 1063, a second dielectric layer 1064, and a second insulating layer 1065.

[0163] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0164] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A phase change memory, characterized by, The phase change memory comprises: a phase change memory cell; the phase change memory cell comprises at least a phase change memory layer; a thermal insulation structure; the thermal insulation structure at least partially covers the sidewall of the phase change memory layer, and the thermal insulation structure is used to slow down the heat dissipation of the phase change memory layer; the material of the thermal insulation structure comprises silicon carbide, silicon germanium, silicon selenide, silicon sulfide, silicon telluride and tin telluride; an isolation structure; the isolation structure covers the sidewall of the thermal insulation structure; a filling layer; the filling layer covers the sidewall of the isolation structure away from the phase change memory cell; a repair layer; the material of the repair layer comprises boron nitride; the repair layer comprises a first sub-repair layer and a second sub-repair layer; the first sub-repair layer is located between the thermal insulation structure and the phase change memory cell, and is used to repair the structural defects between the thermal insulation structure and the phase change memory cell; the first sub-repair layer makes the phase change memory cell and the thermal insulation structure more closely combined; the second sub-repair layer is located between the filling layer and the isolation structure, and is used to repair the structural defects between the filling layer and the isolation structure; the second sub-repair layer makes the filling layer and the isolation structure more closely combined.

2. The phase change memory of claim 1, wherein, The phase change memory cell further comprises a gating layer and at least three electrode layers; wherein, the gating layer and the at least three electrode layers are stacked along a first direction perpendicular to the substrate, the gating layer is located between a first electrode layer and a second electrode layer in the at least three electrode layers, and the phase change memory layer is located between the second electrode layer and a third electrode layer in the at least three electrode layers.

3. The phase change memory of claim 2, wherein, The phase change memory further comprises an isolation structure; wherein, the thermal insulation structure covers the sidewall of the three electrode layers parallel to the third direction, the sidewall of the phase change memory layer parallel to the third direction and the sidewall of the gating layer parallel to the third direction; the isolation structure covers the sidewall of the thermal insulation structure, and the isolation structure covers the sidewall of the three electrode layers parallel to the second direction, the sidewall of the phase change memory layer parallel to the second direction and the sidewall of the gating layer parallel to the second direction, the second direction and the third direction are both perpendicular to the first direction, and the second direction is perpendicular to the third direction.

4. The phase change memory of claim 2, wherein, The thermal insulation structure comprises a first thermal insulation layer and a second thermal insulation layer; The phase change memory further comprises an isolation structure, and the isolation structure comprises a first insulating layer and a second insulating layer; wherein, the first thermal insulation layer covers the sidewall of the phase change memory layer and the sidewall of the third electrode layer, the first insulating layer covers the sidewall of the first thermal insulation layer, the second thermal insulation layer covers the sidewall of the first insulating layer, the sidewall of the second electrode layer, the sidewall of the gating layer and the sidewall of the first electrode layer, and the second insulating layer covers the sidewall of the second thermal insulation layer.

5. The phase change memory of claim 2, wherein, The thermal insulation structure comprises a first thermal insulation layer and a second thermal insulation layer; The phase change memory further comprises an isolation structure, and the isolation structure comprises a first insulating layer, a second insulating layer, a first dielectric layer and a second dielectric layer; The first thermal insulation layer covers the sidewall of the phase change storage layer and the sidewall of the third electrode layer, the first dielectric layer covers the sidewall of the first thermal insulation layer, the first insulation layer covers the sidewall of the first dielectric layer, and the second thermal insulation layer covers the sidewall of the first insulation layer, the sidewall of the second electrode layer, the sidewall of the gating layer and the sidewall of the first electrode layer; the second dielectric layer covers the sidewall of the second thermal insulation layer, and the second insulation layer covers the sidewall of the second dielectric layer.

6. A method of manufacturing a phase change memory, characterized by: Comprise: forming a phase change storage unit, the phase change storage unit at least comprising a phase change storage layer; forming a thermal insulation structure; the thermal insulation structure at least partially covers the sidewall of the phase change storage layer, and the thermal insulation structure is used to slow down the heat dissipation of the phase change storage layer; the material of the thermal insulation structure comprises silicon carbide, germanium silicon, selenium silicon, sulfur silicon, silicon telluride and tin telluride; forming an isolation structure; the isolation structure covers the sidewall of the thermal insulation structure; forming a filling layer; the filling layer covers the sidewall of the isolation structure away from the phase change storage unit side; forming a repair layer; the material of the repair layer comprises boron nitride; the repair layer comprises a first sub-repair layer and a second sub-repair layer; the first sub-repair layer is located between the thermal insulation structure and the phase change storage unit, used to repair the structural defects between the thermal insulation structure and the phase change storage unit, and the first sub-repair layer makes the phase change storage unit and the thermal insulation structure more closely combined; the second sub-repair layer is located between the filling layer and the isolation structure, used to repair the structural defects between the filling layer and the isolation structure, and the second sub-repair layer makes the filling layer and the isolation structure more closely combined.

Images