Cell Current Test Circuit and Its Test Method

Abstract

The present invention provides a cell current test circuit and a test method thereof. The circuit includes: a cell unit module for selecting a cell unit; a test switch transistor connected between the output end of the cell unit module and an IO port and controlled by a first control signal, for conducting in a current test mode; a sense amplifier connected to the output end of the cell unit module, for making the current input to the sense amplifier be 0 in the current test mode. Through the cell current test circuit and the test method thereof provided by the present invention, the problem that the existing technology cannot accurately measure the cell current is solved.

Description

Technical Field

[0001] The present invention belongs to the field of memories, and particularly relates to a cell current test circuit and a test method thereof. Background Art

[0002] Memories are important components in digital integrated circuits, and are an indispensable part for constructing application systems based on microprocessors. In recent years, various memories have been embedded inside processors to improve the integration and working efficiency of processors.

[0003] The multi-time programmable (MTP) memory, compared with the one-time programmable (OTP) memory, has the advantages of being able to perform operations such as data storage, reading, and erasing multiple times, and the stored data will not disappear after power-off. It has gradually become a memory device widely used in fields such as personal computers, electronic devices, and mobile storage.

[0004] The MTP memory must have high reliability. The cell current of the MTP memory (cell can refer to bit-cell, that is, the storage unit) is the starting point of its design. Only by fully understanding the characteristics of the cell current can a highly reliable MTP memory be designed. Therefore, the test of the cell current plays a crucial role in the R & D stage of the MTP memory. How to accurately measure the cell current is a very important issue. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a cell current test circuit and a test method thereof, which are used to solve the problem that the cell current cannot be accurately measured in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a cell current test circuit, and the circuit includes:

[0007] A cell unit module, which is used to select a cell unit;

[0008] A test switch transistor, which is connected between the output end of the cell unit module and the IO port and is controlled by a first control signal, and is used to conduct in the current test mode;

[0009] A sense amplifier, which is connected to the output end of the cell unit module, and is used to make the current input to the sense amplifier be 0 in the current test mode.

[0010] Optionally, the cell current test is realized by testing the current flowing through the IO port.

[0011] Optionally, the sense amplifier includes an internal MOS transistor, with its gate connected to the second control signal, its drain connected to the output terminal of the cell unit module, and its source grounded; in the current test mode, the current input to the sense amplifier is made 0 by disconnecting the path to ground of the internal MOS transistor.

[0012] Optionally, the sense amplifier further includes a switch connected between the gate of the internal MOS transistor and ground. By controlling the switch to close, the gate potential of the internal MOS transistor is pulled low, disconnecting the path to ground of the internal MOS transistor.

[0013] Optionally, the sense amplifier further includes a switch connected between the drain of the internal MOS transistor and the output terminal of the cell unit module. By controlling the switch to open, the connection between the drain of the internal MOS transistor and the output terminal of the cell unit module is cut off, disconnecting the path to ground of the internal MOS transistor.

[0014] Optionally, the sense amplifier further includes a switch connected between the source of the internal MOS transistor and ground. By controlling the switch to open, the connection between the source of the internal MOS transistor and ground is cut off, disconnecting the path to ground of the internal MOS transistor.

[0015] Optionally, the sense amplifier further includes at least two switches connected to at least two of the following locations: between the gate of the internal MOS transistor and ground, between the drain of the internal MOS transistor and the output terminal of the cell unit module, and between the source of the internal MOS transistor and ground.

[0016] Optionally, the switch includes a MOS switch transistor or a CMOS switch transistor, where the MOS switch transistor includes an NMOS switch transistor or a PMOS switch transistor.

[0017] Optionally, the test switch transistor is an NMOS transistor, with its gate connected to the first control signal, its drain connected to the output terminal of the cell unit module, and its source connected to the IO port.

[0018] Optionally, the cell unit module includes a cell unit array, a row selection unit, and a column selection unit. The row selection unit is used to select the word lines of the cell unit array, and the column selection unit is used to select the bit lines of the cell unit array.

[0019] The present invention also provides a method for testing the cell current. The method includes: when entering the current test mode, making the current input to the sense amplifier 0. At this time, the cell current test is achieved by testing the current flowing through the IO port.

[0020] As described above, a cell current test circuit and a test method thereof according to the present invention set a test switch transistor between the cell unit module and the sense amplifier, and add at least one switch in the sense amplifier, so that the current input to the sense amplifier is 0, thereby realizing accurate testing of the cell current without affecting the normal operation of the circuit in other modes; moreover, the circuit is simple, small in area and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It shows a circuit schematic diagram of the cell current test circuit.

[0022] Figure 2 It shows a circuit schematic diagram of a cell current test circuit according to the present invention.

[0023] Figure 3 It shows a circuit schematic diagram of another cell current test circuit according to the present invention.

[0024] Figure 4 It shows a circuit schematic diagram of still another cell current test circuit according to the present invention.

[0025] DESCRIPTION OF REFERENCE NUMERALS

[0026] 100 cell unit module

[0027] 101 cell unit array

[0028] 102 row selection unit

[0029] 103 column selection unit

[0030] 200 sense amplifier DETAILED DESCRIPTION OF THE INVENTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0033] For Figure 1As for the cell current test circuit shown, when performing the cell current test, its working principle is: the IO port is grounded, and the gate of the test switch tube M0 is connected to a high level (that is, the first control signal MICELL is a high level). At this time, the test switch tube M0 is turned on, and the current of the selected cell unit will flow into the ground terminal through the IO port. The current of the selected cell unit can be measured by testing the current flowing through the IO port.

[0034] But adopt Figure 1 The cell current measured by the circuit shown is always smaller than the theoretical value. The problem is that after the cell current flows into the node NetA, it will flow out from two branches. In the normal working mode (i.e., the reading mode), the first control signal MICELL is at a low level, and the second control signal SREF is at a higher level determined by the internal circuit of the sense amplifier itself. At this time, the test switch tube M0 is turned off, the internal MOS tube M1 is turned on, and the cell current will flow into the sense amplifier 200. In the current test mode, most of the circuits in the sense amplifier 200 are working normally. At this time, the first control signal MICELL is at a high level, and the second control signal SREF is at a higher level determined by the internal circuit of the sense amplifier itself. The test switch tube M0 and the internal MOS tube M1 are both turned on. Although the potential at the NetA point is very low at this time, only a dozen millivolts, some cell current will still flow into the sense amplifier 200.

[0035] According to Kirchhoff's current law: the sum of the currents flowing into a node is equal to the sum of the currents flowing out of the node, we can get Icell=Isa+Iio, where Icell represents the current of the selected cell unit, Isa represents the current flowing into the sense amplifier, and Iio represents the current flowing into the IO port.

[0036] When testing the cell current, the first control signal MICELL is at a high level, the test switch tube M0 works in the deep linear region, and the on-resistance is relatively small, generally around a few hundred ohms, so the node voltage of NetA is usually in the order of tens of millivolts; Figure 1 In the circuit shown, Isa is mistakenly considered to be close to 0, based on the assumption that Icell≈Iio; but in fact, Isa is not equal to 0, so Iio <Icell;而把Iio作为cell电流,这会导致测得的cell电流偏小。

[0037] To solve Figure 1 To solve the problem that the cell current measured by the circuit shown is too small, this embodiment will provide a new circuit that can be used for cell current testing.

[0038] like Figures 2 - 4As shown, this embodiment provides a cell current test circuit, which includes:

[0039] A cell unit module 100 for selecting a cell unit;

[0040] A test switch transistor M0 connected between the output terminal of the cell unit module 100 and the IO port and controlled by a first control signal MICELL, for conducting in the current test mode;

[0041] A sense amplifier 200 connected to the output terminal of the cell unit module 100, for making the current input to the sense amplifier 200 be 0 in the current test mode.

[0042] For the cell current test circuit of this embodiment, in the current test mode, the IO port is grounded; at this time, the cell current can be tested by measuring the current flowing through the IO port.

[0043] Specifically, the cell unit module 100 includes: a cell unit array 101, a row selection unit 102, and a column selection unit 103. The row selection unit 102 is used to select the word line of the cell unit array 101, and the column selection unit 103 is used to select the bit line of the cell unit array 101, so as to select a cell unit based on the word line and the bit line (as Figures 2 - 4 shown).

[0044] Specifically, the test switch transistor M0 is an NMOS transistor, the gate is connected to the first control signal MICELL, the drain is connected to the output terminal of the cell unit module 100, and the source is connected to the IO port (as Figures 2 - 4 shown). The test switch transistor M0 is turned off in the normal operating mode and turned on in the current test mode under the control of the first control signal MICELL.

[0045] Specifically, the sense amplifier includes an internal MOS transistor M1, the gate is connected to a second control signal SREF, the drain is connected to the output terminal of the cell unit module 100, and the source is grounded; in the current test mode, the current input to the sense amplifier 200 is made 0 by disconnecting the ground path of the internal MOS transistor M1 (as Figures 2 - 4 shown).

[0046] In the first example, the sense amplifier 200 further includes a switch S1 connected between the gate of the internal MOS transistor M1 and the ground. By controlling the switch S1 to close, the gate potential of the internal MOS transistor M1 is pulled low, thereby disconnecting the ground path of the internal MOS transistor M1 (as Figure 2As shown). It should be noted that the switch S1 is only closed in the current test mode, and in other modes, in order not to affect the normal operation of the circuit, the switch S1 is open.

[0047] In the second example, the sense amplifier 200 further includes a switch S1 connected between the drain of the internal MOS transistor M1 and the output terminal of the cell unit module 100. By controlling the opening of the switch S1, the connection between the drain of the internal MOS transistor M1 and the output terminal of the cell unit module 100 is cut off, thereby disconnecting the ground path of the internal MOS transistor M1 (as Figure 3 shown). It should be noted that the switch S1 is only open in the current test mode, and in other modes, in order not to affect the normal operation of the circuit, the switch S1 is closed.

[0048] In the third example, the sense amplifier 200 further includes a switch S1 connected between the source of the internal MOS transistor M1 and the ground. By controlling the opening of the switch S1, the connection between the source of the internal MOS transistor M1 and the ground is cut off, thereby disconnecting the ground path of the internal MOS transistor M1 (as Figure 4 shown). It should be noted that the switch S1 is only open in the current test mode, and in other modes, in order not to affect the normal operation of the circuit, the switch S1 is closed.

[0049] In the fourth example, the sense amplifier 200 further includes at least two switches connected to at least two of the gate of the internal MOS transistor M1 and the ground, the drain of the internal MOS transistor M1 and the output terminal of the cell unit module 100, and the source of the internal MOS transistor M1 and the ground, so as to make the current input to the sense amplifier 200 zero by controlling the closing and / or opening of the switches (the control of the corresponding switches can be seen in detail in the first three examples). In practical applications, however, in order to reduce the area, usually one switch is used to achieve this, as in the first three examples. Optionally, the switch S1 can be implemented by a MOS switch transistor or a CMOS switch transistor; when implemented by a MOS switch transistor, the MOS switch transistor can be an NMOS switch transistor or a PMOS switch transistor.

[0050] Correspondingly, this embodiment further provides a cell current test method, which includes: when entering the current test mode, making the current input to the sense amplifier zero, and at this time, the cell current test is realized by testing the current flowing through the IO port.

[0051] Next, please combine Figures 2 - 4 to describe the cell current test method of this embodiment in detail.

[0052] ForFigure 2 For the cell current test circuit shown, in the current test mode, the control switch S1 is closed to pull down the gate potential of the internal MOS transistor M1, thereby turning off the internal MOS transistor M1 and disconnecting the grounding path of the internal MOS transistor M1 to the ground. At this time, the current flowing into the sense amplifier is 0, that is, Isa = 0, so that Icell = Iio.

[0053] For Figure 3 For the cell current test circuit shown, in the current test mode, the control switch S1 is opened to cut off the connection between the drain of the internal MOS transistor M1 and the output terminal of the cell unit module 100, thereby disconnecting the grounding path of the internal MOS transistor M1 to the ground. At this time, the current flowing into the sense amplifier is 0, that is, Isa = 0, so that Icell = Iio.

[0054] For Figure 4 For the cell current test circuit shown, in the current test mode, the control switch S1 is opened to cut off the connection between the source of the internal MOS transistor M1 and the ground, thereby disconnecting the grounding path of the MOS transistor M1 to the ground. At this time, the current flowing into the sense amplifier is 0, that is, Isa = 0, so that Icell = Iio.

[0055] In summary, a cell current test circuit and a test method thereof according to the present invention set a test switch transistor between the cell unit module and the sense amplifier, and add at least one switch in the sense amplifier to make the current input to the sense amplifier 0, so as to accurately test the cell current without affecting the normal operation of the circuit in other modes; moreover, the circuit is simple, small in area and low in cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0056] The above embodiments are only used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A cell current test circuit, characterized in that, The circuit includes: A cell unit module for selecting a cell unit; A test switch transistor connected between the output terminal of the cell unit module and the IO port and controlled by a first control signal, for conducting in the current test mode; A sense amplifier connected to the output terminal of the cell unit module, for making the current input to the sense amplifier be 0 in the current test mode; The circuit realizes cell current testing by testing the current flowing through the IO port; Wherein, the sense amplifier includes an internal MOS transistor, the gate is connected to a second control signal, the drain is connected to the output terminal of the cell unit module, and the source is grounded; in the current test mode, the input current to the sense amplifier is made 0 by disconnecting the ground path of the internal MOS transistor.

2. The cell current test circuit according to claim 1, wherein The sense amplifier further includes a switch connected between the gate of the internal MOS transistor and the ground, and the gate potential of the internal MOS transistor is pulled low by controlling the switch to close, disconnecting the ground path of the internal MOS transistor.

3. The cell current test circuit according to claim 1, characterized in that, The sense amplifier further includes a switch connected between the drain of the internal MOS transistor and the output terminal of the cell unit module, and the connection between the drain of the internal MOS transistor and the output terminal of the cell unit module is cut off by controlling the switch to open, disconnecting the ground path of the internal MOS transistor.

4. The cell current test circuit according to claim 1, wherein The sense amplifier further includes a switch connected between the source of the internal MOS transistor and the ground, and the connection between the source of the internal MOS transistor and the ground is cut off by controlling the switch to open, disconnecting the ground path of the internal MOS transistor.

5. The cell current test circuit according to claim 1, wherein The sense amplifier further includes at least two switches connected to at least two of the following: between the gate of the internal MOS transistor and the ground, between the drain of the internal MOS transistor and the output terminal of the cell unit module, and between the source of the internal MOS transistor and the ground.

6. The cell current test circuit according to any one of claims 2-5, characterized in that, The switch includes a MOS switch transistor or a CMOS switch transistor, wherein, the MOS switch transistor includes an NMOS switch transistor or a PMOS switch transistor.

7. The cell current test circuit according to claim 1, wherein The test switch transistor is an NMOS transistor, the gate is connected to the first control signal, the drain is connected to the output terminal of the cell unit module, and the source is connected to the IO port.

8. The cell current test circuit according to claim 1, characterized in that, The cell unit module includes: a cell unit array, a row selection unit and a column selection unit, the row selection unit is used to select the word line of the cell unit array, and the column selection unit is used to select the bit line of the cell unit array.

9. A cell current testing method implemented based on the cell current testing circuit according to any one of claims 1-8, characterized in that The method includes: when entering the current test mode, making the current input to the sense amplifier be 0, and at this time, realizing cell current testing by testing the current flowing through the IO port.

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