Memory device for data search and data search method

Abstract

This disclosure provides a memory device and a data searching method for data searching. The data searching method includes the following steps: receiving a search word and dividing it into multiple segments; encoding these segments into multiple encoded segments to correspond to multiple memory blocks of a memory array; guiding these encoded segments to these memory blocks for data comparison to obtain a data comparison result; and then obtaining the address of the bit line matching the search word based on the data comparison result of each memory block.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of operating the same, and more particularly to a memory device and a method for data searching. Background Technology

[0002] With the rapid development of semiconductor technology, various forms and architectures of memory are now widely used in electronic devices. Memory typically takes the form of an array to efficiently address each memory cell, enabling fast access to the large amounts of data stored in the memory array.

[0003] However, as the capacity of memory arrays increases significantly, the time required to search for data in the memory array also increases significantly; in particular, when the length of the target search word is long, it will consume more data search time.

[0004] Furthermore, for large memory arrays, performing complex data searches requires a large number of peripheral components, such as numerous word line drivers, search line encoders, and bit line induction amplifiers, which significantly increases the chip area of ​​the overall memory device and raises the chip manufacturing cost.

[0005] The above describes the technical problems faced by existing large-scale memory arrays in terms of operation and manufacturing.

[0006] Public content

[0007] In order to overcome the aforementioned technical problems of existing large memory arrays, this disclosure proposes a technical solution that sets up input and output circuits to be used in conjunction with large memory arrays, thereby performing data search and comparison within the memory array to improve data search efficiency.

[0008] The present disclosure provides a memory device for data searching, including a memory array, an input circuit, and an output circuit. The memory array has multiple memory blocks for storing data and multiple bit lines. The input circuit includes a segmentation circuit, an encoding circuit, and a multiplexing circuit. The segmentation circuit receives a search word and segments it into multiple segments. The encoding circuit encodes these segments into multiple encoded segments, each corresponding to one of the memory blocks. The multiplexing circuit directs these encoded segments to the memory blocks, and each encoded segment is compared with each memory block in the memory array to obtain a comparison result. Furthermore, the output circuit obtains the addresses of the bit lines matching the search word based on the comparison results of each memory block.

[0009] The present disclosure also provides another memory device for data searching, including a memory array, an input circuit, and an output circuit. The memory array has multiple memory blocks for storing data and multiple bit lines. The input circuit receives and processes a search word, directing the processed search word to the memory blocks. The processed search word is compared with the memory blocks in the memory array to obtain multiple data comparison results. Furthermore, the output circuit includes multiple processing circuits and a selection circuit. These processing circuits are respectively mapped to the bit lines and process the data comparison results corresponding to the memory blocks of each bit line. The selection circuit collects and processes the data comparison results of each bit line and obtains the addresses of the bit lines that match the search word based on the data comparison results of each bit line.

[0010] The present disclosure provides a data search method for a memory device, comprising the following steps: receiving a search word and dividing the search word into multiple segments; encoding these segments into multiple coded segments, each coded segment corresponding to a multiple memory block of a memory array, wherein the memory array has multiple bit lines; directing these coded segments to these memory blocks; comparing each coded segment with each memory block within the memory array to obtain a data comparison result; and obtaining the addresses of the bit lines matching the search word based on the data comparison results of each memory block.

[0011] The technical solution disclosed herein also provides another data search method for a memory device, comprising the following steps: receiving and processing a search word; directing the processed search word to multiple memory blocks of a memory array, wherein the memory array has multiple bit lines; performing data comparisons between the processed search word and each memory block corresponding to each bit line to obtain multiple data comparison results; collecting and processing each data comparison result of each bit line; and obtaining the addresses of the bit lines that match the search word based on the data comparison results of each bit line.

[0012] By employing the technical solutions described above, the input circuit performs diverse processing on the target search word, and the output circuit collects and integrates the data comparison results of each memory block in the memory array, thereby effectively improving data search efficiency.

[0013] Other aspects and advantages of this disclosure will become apparent from the following figures, detailed description, and claims. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall architecture of the memory device 10 for performing data search according to the present disclosure.

[0015] Figure 2 This is a schematic diagram of the architecture of the input circuit 20A according to the first embodiment of the present disclosure.

[0016] Figure 3A , 3B This is a schematic diagram illustrating the operation of the input circuit 20A according to the first embodiment of this disclosure.

[0017] Figure 4A This is a schematic diagram of the architecture of the input circuit 20B according to the second embodiment of the present disclosure.

[0018] Figure 4B This is a schematic diagram illustrating the operation of the input circuit 20B according to a second embodiment of the present disclosure.

[0019] Figure 5A This is a schematic diagram of the architecture of the output circuit 30A according to the first embodiment of the present disclosure.

[0020] Figure 5B This is a schematic diagram illustrating the operation of the output circuit 30A according to the first embodiment of the present disclosure.

[0021] Figure 5C This is a schematic diagram of the architecture of the output circuit 30B according to the second embodiment of the present disclosure.

[0022] Figure 5D This is a schematic diagram of the architecture of the output circuit 30C according to the third embodiment of the present disclosure.

[0023] Figure 6A This is a flowchart of a data search method for a memory device according to the present disclosure.

[0024] Figure 6B for Figure 6A A flowchart detailing a first embodiment of step S16 in the figure is provided.

[0025] Figure 6C for Figure 6A A flowchart detailing a second embodiment of step S16 in the figure is provided.

[0026] Explanation of reference numerals in the attached figures

[0027] 10: Memory devices

[0028] 11: Memory Array

[0029] 12: Memory unit

[0030] 13A~13C: Memory subarray

[0031] 20, 20A, 20B: Input circuit

[0032] 21: Bit resolution circuit

[0033] 22: Segmentation Circuit

[0034] 23: Encoding Circuit

[0035] 24, 24-1, 24-2: Multiplexing Circuits

[0036] 30, 30A, 30B, 30C: Output circuits

[0037] 31A, 31B, 31C: Processing circuits

[0038] 32: and the door

[0039] 32a: First input terminal

[0040] 32b: Second input terminal

[0041] 32c: Output terminal

[0042] 33: Temporary Register

[0043] 34: Matching Address Encoder

[0044] 35: Counter

[0045] 36: Comparator

[0046] bi: bit

[0047] b1~b m :Bit

[0048] S: Search term

[0049] Si: Section

[0050] S1~S k Section

[0051] eS i : Encoding segment

[0052] eS1~eS k : Encoding segment

[0053] WL, WL i : Word line

[0054] WL1~WL m : Word line

[0055] WL' i WL” i Entity signal

[0056] BL j Bit line

[0057] BL1~BLp Bit line

[0058] M i : Memory block

[0059] M1~M k : Memory block

[0060] SA i Induction amplifier

[0061] SA1~SA p Induction amplifier

[0062] SeL(i), SeL(i)': Search row signals

[0063] S11~S16: Steps

[0064] S21~S26: Steps

[0065] S31~S33: Steps Detailed Implementation

[0066] Detailed descriptions of the embodiments of this disclosure are given in Figures 1 through 6C.

[0067] Figure 1 This is a schematic diagram of the overall architecture of the memory device 10 for performing data searching according to this disclosure. See also... Figure 1 The memory device 10 includes a memory array 11, an input circuit 20, and an output circuit 30.

[0068] The memory array 11 includes multiple memory cells 12, which can be accessed via p bit lines (BL) BL1, BL2, ..., BL3. p And m word lines (WL) WL1, WL2, ..., WL m Addressing is performed on each memory cell 12. Each word line WL i It can be composed of two physical signals {WL' i WL i The search line (SeL) signal transmitted by the input circuit 20 is also composed of two physical signals {SeL(i)}, which correspond to {WL'} respectively. i WL i The memory array 11 can be divided into multiple memory blocks. For example, the memory array 11 can be divided into k memory blocks M1, M2, ..., M according to the second direction (vertical direction). k .

[0069] The memory array 11 is electrically connected to the input circuit 20 and the output circuit 30. The input circuit 20 is connected via word lines WL. i Electrically connected to memory array 11; input circuit 20 and via word line WL i The search row signals {SeL(i) , SeL(i)'} are transmitted to the memory array 11. The output circuit 30 transmits the signals via bit line BL. j Electrically connected to memory array 11; bit lines BL j via the corresponding sense amplifier (SA) i The data comparison result is transmitted to the output circuit 30. The data comparison result is the sum of the values ​​of each bit line BL. j The comparison result between the data stored in each corresponding memory block M1 and a search word S.

[0070] Furthermore, the input circuit 20 can receive the search word S = {b1, b2, ..., b}. m The input circuit 20 performs one or more input functions to convert the search word S into search row signals {SeL(i), SeL(i)'}. Each search row signal {SeL(i), SeL(i)'} is then transmitted to k memory blocks M1, M2, ..., Mk. k And with each memory block M i The stored data is compared to obtain the memory address that matches the search word S, thus achieving the purpose of data search. Therefore, the input circuit 20 can also be called a search word encoder.

[0071] The main feature of the technical solution disclosed herein is that the search word S is divided into multiple shorter segments S. i Each segment S after division i Only with one memory block M i Data comparisons are performed to improve the overall search efficiency of memory array 11. Each segment S i With the corresponding memory block M i After completing the data comparison, use a single line BL. j Based on this, for each line of BL j The data comparison results are transmitted to the output circuit 30 respectively.

[0072] The output circuit 30 performs one or more output functions to integrate the data comparison results of each bit line BLj and select the bit line BLj that matches the search word S. jThe output circuit 30 is used to preferentially select the bit line BL that yields the best data comparison result (perfectly matches the search word S or is closest to the search word S). j The address is used, so the output circuit 30 can also be called a priority encoder.

[0073] Figure 2 This is a schematic diagram of the architecture of the input circuit 20A according to the first embodiment of the present disclosure. Figure 3A , 3B This is a schematic diagram illustrating the operation of the input circuit 20A according to the first embodiment of this disclosure. See also... Figure 2 and Figure 3A , 3B The input circuit 20A includes a one-bit parsing circuit 21, a segmentation circuit 22, an encoding circuit 23, and a multiplexing circuit 24.

[0074] Bit parsing circuit 21 receives and temporarily stores the search word S = {b1, b2, ..., b}. m} and perform bit parsing processing on each bit b1, including: masking, rotation or shifting.

[0075] In the masking process, the search term S = {b1, b2, ..., b} is... m} Specific positions (e.g., positions n to (n+2)) are masked with wildcard bits "x" to become the search word S = {b1, b2, ..., b} n-1 ,x,x,x,b n+3 , ..., b m When performing data comparison on the search word S in the memory array 11, the nth to (n+2th)th bits of the search word S can be ignored and not compared.

[0076] In rotation processing, the bits bi of the search word S can be rotated clockwise (towards the higher-order bits) or counterclockwise (towards the lower-order bits). For example: the search word S = {b1, b2, ..., b} m Rotate two positions clockwise to obtain the search term S = {b} m-1 b m b1, b2, ..., b m-2}, or rotate two positions counterclockwise to become the search word S = {b3, b4, ..., b} m ,b1,b2}.

[0077] In the translation process, the bits bi of the search word S are shifted either towards the higher or lower bits. For example, shifting the search word S = {b1, b2, ..., bm} two bits towards the higher bits results in the search word S = {0, 0, b1, b2, ..., bm}. m-2}, or shift two bits toward the lower bits to become the search word S = {b3, b4, ..., b}. m In other respects, the filling bit at the vacancy after translation can also be "1" or "x", for example, shifting two bits towards the lower position to become the search word S = {b3, b4, ..., b}. m The search term S = {b3, b4, ..., b} or 1, 1} m ,x,x}.

[0078] Through the masking, rotation, or translation processing of the bit resolution circuit 21, the processed search word S can be flexibly and elastically mapped to the address of the word line WL of the memory array 11 by conforming to different bias conditions of the word line WL.

[0079] The segmentation circuit 22 divides the search word S into k segments S1, S2, ..., Sk, which correspond to k memory blocks M1, M2, ..., Mk of the memory array 11, respectively. k In one aspect, each segment S1, S2, ..., S... k All segments have the same length (n bits). Therefore, the first segment S1 = {b1, b2, ..., b...} n} corresponds to n memory cells in memory block M1, and the second segment S2 = {b n+1 b n+2 , ..., b 2n} corresponds to n memory units in memory block M2, and so on.

[0080] In the example above, the total length of the search word S is one unit, which is an integer multiple of the total number of memory blocks k. If the total length of the search word S is not an integer multiple of the total number of memory blocks k, for example, if the total length of the search word S is +2 units, then the last two units {b} of the search word S are ignored. kn+1 b kn+2 No data comparison is performed.

[0081] Encoding circuit 22 for each segment S1, S2, ..., S k Encoding is performed to obtain coded segments eS1, eS2, ..., eS k These correspond to memory blocks M1, M2, ..., M, respectively. k The letter line WL i For example, let the first segment S1 = {b1, b2, ..., b} n Each b in}i The encoding is transformed into a set of search row signals {SeL(i), SeL(i)'}, which correspond to word lines WL in memory block M1. i The bit b can be encoded according to different encoding schemes. i Encoding into different logical values, for example, bit b i When the logic value is "1", the search row signal {SeL(i) , SeL(i)'} is encoded as {0, 1}; while bit b i When the logic value is "0", the search row signal {SeL(i),SeL(i)'} is encoded as {1,0}.

[0082] The multiplexing circuit 24 divides each coded segment eS1, eS2, ..., eS k Guided to the corresponding memory blocks M1, M2, ..., M k For example, the encoded segment eS1 is directed to the memory block M1, and the search row signals {SeL(1), SeL(1)', SeL(2), SeL(2)', ..., SeL(n), SeL(n)'} within the encoded segment eS1 correspond to n memory cells within the memory block M1 for data comparison.

[0083] Figure 4A This is a schematic diagram of the architecture of the input circuit 20B according to a second embodiment of the present disclosure. Figure 4A As shown, the input circuit 20B of the second embodiment can perform hierarchical multiplexing. The memory array 11 can be divided into multiple memory subarrays 13A, 13B, 13C, each memory subarray including multiple memory blocks M1, M2, ..., M k Furthermore, the memory array 11 is divided into memory subarrays 13A, 13B, and 13C according to a first direction (e.g., horizontal direction), and each memory subarray 13A, 13B, and 13C is further divided into memory blocks M1, M2, ..., M according to a second direction (e.g., vertical direction). k In other words, each of the memory subarrays 13A, 13B, and 13C contains multiple memory blocks M1, M2, ..., M... k However, in this embodiment, each memory block M1, M2, ..., M... k The scope is limited to within the memory subarray and is not equivalent to Figure 1 and Figure 2 The memory blocks M1, M2, ..., M shown k The range.

[0084] The multiplexing circuit in the second embodiment includes a first multiplexing circuit 24-1 and multiple second multiplexing circuits 24-2. The first multiplexing circuit 24-1 first processes the encoded segment eS... i The data is directed to each of the second multiplexing circuits 24-2, and then via each of the second multiplexing circuits 24-2 to different memory blocks M in the corresponding memory subarrays 13A, 13B, and 13C. i .

[0085] Figure 4B This is a schematic diagram illustrating the operation of the input circuit 20B according to the second embodiment of this disclosure. Figure 4B As shown, the encoding segment eS of the search word S i Data comparison is performed in memory subarrays 13A, 13B, and 13C using a time-divisional and interlacing approach. Specifically, each memory subarray 13A, 13B, and 13C performs data comparison sequentially at different time periods, and only one memory subarray is compared within a single time period.

[0086] Furthermore, while the preceding memory subarray 13A is performing data comparison and its word line WL is in a sensing state, the next memory subarray 13B can simultaneously set up its word line WL. For example, the sensing times of the word lines WL of memory subarrays 13A, 13B, and 13C are T2_A, T2_B, and T2_C, respectively, and the setup times of memory subarrays 13A, 13B, and 13C are T1_A, T1_B, and T1_C, respectively. The sensing time T2_A of the word line WL of the preceding memory subarray 13A can overlap with the setup time T1_B of the next memory subarray 13B, and the two are arranged alternately in a pipeline manner, which can shorten the overall data comparison time of memory array 11. Similarly, the sensing time T2_B of the word line WL of memory subarray 13B can overlap with the setup time T1_C of the next memory subarray 13C.

[0087] Figure 5A This is a schematic diagram of the architecture of the output circuit 30A according to the first embodiment of this disclosure. See also... Figure 5A The output circuit 30A of the first embodiment includes a plurality of processing circuits 31A, each processing circuit 31A corresponding to a bit line BL. j And electrically connected to the corresponding bit line BL j Sense amplifier (SA) i .

[0088] In a first embodiment, each processing circuit 31A may include a logic circuit and a memory. The memory stores a logic value, which is either "1" or "0", and this logic value is updated at different times. A logic value "1" represents a logic value of "TRUE", and a logic value "0" represents a logic value of "FALSE". According to the definition of a positive potential, a logic value "1" is a high potential, and a logic value "0" is a low potential. Conversely, according to the definition of a negative potential, a logic value "1" can be a low potential, and a logic value "0" can be a high potential. On one hand, the memory may be, for example, a register 33. On the other hand, the logic circuit may be, for example, an AND gate 32. The AND gate 32 performs a logical AND operation (hereinafter referred to as a "logical AND operation") on the logic values ​​"1" or "0".

[0089] The first input terminal 32a of AND gate 32 is electrically connected to the output terminal of temporary register 33, and the second input terminal 32b of AND gate 32 is electrically connected to inductive amplifier SA. i The output terminal of AND gate 32 is fed back to the input terminal of temporary register 33. In other words, the connection between AND gate 32 and temporary register 33 forms a loop (l00p), so the output value of AND gate 32 can be successively stored back to temporary register 33 at different times to update the logic value stored in temporary register 33.

[0090] Figure 5B This is a schematic diagram illustrating the operation of an output circuit 30A according to a first embodiment of the present disclosure. See also... Figure 5B The operation of output circuit 30A is explained using the first line BL1 as an example. The search word S and memory blocks M1, M2, ..., M... k Before performing data comparison, the initial logic value of temporary register 33 is "1", and temporary register 33 outputs the logic value "1" to the first input terminal 32a of AND gate 32.

[0091] Then, search for the encoded segments eS1, eS2, ..., eS of the word S. k With memory blocks M1, M2, ..., M k Data comparisons are performed sequentially. First, taking the first line BL1 as an example, the encoding segment eS1 is compared with the memory block M1. If the encoding segment eS1 matches the data of the first line BL1 in the memory block M1, the inductive amplifier SA1 corresponding to the first line BL1 outputs a logic value "1" and transmits this logic value "1" to the second input terminal 32b of the AND gate 32. At this time, the logic values ​​of the first input terminal 32a and the second input terminal 32b of the AND gate 32 are both "1". The logic operation result of the AND gate 32 is the logic value "1" and stored back in the temporary register 33.

[0092] In subsequent time periods, the subsequent encoded segments eS2 and eS3 are compared with the memory blocks M2 and M3 in sequence. If the encoded segments eS2 and eS3 match the data of the first bit line BL1 in the memory blocks M2 and M3, the output value of the sensing amplifier SA1 is the logic value "1". Since the logic value stored in the temporary register 33 in the previous time period is "1", the result of the logical operation of the AND gate 32 remains the logic value "1".

[0093] In a later time period, the later encoded segment eS4 and the first bit line BL in memory block M4 １ Perform a data comparison; if the encoded segment eS4 does not match the first bit line BL in memory block M4... １ The data, then the sensing amplifier SA １ The output logic value is "0". At this time, the result of the logical operation of AND gate 32 is changed to the logic value "0", and the result of the logical operation is stored again in temporary register 33.

[0094] Similarly, register 33 stores the logical operation result of the current time period, while AND gate 32 performs a logical AND operation on the stored current logical operation result and the comparison result of the next data (the comparison result of the next encoded segment eS5 and the next memory block M5 of the next time period) to obtain the logical operation result of the next data. Furthermore, the logical operation result of the next data is stored back in register 33 to update the logical value stored in register 33, replacing the logical operation result stored in the previous time period.

[0095] The above operations occur simultaneously on bit lines BL1 to BL2. p And repeat the process in memory blocks M1 to M2. k Until the last data comparison result (the last encoded segment eS) k With the last memory block M k The data comparison results have been logically ANDed, and the result of the last logical operation has been stored in the bit line BL. j The corresponding temporary register is 33.

[0096] In the output circuit 30A of the first embodiment, corresponding to each bit line BL j Only an AND gate 32 and a temporary register 33 are needed to sequentially (according to the order of memory blocks M1, M2, M3...) store and update each memory block M. i The results of the data comparison.

[0097] From the above, bit line BL j If there is any memory block M i The corresponding encoding segment es does not match the search term Si The result of the logical operation of AND gate 32 is the logical value "0"; the bit line BL must be used. j All memory blocks M i All conditions must be met for the search word S to result in a logical value of "1" after the AND operation of gate 32. Referring again to Figure 5A, the output circuit 30A also includes a selection circuit to collect each bit line BL. j The selection circuit stores the logical operation results in register 33 and selects the bit line (e.g., bit line BL2) from which the logical operation result is a logical value "1". The selected bit line is an all-matched search word S. In one aspect, the selection circuit is a match address encoder 34, which further calculates and outputs the address of the selected bit line BL2. Since the output circuit 30A is used to preferentially select the bit line of the all-matched search word S, the output circuit 30A can also be called a priority encoder.

[0098] Figure 5C This is a schematic diagram of the architecture of the output circuit 30B according to a second embodiment of the present disclosure. See also... Figure 5C The output circuit 30B in the second embodiment also includes a plurality of processing circuits 31B, which are electrically connected to the corresponding bit lines BL. j SA inductive amplifier i .

[0099] In the second embodiment, each processing circuit 31B may include a counter 35 for bit line BL. j On the memory block M i The results of comparing the data with the search word S are counted. For example: if there are five memory blocks M1, M4, M5, M8, M... on the first line BL1... 11 The corresponding encoding segments eS1, eS4, eS5, eS8, and eS match the search term S. 11 If the counter 35 on the first bit line BL1 increments five times, the count value will be "five". Similarly, if twelve memory blocks Mi on the second bit line BL2 match the corresponding encoded segment of the search word S, the count value of the counter 35 on the second bit line BL2 will be "twelve".

[0100] Furthermore, the selection circuit of the output circuit 30B in the second embodiment is a comparator 36, which collects each bit line BL. j The counter 35 counts the results and compares these results to select the count value that meets the target (e.g., the highest count value, the lowest count value, or a count value greater than a predetermined value, etc.). For example, the bit line BL2 with the highest count value "twelve" is selected.

[0101] Although not all memory blocks on the selected bit line BL2 match the search word S, the bit line BL2 has the largest number (highest count value) of memory blocks matching the search word S. Therefore, the selected bit line BL2 is the closest or most-matched search word S. The comparator 36 also calculates and outputs the address of the selected bit line BL2.

[0102] Figure 5D This is a schematic diagram of the architecture of the output circuit 30C according to the third embodiment of this disclosure. Referring to Figure 5D, the output circuit 30C of the third embodiment covers the content of the first and second embodiments; wherein, corresponding to each bit line BL j The processing circuit 31C includes an AND gate 32, a temporary register 33, and a counter 35. Each bit line BL j SA inductive amplifier j The output terminal is connected to AND gate 32 and counter 35.

[0103] The result of the logical operation of each AND gate 32 is sent to the matching address encoder 34 to obtain the bit line BL of the perfect match search word S. j The address. On the other hand, the count value of each counter 35 is sent to the comparator 36 to obtain the bit line BL that is closest to the search word S. j The address.

[0104] Figure 6A This is a flowchart of a data search method for a memory device according to the present disclosure. The data search method of the present disclosure includes steps S11 to S16, which roughly correspond to... Figures 1 to 5D The operation of the memory device 10 shown.

[0105] See Figure 6A First, in step S11, a search term S = {b1, b2, ..., b} is received and temporarily stored. m In subsequent steps, input functions are performed on the search word S, including bit parsing, segmentation, encoding, and multiplexing guidance.

[0106] In step S12, bit parsing is performed on the search word S to mask, rotate, or translate multiple bits in the search word S. For example, the search word S = {b1, b2, ..., bm} is masked to the search word S = {b1, b2, ..., bm}. n-1 ,x,x,x,b n+3 , ..., b m}, or the search term S = {b1, b2, ..., b m Rotate to search word S = {b n-1 b m b1, b2, ..., b m-2Alternatively, the search term S = {b1, b2, ..., bm} can be shifted to the search term S = {0, 0, b1, b2, ..., bm}. m-2}

[0107] Next, in step S13, the search word S is segmented into k segments S1, S2, ..., Sk, where each segment Si corresponds to a memory block M. i .

[0108] Next, in step S14, encoding is performed to encode the segments S1, S2, ..., Sk of the search word S into encoded segments eS1, eS2, ..., eSk, respectively. k Each coded segment eS i This includes the search row signals {SeL(i), SeL(i)'}, which are mapped to the word line WL in the memory block via word line address bias (WL bias). i .

[0109] Next, in step S15, multiplexing guidance is performed to separate the different coded segments eS1, eS2, ..., eS k Guided to the corresponding memory blocks M1, M2, ..., M k And each coded segment eS is stored in memory array 11. i With the corresponding memory block M i The data were compared.

[0110] Next, in step S16, an output function is executed to consolidate each bit line BL of the memory array 11. j The associated memory blocks M i The results are compared with the data of the search word S to obtain the bit line BL that best matches the search word S. j The address; hereby, the data search method disclosed herein is completed. Detailed implementation of step S16 may have two aspects of embodiments, shown in Figures 6B and 6C respectively.

[0111] See Figure 6B The first embodiment is shown. First, in step S21, an initial value is stored. This initial value is the logical value "1".

[0112] Next, in step S22, a logical AND operation is performed on the current data comparison result (the data comparison result between the current encoded segment eS1 and the current memory block M1) and the stored initial value. The result of this logical operation is then stored to replace the previously stored initial value.

[0113] Next, in step S23, a logical AND operation is performed between the next data comparison result (the data comparison result between the next encoded segment eS2 and the next memory block M2) and the previously stored logical operation result (the logical operation result stored in step S22) to obtain the next logical operation result. Furthermore, the next logical operation result is stored to replace the previously stored logical operation result.

[0114] Next, in step S24, the comparison result of the last data (the last encoded segment eS) is determined. k With the last memory block M k Check if the data comparison result has been logically ANDed to obtain the last logical operation result. If the result is "No", repeat step S23; if the result is "Yes", execute step S25.

[0115] Then, in step S25, each line BL is collected. j The last stored logical operation result is used to select the bit line whose logical operation result is "1". The selected bit line is the exact match or perfect match search word S.

[0116] Then, in step S26, the address of the selected bit line is calculated and the address of the bit line is output.

[0117] For a second embodiment of step S16, please refer to [link to embodiment]. Figure 6C In step S31, the output function is applied to the bit line BL. j On the memory block M i The results are counted by comparing them with the data of the search term S.

[0118] If the encoded segments eS1, eS2, and eS3 all match memory blocks M1, M2, and M3, the count is incremented three times to obtain a count value of "three". If the subsequent encoded segment eS4 does not match memory block M4, no increment is performed, and the count value remains at "three". In other words, the output function counts the number of memory blocks that match the search word S.

[0119] Next, in step S32, each line BL is collected. j The counting results are calculated and compared to select the count value that matches the target. For example, the one with the highest count value is selected, and the bit line with the highest count value is the closest or most matching search word S.

[0120] Then, in step S33, the address of the selected bit line is calculated and the address of the bit line is output.

[0121] Through the above embodiments of this disclosure, the memory array is divided into multiple memory blocks M. i The input function is performed via input circuit 20 to divide the search word S into multiple segments S. i And encoded into the encoding segment eS i And respectively with the corresponding memory block M i By performing data comparisons, it can handle search words S with relatively long lengths. Furthermore, the memory array can be divided into multiple memory subarrays for time-division interleaving data comparisons, thus improving data search efficiency for large memory arrays.

[0122] Furthermore, the output circuit 30 of this disclosure may include various output functions, enabling flexible output of diverse data comparison results.

[0123] Furthermore, the input circuit 20 and output circuit 30 of this disclosure can be applied to memory arrays with different circuit architectures or memory types, such as NAND-string memory, floating-gate memory, charge-trapping memory, or FinFET memory.

[0124] While this disclosure has been detailed above with reference to preferred embodiments and examples, it is understood that these examples are intended to be illustrative rather than limiting. It is anticipated that those skilled in the art will conceive of various modifications and combinations that fall within the spirit of this disclosure and the scope of the appended claims.

Claims

1. A memory device for data retrieval, comprising: A memory array having multiple memory blocks for storing data and multiple bit lines, wherein the memory array is divided into multiple memory subarrays relative to a first direction, and each memory subarray is divided into memory blocks relative to a second direction perpendicular to the first direction. An input circuit, including: A segmentation circuit receives a search word and divides the search word into multiple segments; An encoding circuit encodes these segments into multiple encoded segments, each corresponding to a memory block; and A multiplexing circuit guides these coded segments to these memory blocks. Each coded segment is compared with each memory block of each memory subarray in a time-division interleaved manner to obtain a data comparison result. An output circuit obtains the addresses of the bit lines that match the search word based on the comparison results of the data in each memory block.

2. The memory device of claim 1, wherein, The input circuit also includes: A single-bit parsing circuit can mask, rotate, or translate multiple bits of the search word.

3. A memory device for data retrieval, comprising: A memory array having multiple memory blocks for storing data and multiple bit lines; An input circuit receives and processes a search word, and directs the processed search word to these memory blocks. The processed search word is compared with the data in these memory blocks in the memory array to obtain multiple data comparison results. as well as An output circuit, including: Multiple processing circuits, each corresponding to a bit line, process the data comparison results of each memory block corresponding to each bit line. Each processing circuit includes: a temporary register storing a logic value, which is updated at different time periods; and a logic gate performing a logical AND operation between the logic value stored in the temporary register at the current time period and the data comparison result corresponding to the bit line to obtain a logic operation result, and storing the logic operation result back into the temporary register to update the logic value stored in the temporary register at the current time period; and A selection circuit collects and processes the comparison results of each bit line, and obtains the addresses of the bit lines that match the search word based on the comparison results of each bit line. The selection circuit selects the registers whose logic value is "1" to obtain the addresses of the bit lines that completely match the search word.

4. A data search method for a memory device, comprising: Receive a search term and divide the search term into multiple segments; These segments are encoded into multiple encoded segments, each corresponding to a multiple memory block of a memory array, and the memory array has multiple bit lines; Based on a first direction, the memory array is divided into multiple memory subarrays; Based on a second direction perpendicular to the first direction, each memory subarray is divided into multiple memory blocks; These coded segments are directed to these memory blocks; In this memory array, these coded segments are compared with each memory block of each memory subarray in a time-division interleaved manner to obtain a data comparison result; as well as The addresses of the bit lines that match the search word are obtained based on the comparison results of the data in each memory block.

5. The data search method according to claim 4, wherein, Before the step of segmenting the search term into multiple sections, the following is also included: Mask, rotate, or translate multiple bits of the search term.

6. A data search method for a memory device, comprising: Receive and process a search term; The processed search word is directed to multiple memory blocks of a memory array, wherein the memory array has multiple bit lines; Each bit line corresponds to a different bit line, and the processed search word is compared with each memory block to obtain multiple data comparison results; Collect and process the comparison results of each bit line; as well as The addresses of the bit lines that match the search word are obtained based on the comparison results of the data of each bit line. The steps for collecting and processing the data comparison results for each bit line also include: Each bit line is associated with a logic value, which is then updated at different times. For each bit line, a logical AND operation is performed on the logical value stored in the current time period and the data comparison result to obtain a logical operation result; The result of the logical operation is stored back to update the logical value stored in the current time period; and Select the bit lines whose logical value is "1" stored in each bit line to obtain the addresses of these bit lines that completely match the search word.

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