Antifuse memory circuit

Abstract

The embodiments of the present application are applied to the field of semiconductor circuit design to provide an anti-fuse memory circuit, including: a memory array including a plurality of anti-fuse memory cells; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines; a second switching transistor for connecting the bit lines to a transmission wire; a third switching transistor for discharging the transmission wire; a reading module including a first input terminal, a second input terminal, and a sampling input terminal, the first input terminal is connected to the transmission wire, the second input terminal is used to receive a reference voltage, and the sampling input terminal is used to receive a sampling signal; a compensation module connected to the third switching transistor for slowing down the voltage reduction speed of the transmission wire, and by slowing down the discharging speed of the third switching transistor to the transmission conductor, thereby ensuring the accuracy of the data read out by the anti-fuse memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit design, and particularly to an anti-fuse memory circuit. Background Art

[0002] An anti-fuse memory can be implemented by an anti-fuse memory cell array. The gate oxide dielectric of the anti-fuse memory cell will break down when a high voltage is applied. After breakdown, the impedance of the path decreases; the information stored in the anti-fuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0003] During the data programming stage of the anti-fuse memory, the discharge transistor for discharging the transmission wire needs to perform rapid discharge. Therefore, the discharge transistor is usually designed as a transistor with a relatively large size.

[0004] However, during the data reading stage of the anti-fuse memory, although the discharge transistor is turned off, there will still be leakage current due to the relatively large size of the discharge transistor, that is, the discharge transistor will still discharge the transmission wire. When the anti-fuse memory cell is not programmed, the voltage of the transmission wire may cause a reading error due to the discharge of the discharge transistor. Summary of the Invention

[0005] An embodiment of this application provides an anti-fuse memory circuit, which ensures the accuracy of the data read out by the anti-fuse memory by slowing down the discharge speed of the discharge transistor to the transmission conductor.

[0006] An embodiment of this application provides an anti-fuse memory circuit, including: a storage array including a plurality of anti-fuse memory cells, and the anti-fuse memory cells characterize the stored 1-bit data by whether the gate oxide layer is broken down; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines for turning on the selected first switching transistors according to a row selection signal, wherein the extending direction of the bit lines and the extending direction of the word lines are perpendicular to each other; a second switching transistor for connecting the bit lines to a transmission wire; a third switching transistor for discharging the transmission wire; a reading module including a first input terminal, a second input terminal, and a sampling input terminal, the first input terminal is connected to the transmission wire, the second input terminal is used for receiving a reference voltage, and the sampling input terminal is used for receiving a sampling signal; a compensation module connected to the third switching transistor for slowing down the voltage reduction speed of the transmission wire caused by the leakage of the third switching transistor; when the sampling signal is a valid pulse, the reading module compares the input voltage of the first input terminal with the reference voltage to output the 1-bit data stored in the anti-fuse memory cell.

[0007] In the data programming stage, the third switching transistor is used to discharge the transmission wire, so as to ensure the accuracy of programming the antifuse memory cell; in the data reading stage, the third switching transistor has a leakage current to discharge the transmission wire, and due to the buffering of the compensation module, the discharge speed of the third switching transistor to the transmission wire is slowed down. When the antifuse memory cell to be read has been programmed, the gate oxide layer of the antifuse memory cell has been broken down, the equivalent resistance is small, and the discharge speed to the transmission wire is fast; due to the action of the compensation module, the discharge speed of the third switching transistor to the transmission wire is slower, which does not affect the discharge of the antifuse memory cell to the transmission wire. When the sampling signal is a valid pulse, the input voltage of the transmission wire connected to the first input terminal is less than the reference voltage; when the antifuse memory cell to be read has not been programmed, the gate oxide layer of the antifuse memory cell has not been broken down, the equivalent resistance is large, and the discharge speed to the transmission wire is slow; due to the action of the compensation module, the discharge speed of the third switching transistor to the transmission wire is also slower, so as to ensure that when the sampling signal is a valid pulse, the input voltage of the transmission wire connected to the first input terminal is greater than the reference voltage, that is, to ensure the accuracy of reading data by the antifuse memory. Brief Description of the Drawings

[0008] Figure 1 It is a V-t schematic diagram of the antifuse memory cell before improvement in the data reading stage;

[0009] Figure 2 It is a circuit schematic diagram of an antifuse memory circuit provided by some embodiments of the present application;

[0010] Figure 3 It is a circuit schematic diagram of another antifuse memory circuit provided by some embodiments of the present application;

[0011] Figure 4 It is a V-t schematic diagram of the improved antifuse memory cell in the data reading stage provided by some embodiments of the present application. Detailed Description of the Invention

[0012] The antifuse memory is implemented by an antifuse memory array. The antifuse memory array includes a plurality of antifuse memory cells. The gate oxide medium of the antifuse memory cell will be broken down after applying a high voltage. After breakdown, the impedance of the path decreases. Therefore, the information stored in the antifuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0013] Specifically, during the data reading phase, after the antifuse memory cell is broken down, the path impedance decreases. When this antifuse memory cell is activated by the bit line and the word line, it can quickly discharge the charge after the transmission line is precharged, so that the data readout is at a low level. Additionally, when the antifuse memory cell is not broken down, the path impedance is extremely large. When this antifuse memory cell is activated by the bit line and the word line, the discharge rate of the charge after the transmission line is precharged is slow, so that the data readout is at a high level.

[0014] Therefore, when programming data into the antifuse memory, the antifuse memory cell that is broken down by applying a high voltage is characterized as storing data "0", and the antifuse memory cell that is not applied with a high voltage is characterized as storing data "1".

[0015] However, during the data programming phase of the antifuse memory, the discharge transistor for discharging the transmission wire needs to perform rapid discharge. Therefore, the discharge transistor is usually designed as a transistor with a relatively large size. During the data reading phase of the antifuse memory, although the discharge transistor is turned off, due to the relatively large size of the discharge transistor, there will still be leakage current, that is, the discharge transistor will still discharge the transmission wire, resulting in that even if the antifuse memory cell is not broken down and the path impedance is extremely large, when this antifuse memory cell is activated by the bit line and the word line, the discharge rate of the charge after the transmission line is precharged is slow, but the leakage current of the discharge transistor also has a discharging effect on the transmission line, causing the data that should originally be read as a high level to be finally read as a low level, and thus being recognized as a broken-down antifuse memory cell, resulting in a read error of the antifuse memory.

[0016] Reference Figure 1 , for the programmed antifuse memory cell, the equivalent resistance is small, and the voltage after precharging the transmission wire is quickly discharged through the conducting antifuse memory cell. When the sampling signal CLK is at an effective level, the input voltage of the transmission wire drops to V1, and V1 < reference voltage V TRIP ; for the unprogrammed antifuse memory cell, the equivalent resistance is large, and the voltage after precharging the transmission wire should not be able to be quickly discharged through the antifuse memory cell. However, due to the leakage of the discharge transistor, when the sampling signal CLK is at an effective level, the output voltage of the transmission wire drops to V2, and V2 < reference voltage V TRIP , thus resulting in a read error of the antifuse memory.

[0017] An embodiment of the present application provides an anti-fuse memory circuit, including: a memory array including a plurality of anti-fuse memory cells, where the anti-fuse memory cells characterize the stored 1-bit data by whether the gate oxide layer is broken down; bit lines connected to the anti-fuse memory cells arranged in the extending direction of the bit lines, and the anti-fuse memory cells are electrically connected to the bit lines through first switching transistors; word lines connected to the first switching transistors arranged in the extending direction of the word lines, for turning on the selected first switching transistors according to a row selection signal, where the extending direction of the bit lines and the extending direction of the word lines are perpendicular to each other; a second switching transistor for connecting the bit lines to a transmission wire; a third switching transistor for discharging the transmission wire; a reading module including a first input terminal, a second input terminal, and a sampling input terminal, the first input terminal is connected to the transmission wire, the second input terminal is used to receive a reference voltage, and the sampling input terminal is used to receive a sampling signal; a compensation module connected to the third switching transistor for slowing down the voltage reduction speed of the transmission wire caused by the leakage of the third switching transistor; when the sampling signal is a valid pulse, the reading module compares the input voltage of the first input terminal with the reference voltage to output the 1-bit data stored in the anti-fuse memory cell.

[0018] Those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0019] Figure 2 A circuit schematic diagram of an anti-fuse memory circuit provided for some embodiments Figure 3 A circuit schematic diagram of another anti-fuse memory circuit provided for some embodiments Figure 4 A V-t schematic diagram of the improved anti-fuse memory cell in the data reading stage for some embodiments. The following further details the anti-fuse memory circuit provided for some embodiments with reference to the accompanying drawings, as follows:

[0020] It should be noted that the so-called "source electrode" or "drain electrode" in the following embodiments is only used to distinguish the ports of the MOS transistor and is not limited in any way, that is, the concepts of the source electrode and the drain electrode can be interchanged.

[0021] Refer to Figure 2 , the anti-fuse memory circuit, including:

[0022] A memory array including a plurality of anti-fuse memory cells FsBln01…FsBln0x, FsBln11…FsBln1x, FsBln21…FsBln2x, FsBln31…FsBln3x, and the anti-fuse memory cells characterize the stored 1-bit data by whether the gate oxide layer is broken down.

[0023] It should be noted that taking the antifuse memory cell characterized by "FsBln01" as an example, where "0" represents the 0th word line to which the antifuse memory cell is connected, and "1" represents the 1st bit line to which the antifuse memory cell is connected; taking the antifuse memory cell characterized by "FsBln2x" as an example, where "2" represents the 2nd word line to which the antifuse memory cell is connected, and "x" represents the xth bit line to which the antifuse memory cell is connected; in addition, in the description of some embodiments, if there is no numerical suffix after the label of FsBln, it indicates that no specific antifuse memory cell is specified.

[0024] The bit line BL is connected to the antifuse memory cells FsBln arranged in the extending direction of the bit line BL, and the antifuse memory cells FsBln are connected to the bit line BL through the first switching transistors 1Add. Specifically, the first switching transistors 1Add include: 1Add01…1Add0x, 1Add11…1Add1x, 1Add21…1Add2x, 1Add31…1Add3x.

[0025] It should be noted that taking the first switching transistor characterized by "1Add01" as an example, where "01" represents being connected to the antifuse memory cell "FsBln01", that is, the first switching transistor 1Add01 serves as the switching transistor of the antifuse memory cell FsBln01; taking the first switching transistor characterized by "1Add2x" as an example, where "2x" represents being connected to the antifuse memory cell "FsBln2x", that is, the first switching transistor 1Add2x serves as the switching transistor of the antifuse memory cell FsBln2x; in addition, in the description of some embodiments, if there is no numerical suffix after the label of 1Add, it indicates that no specific first switching transistor is specified.

[0026] The word line WL is connected to the first switching transistors 1Add arranged in the extending direction of the word line WL, and is used to turn on the selected first switching transistors 1Add according to the row select signal. Among them, the extending direction of the bit line BL and the extending direction of the word line WL are perpendicular to each other; it should be noted that the row select signal is the word line select signal, which is used to select a target word line WL among many word lines WL and turn on the first switching transistors 1Add connected to the target word line WL.

[0027] Specifically, the gate of the first switching transistor 1Add is connected to the word line WL, one end of the source or drain is connected to the antifuse memory cell FsBln, and the other end is connected to the bit line BL.

[0028] In some embodiments, in the extending direction of the bit line BL, two adjacent first switching transistors 1Add are connected to the bit line BL through the same conductive wire. Connecting the bit lines between two adjacent first switching transistors 1Add through the same conductive wire enables the source or drain of two adjacent first switching transistors 1Add to be shared during the design, thereby reducing the layout area of the antifuse memory array or integrating more antifuse memory cells under the same area.

[0029] A second switching transistor 2Add is used to connect the bit line BL to the transmission wire 100.

[0030] The gate of the second switching transistor 2Add is used to receive a column select signal. One end of the source or drain is connected to the bit line BL, and the other end is connected to the transmission wire 100. The column select signal is used to select and conduct the bit line BL connected to the selected second switching transistor 2Add; it should be noted that the column select signal is the bit line select signal, which is used to select a target bit line BL from among a plurality of bit lines BL and conduct the second switching transistor 2Add connected to the target bit line BL.

[0031] Specifically, the second switching transistor 2Add includes: 2Add1…2Addx.

[0032] Taking the second switching transistor characterized by "2Add1" as an example, where "1" represents the connection to the first bit line, and the first bit line is connected to the antifuse memory cell "FsBlnz1" through the first switching transistor "1Addz1", where z is any integer from 0 to x; taking the second switching transistor characterized by "2Addx" as an example, where "x" represents the connection to the x-th bit line, and the x-th bit line is connected to the antifuse memory cell "FsBlnzx" through the first switching transistor "1Addzx", where z is any integer from 0 to x; in addition, in the description of some embodiments, if there is no numerical suffix after the label of 2Add, it indicates that a specific second switching transistor is not specified.

[0033] A third switching transistor 3Add is used to discharge the transmission wire 100.

[0034] The gate of the third switching transistor 3Add is used to receive a discharge signal. One end of the source or drain is connected to the transmission wire 100, and the other end is grounded. The discharge signal is used to conduct the third switching transistor 3Add, thereby discharging the charge in the transmission wire 100.

[0035] A reading module 102 includes a first input terminal +, a second input terminal -, and a sampling input terminal C. The first input terminal + is connected to the transmission wire 100, and the second input terminal - is used to receive a reference voltage V TRIP , and the sampling input terminal C is used to receive a sampling signal CLK.

[0036] The compensation module 101 is connected to the third switching transistor 3Add and is used to slow down the voltage reduction rate of the transmission wire 100 caused by the leakage of the third switching transistor.

[0037] In some embodiments, it further includes: a pre-charge MOS transistor, one end of the source or drain is used to receive a pre-charge voltage, the other end is connected to the transmission wire 100, and the gate is used to receive a pre-charge signal PRE. The pre-charge MOS transistor is used to pre-charge the transmission wire 100 to the pre-charge voltage according to the pre-charge signal PRE; additionally, in some embodiments, the pre-charge voltage is the internal power supply voltage V DD .

[0038] When the sampling signal CLK is a valid pulse, the reading module 102 compares the input voltage V at the first input terminal + with the reference voltage V TRIP to output 1-bit data stored in the selected antifuse memory cell FsBln.

[0039] The working principle of the antifuse memory circuit provided in some embodiments will be described in detail below by taking the antifuse memory cells FsBln01 and FsBln11 as examples, specifically as follows:

[0040] In the data programming stage, a high voltage is applied to the antifuse memory cell FsBln01 to cause the gate oxide dielectric of the antifuse memory cell FsBln01 to break down. A low voltage or no voltage is applied to the antifuse memory cell FsBln11, and the gate oxide dielectric of the antifuse memory cell FsBln11 is not broken down.

[0041] Specifically, during the process of applying a high voltage to the antifuse memory cell FsBln01, the first switching transistor 1Add01, the second switching transistor 2Add1, and the third switching transistor 3Add are turned on, and the charge in the transmission wire 100 is discharged through the third switching transistor 3Add to ensure the accuracy of data programming for the antifuse memory cell FsBln01.

[0042] The reading module 102 includes: a comparator 112, including a first input terminal +, a second input terminal -, and an output terminal. A latch device 122, including a sampling input terminal C and a data input terminal D, and the data input terminal D is connected to the output terminal of the comparator; the comparator 112 is used to compare the input voltage V at the first input terminal + with the reference voltage V TRIP and the latch device 122 is used to output 1-bit data stored in the antifuse memory cell.

[0043] In the data reading stage, the third switching transistor 3Add is turned off, and the pre-charge MOS transistor receives the pre-charge signal PRE to conduct the source and the drain. At this time, the transmission wire 100 is connected to the pre-charge voltage and is thus pre-charged to the pre-charge voltage. Although the third switching transistor 3Add is turned off, due to its large size, there will still be leakage current, that is, the third switching transistor 3Add will still discharge the transmission wire. To reduce the discharge effect of the third switching transistor 3Add, the voltage of the transmission wire 100 is compensated by the compensation module 101.

[0044] In one example, referring to Figure 2 , the compensation module 101 includes: a control unit that generates an adjustment signal V based on the temperature of the third switching transistor 3Add BIAS ; a charging MOS transistor, one of the source or the drain of which is used to receive the internal power supply voltage V DD , and the other is connected to the transmission wire 100, and the gate is used to receive the adjustment signal V BIAS ; the adjustment signal V BIAS is configured such that when the temperature of the third switching transistor increases, it is used to increase the charging speed of the charging MOS transistor, and when the temperature of the third switching transistor decreases, it is used to decrease the charging speed of the charging MOS transistor. The reason is that: the leakage current ability of the third switching transistor 3Add is positively correlated with the temperature. The higher the temperature of the third switching transistor 3Add, the stronger the leakage current ability, and the lower the temperature of the third switching transistor 3Add, the weaker the leakage current ability. Therefore, when the temperature of the third switching transistor 3Add increases, it is necessary to increase the charging speed of the charging MOS transistor to strengthen the voltage compensation for the transmission conductor 100; when the temperature of the third switching transistor 3Add decreases, it is necessary to decrease the charging speed of the charging MOS transistor to weaken the voltage compensation for the transmission wire 100.

[0045] Specifically, the charging MOS transistor is a PMOS. The source of the charging MOS transistor is used to receive the internal power supply voltage V DD , the drain is connected to the transmission wire 100, and the gate is used to receive the adjustment signal V BIAS . Correspondingly, the adjustment signal V BIAS is configured such that when the temperature of the third switching transistor 3Add increases, the voltage of the generated adjustment signal V BIAS is decreased to increase the conduction current of the charging MOS transistor. For a PMOS transistor, decreasing the gate voltage means increasing the opening degree of the conduction channel between the source and the drain, thereby increasing the charging ability of the charging MOS transistor, that is, increasing the conduction current of the charging MOS transistor; when the temperature of the third switching transistor 3Add decreases, the voltage of the generated adjustment signal V BIAS is increased to decrease the conduction current of the charging MOS transistor. For a PMOS transistor, increasing the gate voltage means decreasing the opening degree of the conduction channel between the source and the drain, thereby decreasing the charging ability of the charging MOS transistor, that is, decreasing the conduction current of the charging MOS transistor.

[0046] It should be noted that the charging MOS transistor can also be an NMOS transistor. Correspondingly, the regulation signal V BIAS is configured to increase the voltage of the generated regulation signal V when the temperature of the third switching transistor 3Add increases; when the temperature of the third switching transistor 3Add decreases, the voltage of the generated regulation signal V BIAS is decreased. BIAS

[0047] Specifically, the control unit includes: a temperature acquisition sub-unit for acquiring the temperature of the third switching transistor 3Add; a signal generation sub-unit connected to the temperature acquisition sub-unit for generating a regulation signal V according to the temperature of the third switching transistor 3Add BIAS .

[0048] In this example, due to the charging of the transmission wire 100 by the compensation module 101, the discharge of the transmission wire 100 by the third switching transistor 3Add due to leakage is compensated, thereby slowing down the voltage reduction speed of the transmission wire 100 caused by the leakage of the third switching transistor 3Add, thus avoiding the problem of inaccurate reading of the anti-fuse memory caused by the leakage of the third switching transistor 3Add.

[0049] In another example, the compensation module includes: a fourth switching transistor 4Add, which is arranged between the third switching transistor 3Add and the transmission wire 100, or is arranged on the line where the third switching transistor 3Add is grounded, for turning on or off the fourth switching transistor 4Add according to the supplementary discharge signal.

[0050] Among them, the voltage waveform of the supplementary discharge signal is the same as that of the discharge signal, that is, if the discharge signal indicates that the third switching transistor 3Add is turned on, the supplementary discharge signal indicates that the fourth switching transistor 4Add is turned on; if the discharge signal indicates that the third switching transistor 3Add is turned off, the supplementary discharge signal indicates that the fourth switching transistor 4Add is turned off.

[0051] Specifically, since the compensation module 101 discharges in series with the third switching transistor 3Add, in the data programming stage, when the third switching transistor 3Add and the fourth switching transistor 4Add are turned on, it will not affect the current discharge of the third switching transistor 3Add; in the data reading stage, when the third switching transistor 3Add and the fourth switching transistor 4Add are turned off simultaneously, the equivalent resistance of the branch where the third switching transistor 3Add is located is increased, thereby reducing the leakage current of the third switching transistor 3Add and slowing down the voltage reduction speed of the transmission wire 100 caused by the leakage of the third switching transistor 3Add, thus avoiding the problem of inaccurate reading of the anti-fuse memory caused by the leakage of the third switching transistor 3Add.

[0052] In one example, refer to Figure 3 ​, the fourth switching transistor 4Add is arranged on the line where the third switching transistor 3Add is grounded, that is, the drain of the fourth switching transistor 4Add is connected to the source of the third switching transistor 3Add, the source is grounded, and the gate is used to receive the supplementary discharge signal.

[0053] In another example, the fourth switching transistor 4Add is arranged between the third switching transistor 3Add and the transmission wire 100, that is, the drain of the fourth switching transistor 4Add is connected to the transmission wire 100, the source is connected to the drain of the third switching transistor 3Add, and the gate is used to receive the supplementary discharge signal.

[0054] In some embodiments, the third switching transistor 3Add and the fourth switching transistor 4Add are NMOS; it should be noted that the third switching transistor 3Add and the fourth switching transistor 4Add can also use PMOS transistors.

[0055] Reference Figure 4 , for the antifuse memory provided in some embodiments, the data reading process is as follows:

[0056] When reading the data stored in the antifuse memory cell FsBln01, the gate oxide medium of the antifuse memory cell FsBln01 breaks down and the impedance is very small. When the first switching transistor 1Add01 and the second switching transistor 2Add1 are turned on, the charge on the transmission wire 100 is discharged through the antifuse memory cell FsBln01, so as to quickly pull down the input voltage V of the first input terminal +, making the input voltage V input at the first input terminal + less than the reference voltage V TRIP , when the sampling signal CLK is an effective pulse, at this time the reading module 102 outputs a low level, corresponding to the stored data "0".

[0057] When reading the data stored in the antifuse memory cell FsBln11, the gate oxide medium of the antifuse memory cell FsBln11 does not break down and the impedance is extremely large. When the first switching transistor 1Add11 and the second switching transistor 2Add1 are turned on, the charge on the transmission wire 100 is discharged slowly through the antifuse memory cell FsBln11, and cannot quickly pull down the input voltage V of the first input terminal +, so that when the sampling signal CLK is an effective pulse, the input voltage V input at the first input terminal + is still greater than the reference voltage V TRIP , at this time the reading module 102 outputs a high level, corresponding to the stored data "1".

[0058] It should be noted that in some embodiments, the first input terminal is used as the non-inverting input terminal of the comparator, and the second input terminal is used as the inverting input terminal of the comparator, which is only used to illustrate the anti-fuse memory circuit provided in this embodiment. In other embodiments, the second input terminal may receive a transmission wire, and the first input terminal may receive a reference voltage. At this time, the gate oxide dielectric of the anti-fuse memory cell breaks down. During the read process, the read module 102 outputs a high level corresponding to the stored data "0"; when the gate oxide dielectric of the anti-fuse memory cell does not break down, during the read process, the read module 102 outputs a low level corresponding to the stored data "1". In addition, in some embodiments, the latch device 122 is illustrated by taking a D flip-flop as an example, which is only used to illustrate the anti-fuse memory circuit provided in this embodiment. In other embodiments, the latch device may also be a latch.

[0059] Continuing to refer to Figure 2 , in some embodiments, the anti-fuse memory circuit further includes: a voltage stabilizing capacitor Cap, one side electrode plate is connected to the transmission wire 100, and the other side electrode plate is grounded, which is used to stabilize the voltage of the transmission wire 100 and prevent the voltage of the transmission wire 100 from jumping.

[0060] In the data programming stage, the third switching transistor is used to discharge the transmission wire, so as to ensure the accuracy of programming the anti-fuse memory cell; in the data reading stage, the third switching transistor has a leakage current to discharge the transmission wire. Due to the buffering of the compensation module, the discharging speed of the third switching transistor to the transmission wire is slowed down. When the anti-fuse memory cell to be read has been programmed, the gate oxide layer of the anti-fuse memory cell has been broken down, the equivalent resistance is small, and the discharging speed to the transmission wire is fast; due to the action of the compensation module, the discharging speed of the third switching transistor to the transmission wire is slower, which does not affect the discharging of the anti-fuse memory cell to the transmission wire. When the sampling signal is a valid pulse, the input voltage of the transmission wire connected to the first input terminal is less than the reference voltage; when the anti-fuse memory cell to be read has not been programmed, the gate oxide layer of the anti-fuse memory cell has not been broken down, the equivalent resistance is large, and the discharging speed to the transmission wire is slow; due to the action of the compensation module, the discharging speed of the third switching transistor to the transmission wire is also slower, so as to ensure that when the sampling signal is a valid pulse, the input voltage of the transmission wire connected to the first input terminal is greater than the reference voltage, that is, to ensure the accuracy of reading data from the anti-fuse memory.

[0061] It is worth mentioning that each unit involved in the above embodiments is a logic unit. In practical applications, a logic unit may be a physical unit, a part of a physical unit, or may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in the above embodiments, but this does not mean that there are no other units in the above embodiments.

[0062] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

Claims

1. An anti-fuse memory circuit, characterized in that, Comprising: A storage array including a plurality of antifuse storage cells, and the antifuse storage cells characterize the stored 1-bit data by whether the gate oxide layer is broken down; Bit lines connected to the antifuse storage cells arranged in the extending direction of the bit lines, and the antifuse storage cells are electrically connected to the bit lines through first switching transistors; Word lines connected to the first switching transistors arranged in the extending direction of the word lines, for turning on the selected first switching transistors according to a row selection signal, wherein the extending direction of the bit lines and the extending direction of the word lines are perpendicular to each other; A second switching transistor for connecting the bit lines to a transmission wire; A third switching transistor for discharging the transmission wire; A reading module including a first input terminal, a second input terminal, and a sampling input terminal, the first input terminal is connected to the transmission wire, the second input terminal is for receiving a reference voltage, and the sampling input terminal is for receiving a sampling signal; A compensation module connected to the third switching transistor for slowing down the voltage reduction rate of the transmission wire caused by the leakage of the third switching transistor; When the sampling signal is a valid pulse, the reading module compares the input voltage of the first input terminal with the reference voltage to output the 1-bit data stored in the antifuse storage cell.

2. The anti-fuse memory circuit according to claim 1, wherein The compensation module includes: A control unit for generating an adjustment signal based on the temperature of the third switching transistor; A charging MOS transistor, one of the source or the drain is for receiving an internal power supply voltage, the other is connected to the transmission wire, and the gate is for receiving the adjustment signal; The adjustment signal is configured such that when the temperature of the third switching transistor increases, it is used to increase the charging speed of the charging MOS transistor, and when the temperature of the third switching transistor decreases, it is used to decrease the charging speed of the charging MOS transistor.

3. The anti-fuse memory circuit according to claim 2, characterized in that, The control unit includes: A temperature acquisition sub-unit for acquiring the temperature of the third switching transistor; A signal generation sub-unit connected to the temperature acquisition sub-unit for generating the adjustment signal according to the temperature of the third switching transistor.

4. The anti-fuse memory circuit according to claim 2, wherein The charging MOS transistor is a PMOS, the source of the charging MOS transistor is for receiving the internal power supply voltage, the drain is connected to the transmission wire, and the gate is for receiving the adjustment signal.

5. The anti-fuse memory circuit according to claim 4, wherein, The adjustment signal is configured as: When the temperature of the third switching transistor increases, the voltage of the generated adjustment signal is decreased to increase the conduction current of the charging MOS transistor; When the temperature of the third switching transistor decreases, the voltage of the generated adjustment signal is increased to decrease the conduction current of the charging MOS transistor.

6. The anti-fuse memory circuit according to claim 1, characterized in that One end of the source or the drain of the third switching transistor is connected to the transmission wire, the other end is grounded, and the gate is for receiving a discharge signal for discharging the charge in the transmission wire according to the discharge signal.

7. The anti-fuse memory circuit according to claim 6, wherein The compensation module includes: A fourth switching transistor provided between the third switching transistor and the transmission wire or on the line where the third switching transistor is grounded, for turning on or off the fourth switching transistor according to a supplementary discharge signal; Wherein, the voltage of the supplementary discharge signal has the same waveform as the discharge signal.

8. The anti-fuse memory circuit according to claim 7, characterized in that, The drain of the fourth switching transistor is connected to the transmission wire, the source is connected to the drain of the third switching transistor, and the gate is used to receive the supplementary discharge signal.

9. The anti-fuse memory circuit according to claim 7, wherein The drain of the fourth switching transistor is connected to the source of the third switching transistor, the source is grounded, and the gate is used to receive the supplementary discharge signal.

10. The anti-fuse memory circuit according to claim 7, wherein The third switching transistor and the fourth switching transistor are NMOS.

11. The anti-fuse memory circuit according to claim 1, characterized in that, The reading module includes: A comparator, including the first input terminal, the second input terminal and an output terminal; A latch device, including the sampling input terminal and a data input terminal, and the data input terminal is connected to the output terminal of the comparator; The comparator is used to compare the input voltage of the first input terminal with the reference voltage, and the latch device is used to output 1-bit data stored in the antifuse memory cell.

12. The anti-fuse memory circuit according to claim 1, characterized in that, The gate of the first switching transistor is connected to the word line, and one end of the source or the drain is connected to the antifuse memory cell, and the other end is connected to the bit line.

13. The anti-fuse memory circuit according to claim 12, wherein In the extending direction of the bit line, the bit lines are connected by the same conductive wire between every two adjacent first switching transistors.

14. The anti-fuse memory circuit according to claim 1, characterized in that, The gate of the second switching transistor is used to receive the column selection signal, one end of the source or the drain is connected to the bit line, and the other end is connected to the transmission wire. The column selection signal is used to select and conduct the bit line connected to the selected first switching transistor.

15. The anti-fuse memory circuit according to claim 1, wherein It further includes: A pre-charge MOS transistor, one end of the source or the drain is used to receive a pre-charge voltage, the other end is connected to the transmission wire, and the gate is used to receive a pre-charge signal. The pre-charge MOS transistor is used to pre-charge the transmission wire to the pre-charge voltage according to the pre-charge signal.

16. The anti-fuse memory circuit according to claim 15, wherein The pre-charge voltage is an internal power supply voltage.

17. The anti-fuse memory circuit according to claim 1, wherein It further includes: A voltage stabilizing capacitor, one side electrode plate is connected to the transmission wire, and the other side electrode plate is grounded, and is used to stabilize the voltage of the transmission wire.

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