Semiconductor device and method of manufacturing the same

Abstract

A three-dimensional (3D) memory device and a method of fabricating the same are provided. In some embodiments, the disclosed semiconductor device is a memory device and includes an array of memory cells in an array region, word lines extending in parallel in a first lateral direction, bit lines extending in parallel in a second lateral direction; and interconnect structures in the array region and coupled with the word lines, and arranged in staggered columns along the second lateral direction.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Planar memory cells have been shrunk to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become more difficult and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can overcome the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] One aspect of this disclosure provides a memory device comprising: an array of memory cells in an array region, word lines extending parallel to a first lateral direction, bit lines extending parallel to a second lateral direction; and an interconnect structure located in the array region and coupled to the word lines, and arranged in staggered columns along the second lateral direction.

[0005] In some implementations, a first distance between two word line interconnect structures coupled to two adjacent word lines is greater than a second distance between the two adjacent word lines.

[0006] In some implementations, the first column interconnect structure is located on a first side of the center of the array region; and the second column interconnect structure is located on a second side of the center location opposite to the first side.

[0007] In some implementations, a first column interconnect structure is located on a first side of a bit line; and a second column interconnect structure is located on a second side of the bit line opposite to the first side.

[0008] In some implementations, the third distance between the first column interconnect structure and the center location is equal to the fourth distance between the second column interconnect structure and the center location.

[0009] In some implementations, the third distance between the first column interconnect structure and the center location is different from the fourth distance between the second column interconnect structure and the center location.

[0010] In some implementations, the first column interconnect structure and the second column interconnect structure are located on the same side of the center of the array region.

[0011] In some embodiments, the memory device further includes a conductive layer connected to a first end of the interconnect structure, wherein a second end of the interconnect structure is connected to the word line.

[0012] In some embodiments, the interconnect structure includes multiple rows of interconnect structures aligned parallel to each other along the first lateral direction; and the interconnect structures in the same row are connected to the same word line.

[0013] In some embodiments, the memory device further includes: a first conductive layer connected to the interconnect structure of the odd-numbered rows; and a second conductive layer connected to the interconnect structure of the even-numbered rows.

[0014] In some embodiments, each of the memory cell arrays includes a vertical transistor and a memory cell coupled to the vertical transistor; and each word line includes a gate structure of a corresponding row of vertical transistors aligned along the first lateral direction.

[0015] In some implementations, in each vertical transistor, the gate structure is located on the lateral side of the channel structure of the vertical transistor.

[0016] In some implementations, in each vertical transistor, the gate structure is located on three lateral sides of the channel structure of the vertical transistor.

[0017] In some implementations, in each vertical transistor, the gate structure laterally surrounds the channel structure of the vertical transistor.

[0018] Another aspect of this disclosure provides a method of forming a memory device, comprising: forming bit lines extending parallel to a second lateral direction on a semiconductor layer; forming an array of vertical transistors, comprising: forming an array of vertical channel structures, each column of the vertical channel structures along the second lateral direction being coupled to a corresponding bit line of the bit lines; and forming gate structures on the lateral side of each row of the vertical channel structures along a first lateral direction, wherein the gate structures of each column of the array of vertical transistors form a word line along the first lateral direction; forming interconnect structures, each of the interconnect structures extending vertically through the semiconductor layer and contacting a corresponding word line; removing the semiconductor layer to expose a portion of the interconnect structure; and forming a conductive layer coupled to the interconnect structure.

[0019] In some embodiments, forming the interconnect structure includes forming multiple columns of interconnect structures that are parallel and aligned along the second lateral direction; and the interconnect structures of adjacent columns are arranged in an interleaved manner.

[0020] In some embodiments, forming the interconnect structure includes forming multiple rows of interconnect structures that are parallel and aligned along the first lateral direction; and the interconnect structures in the same row are connected to the same word line, and the interconnect structures in adjacent rows are arranged in an interleaved manner.

[0021] In some embodiments, forming the conductive layer includes: forming a first conductive layer connected to the interconnect structure in the odd-numbered rows; and forming a second conductive layer connected to the interconnect structure in the even-numbered rows.

[0022] In some embodiments, the method further includes forming an array of memory cells on the array of vertical transistors.

[0023] Another aspect of this disclosure provides a method of forming a memory device, comprising: forming an array of semiconductor pillars on a semiconductor layer; forming an insulating layer on the semiconductor layer to laterally isolate the semiconductor pillars; forming sacrificial structures, each sacrificial structure extending vertically through the insulating layer and into the semiconductor layer; forming conductive lines, each conductive line located on a lateral side of each row of the semiconductor pillars along a first lateral direction, wherein the conductive lines contact the sacrificial structures; removing the semiconductor layer to expose portions of the sacrificial structures; replacing the sacrificial structures with interconnect structures; and forming a conductive layer coupled to the interconnect structures.

[0024] In some embodiments, forming the sacrificial structure includes forming multiple columns of sacrificial structures that are parallel and aligned along a second transverse direction; and the sacrificial structures in adjacent columns are arranged in an alternating manner.

[0025] In some embodiments, forming the sacrificial structure includes forming multiple rows of sacrificial structures that are parallel and aligned along the first transverse direction; and the sacrificial structures in the same row are connected to the same conductive line, and the sacrificial structures in adjacent rows are arranged in an alternating manner.

[0026] In some embodiments, forming the conductive layer includes: forming a first conductive layer connected to the interconnect structure in the odd-numbered rows; and forming a second conductive layer connected to the interconnect structure in the even-numbered rows.

[0027] In some specific implementations, the method further includes: forming bit lines that extend parallel to the second lateral direction and are coupled to a second end of the array of semiconductor pillars; and forming an array of memory cells coupled to the second end of the array of semiconductor pillars.

[0028] In some embodiments, forming the conductive structure includes forming the conductive structure laterally around each channel structure in the row. Attached Figure Description

[0029] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0030] Figure 1 A schematic circuit diagram of a memory device comprising an array of memory cells, each having a vertical transistor, according to some embodiments of the present disclosure is shown.

[0031] Figure 2A A schematic plan view of a memory device according to some embodiments of the present disclosure is shown.

[0032] Figure 2B A schematic plan view of a memory device according to some embodiments of the present disclosure is shown.

[0033] Figure 3A A schematic plan view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 3B A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0035] Figure 3C A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0036] Figure 4A A schematic plan view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0037] Figure 4B A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0038] Figure 4C A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0039] Figure 5A A schematic plan view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0040] Figure 5B A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0041] Figure 5C A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0042] Figure 6AA schematic plan view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0043] Figure 6B A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0044] Figure 6C A schematic side cross-sectional view of a portion of a memory device according to some embodiments of the present disclosure is shown.

[0045] Figure 7 A block diagram of a system having a memory device according to some embodiments of the present disclosure is shown.

[0046] Figure 8 A flowchart is shown of a manufacturing method for forming a 3D memory device according to some embodiments of the present disclosure.

[0047] Figures 9A-9E All of these illustrate 3D memory devices according to various embodiments of the present disclosure. Figure 8 A schematic side cross-sectional view of a certain manufacturing stage of the method shown.

[0048] Figure 10 A flowchart is shown of a manufacturing method for forming a 3D memory device according to some embodiments of the present disclosure.

[0049] Figure 11A-11B 12A-12B, 13, and 14 all illustrate 3D memory devices according to various embodiments of the present disclosure. Figure 10 A schematic side cross-sectional view of a certain manufacturing stage of the method shown.

[0050] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0051] Although specific configurations and arrangements have been discussed, it should be understood that they are for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically shown in the accompanying drawings, and such combinations, adjustments, and modifications are therefore within the scope of this disclosure.

[0052] Generally, terms can be understood at least partly by their use in context. For example, the term "one or more" can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood, at least partly depending on the context, to convey either singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors; rather, it may allow for additional factors that are not explicitly described, again at least partly depending on the context.

[0053] It should be readily understood that the meanings of “on”, “above”, and “on top” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with an intervening feature or layer between them, and that “above” or “on top” means not only “above” or “on top” something but can also include something without an intervening feature or layer between them (i.e., directly on something).

[0054] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to cover different orientations during the use or operation of the device other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted similarly accordingly.

[0055] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0056] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure whose thickness is less than the thickness of that continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0057] Transistors are used as switches or selection devices in memory cells of some memory devices, such as Dynamic Random Access Memory (DRAM). In a transistor-capacitor (1T1C) DRAM structure, data is stored in a capacitor. In traditional DRAM architectures, word lines (WLs) are typically buried on one or more sides of the transistor channel structure, resulting in significant WL-WL parasitic capacitance. Furthermore, WL wiring interconnects that contact word lines are typically located on opposite sides of the array. Back-of-line (BEOL) wiring also contributes significantly to parasitic capacitance. To meet sensing margin requirements, capacitors need to be very large, posing a significant challenge in terms of process technology, and further miniaturization becomes increasingly difficult as DRAM scaling advances.

[0058] To address one or more of the aforementioned problems, this disclosure presents a solution employing a pre-buried word line (WL) method. Specifically, in some embodiments, periodic metal vias can be embedded during the front-end online (FEOL) process. In other embodiments, periodic sacrificial vias can be embedded during the FEOL process and then replaced with metal in subsequent processes. In the BEOL process, metal vias can be alternately laid outward through metal lines to adjacent word lines. In some embodiments, two or more metal lines can be used to form the word line interconnect structure to further reduce parasitic capacitance. By completing the vias in the FEOL process, the overlay (OVL) problem in the BEOL process can be avoided, thereby enabling interconnect pickup with a grid-like word line layout. The disclosed solution significantly reduces WL-WL parasitic capacitance, thereby reducing capacitor requirements, simplifying capacitor manufacturing, and paving the way for further miniaturization as DRAM continues to scale.

[0059] According to the scope of this disclosure, and in some embodiments thereof, a memory cell array has vertical transistors, each vertical transistor including a semiconductor layer extending in a vertical direction, and a gate structure adjacent to or surrounded by the semiconductor layer. In some embodiments, word lines and bit lines connected to the vertical transistors are arranged along a first lateral direction and a second lateral direction, respectively. Each of the semiconductor bodies of the vertical transistor array extends in a vertical direction. By using such an arrangement, the area efficiency of the memory can be increased. Furthermore, the memory cell array and peripheral circuitry can be formed independently on different wafers, so that the manufacturing processes of the memory cell array and peripheral circuitry do not interfere with each other, and the area efficiency of the memory can be further increased.

[0060] Figure 1 A schematic diagram of a memory device 100 comprising an array of memory cells, each having a vertical transistor, according to some embodiments of the present disclosure is shown. The memory device 100 may include an array of memory cells, wherein each memory cell 110 includes a vertical transistor 120 and a memory cell coupled to the vertical transistor 120. Figure 1 In some embodiments shown, the memory cell array is a DRAM cell array, and the storage cell is a capacitor 130 used to store charge as binary information stored by the respective DRAM cell. In some other embodiments not shown in the figures, the memory cell array is a PCM cell array, and the storage cell can be a PCM element (e.g., including chalcogenide alloys) used to store the binary information of the respective PCM cell based on the different resistivities of the PCM elements in the amorphous phase and the crystalline phase.

[0061] like Figure 1 As shown, memory cells 110 can be arranged as a two-dimensional (2D) array with rows and columns. Memory device 100 may include word lines 150 that couple the memory cell array to peripheral circuitry to control the switching of vertical transistors 120 in the memory cells 110 located in a row, and bit lines 160 that couple the memory cell array to peripheral circuitry to send data to and / or receive data from the memory cells 110 located in a column. That is, each word line 150 is coupled to a memory cell 110 in a corresponding row, and each bit line 160 is coupled to one or more memory cells 110 in a corresponding logical column. In some embodiments, the gate of a vertical transistor 120 is coupled to word line 150, one of the source and drain of a vertical transistor 120 is coupled to bit line 160, and the other of the source and drain of a vertical transistor 120 is coupled to one electrode of a capacitor 130, the other electrode of which is coupled to ground.

[0062] Within the scope of this disclosure, a vertical transistor 120, such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a conventional planar transistor as a pass transistor for memory cell 110 to reduce the area occupied by the pass transistor, coupling capacitance, and interconnect wiring complexity, as described in more detail below.

[0063] Figure 2A A schematic plan view in the xy plane is shown of a memory device 200A including multiple memory arrays 211 according to some embodiments of the present disclosure. Each memory array 211 may include an array of memory cells, each memory cell including a vertical transistor and a vertical capacitor. According to some embodiments of the present disclosure, the vertical transistor may have any suitable component arrangement, such as a channel full-around (CAA) type vertical transistor, a gate full-around type vertical transistor, a single metal gate (SMG) type vertical transistor, a dual metal gate (DMG) type vertical transistor, a triple metal gate (TMG) type vertical transistor, etc.

[0064] like Figure 2A As shown, each memory array 211 may include multiple word lines 250, each word line extending along a first lateral direction (x-direction, referred to as the word line direction). It should be noted that each memory array 211 may also include multiple bit lines (not shown), each bit line extending along a second lateral direction perpendicular to the first lateral direction (y-direction, referred to as the bit line direction). For ease of routing, word lines 250 and bit lines may be formed in different lateral planes. In some embodiments, the memory device 200A may also include multiple word line interconnect structures 210 located on both sides of each memory array 211 along the word line direction (x-direction). Word lines 250 may be interconnected to word line interconnect structures 210 in an interleaved manner on both sides of each memory array 211 along the word line direction (x-direction). For example, a first set of word line interconnect structures 210 located on a first side of each memory array 211 may be connected to odd-numbered word lines 250, and a second set of word line interconnect structures 210 located on a second side of each memory array 211 may be connected to even-numbered word lines 250.

[0065] Such a layout may require a large space between adjacent memory arrays 211 to accommodate word line interconnect structures 210. For example, the area between adjacent memory arrays 211 used to accommodate word line interconnect structures 210 may occupy approximately 4.6% of the total area of ​​the memory device, making it difficult to reduce the size of the memory device 211, as this proportion increases when the size of the memory array 211 is reduced. Furthermore, since the word lines 250 are driven via word line interconnect structures 210 at both ends, the lead resistance of the word lines 250 may be high, resulting in significant RC delay. In addition, the routing of the word line drive lines contributes significantly to parasitic capacitance due to their driving at both ends.

[0066] Figure 2B A schematic plan view in the xy plane is shown of a memory device 200B including multiple memory arrays 211 according to some embodiments of the present disclosure. Each memory array 211 may include an array of memory cells, and each memory cell includes a vertical transistor and a vertical capacitor. According to some embodiments of the present disclosure, the vertical transistor may have any suitable component arrangement, such as a channel full-around (CAA) type vertical transistor, a gate full-around type vertical transistor, a single metal gate (SMG) type vertical transistor, a dual metal gate (DMG) type vertical transistor, a triple metal gate (TMG) type vertical transistor, etc.

[0067] like Figure 2B As shown, each memory array 211 may include multiple word lines 250, each extending along a first lateral direction (x-direction). It should be noted that each memory array 211 may also include multiple bit lines (not shown), each extending along a second lateral direction (y-direction). For ease of routing, word lines 250 and bit lines may be formed in different lateral planes. In some embodiments, the memory device 200B may also include multiple word line interconnect structures 290 located within the array region and coupled to the word lines 250, and arranged in staggered columns along the second lateral direction (y-direction). Word lines 250 may be interconnected to corresponding word line interconnect structures 290 in an interleaved manner. For example, a first column of word line interconnect structures 290 aligned along the second lateral direction may be connected to odd-numbered word lines 250, while a second column of word line interconnect structures 290 aligned along the second lateral direction may be connected to even-numbered word lines 250, such as... Figure 2B As shown.

[0068] This layout eliminates the need for a large space between adjacent memory arrays 211 to accommodate the word line interconnect structure 290. For example, the region located between adjacent memory arrays 211 along the first lateral direction may occupy approximately 0.25% or less of the total area of ​​the memory device, making it easier to reduce the size of the memory arrays 211 to minimize capacitance. Furthermore, since the word lines 250 are driven from the center of the memory arrays 211 via the word line interconnect structure 290, the wiring resistance of the word lines 250 may be lower, resulting in reduced RC delay.

[0069] Figure 3A A schematic plan view of a memory array 300A according to some embodiments of the present disclosure is shown in the xy plane. Figure 3AAs shown, multiple word lines 350 extend parallel to each other along a first lateral direction (x-direction), and multiple bit lines 360 extend parallel to each other along a second lateral direction (y-direction). For ease of routing, word lines 350 and bit lines 360 can be formed in different lateral planes. In some embodiments, the memory array 300A also includes multiple word line interconnect structures 390 located within the array region and coupled to the word lines 350, and arranged in staggered columns along the second lateral direction (y-direction). The word lines 350 can be interconnected to the corresponding word line interconnect structures 390 in an interleaved manner.

[0070] In some implementations, the distance D1 between two word line interconnect structures 390 coupled to two adjacent word lines 350 is greater than a second distance D2 between the two adjacent word lines 350, such as... Figure 3A As shown in the diagram. In some embodiments, the first column word line interconnection structure 390 aligned along the second lateral direction can be connected to even-numbered word lines 350, while the second column word line interconnection structure 390 aligned along the second lateral direction can be connected to odd-numbered word lines 350.

[0071] like Figure 3A As shown, the first column word line interconnect structure 390 may be located on a first side of the center line 310 of the array region of the memory array 300A, and the second column word line interconnect structure 390 may be located on a second side of the center line 310 of the array region of the memory array 300A opposite to the first side. In some embodiments, the third distance D3 between the first column word line interconnect structure 390 and the center line 310 is equal to the fourth distance D4 between the second column word line interconnect structure 390 and the center line 310. In some other embodiments, the third distance D3 between the first column word line interconnect structure 390 and the center line 310 is different from the fourth distance D4 between the second column word line interconnect structure 390 and the center line 310. In some other embodiments not shown in the figures, the first column word line interconnect structure 390 and the second column word line interconnect structure 390 may be located on the same side of the center line 310 of the array region of the memory array 300A. Figure 3A In some embodiments shown, the first column word line interconnect structure 390 may be located on a first side of a bit line 360, and the second column word line interconnect structure 390 may be located on a second side of the bit line 360 ​​opposite to the first side.

[0072] Figure 3B A memory array 300A according to some embodiments of the present disclosure is shown. Figure 3A The schematic lateral section of line AA' in the xz plane is shown in Figure 300B. Figure 3C A memory array 300A according to some embodiments of the present disclosure is shown. Figure 3AThe schematic lateral section of the BB' line in the yz plane is shown in Figure 300C.

[0073] like Figure 3B As shown, transistor layer 320 includes a plurality of vertical transistors 324, each vertical transistor having a vertical semiconductor body 328 and a gate electrode 350 (also referred to as a word line 350) located on one or more lateral sides of the vertical semiconductor body 328. The vertical semiconductor body 328 may comprise any suitable semiconductor material, such as polysilicon. The vertical semiconductor body 328 may have a leakage value below picoamperes. In some embodiments, the leakage value of the vertical semiconductor body 328 is lower than the intrinsic leakage value of monocrystalline silicon. In some embodiments, the material of the vertical semiconductor body 328 may be a metal-oxide-semiconductor material, such as IGZO. In some embodiments, bit line 360 ​​contacts the lower end of semiconductor body 328. In some embodiments, word line interconnect structure 390 may extend through bit line 360 ​​and into semiconductor body 328 of transistor layer 320.

[0074] In some embodiments, the gate electrode 350 may comprise any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, the gate electrode 350 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 350 comprises multiple conductive layers, such as a W layer over a TiN layer. In some embodiments, the gate dielectric layer 370 may be located between the vertical semiconductor body 328 and the gate electrode 350. The gate dielectric layer 370 may comprise any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In various embodiments, the gate electrode 350 may be located on one or more lateral sides of the vertical semiconductor body 328 to form a CAA-type, SMG-type, DMG-type, or TMG-type vertical transistor 324. In some implementations, the gate electrodes 350 of a row of vertical transistors 324 along a first lateral direction (x direction) can be connected to each other to form word lines 350.

[0075] like Figure 3B and 3CAs shown, in some embodiments, the word line interconnect structure 390 may extend into and / or through the word line 350 to increase the contact area and achieve better contact conductivity. The word line interconnect structure 390 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. In some embodiments, the word line interconnect structure 390 may include multiple conductive layers, such as a W layer above a TiN layer. In some embodiments, a conductive layer 380 (e.g., a BEOL metal layer) may be connected to the lower end of the word line interconnect structure 390.

[0076] like Figure 3C As shown, a column of word line interconnect structures 390 along the second lateral direction (y-direction) can be alternately connected between corresponding even / odd numbered word lines 350 and conductive layer 380. In some embodiments, the fifth distance D5 between adjacent word line interconnect structures 390 in the same column is in the range of approximately 60 nm to approximately 120 nm, for example, approximately 90 nm. Such a spacing can meet the overlay requirements of wiring in the BEOL metal layer 380.

[0077] In some embodiments, adjacent word lines 350 may be separated from each other by a spacer layer 335, the spacer layer comprising any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, and / or having one or more air gaps (not shown). The one or more air gaps may be formed due to the smaller spacing between adjacent word lines 350. Furthermore, the larger dielectric constant of the air in the air gaps (e.g., approximately four times the dielectric constant of silicon oxide) can improve the insulation effect between adjacent word lines 350. In some embodiments, the spacer layer 335 is part of an insulating layer 330 covering the vertical transistor 324, word lines 350, bit lines 360, and word line interconnect structure 390. The word line interconnect structure 390 extends vertically through the insulating layer 330 to connect the bit lines 360 to the conductive layer 380.

[0078] In some embodiments, but not shown in the figures, each memory cell of the memory array 300A in the disclosed memory device may further include a memory cell coupled to a vertical transistor 324. The memory cell may include any means capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor controls the selection and / or state switching of a corresponding memory cell coupled to the vertical transistor 324. In some embodiments, the memory cell includes a capacitor. It is to be understood that the capacitor may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a pillar capacitor, a trench capacitor, or a substrate-plate capacitor.

[0079] In some embodiments, one or more peripheral circuits (not shown) may be coupled to the memory cell array 300A via word lines 350, bit lines 360, and any other suitable metal lines. It should be noted that the one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the memory cell array 300A by applying and sensing voltage and / or current signals traveling to and from each vertical transistor 324 via word lines 350 and bit lines 360. The one or more peripheral circuits may include various types of peripheral circuits formed using CMOS technology.

[0080] Figure 4A A schematic plan view of a memory array 400A according to some embodiments of the present disclosure is shown in the xy plane. Figure 4A As shown, multiple word lines 450 extend parallel to each other along a first lateral direction (x-direction), and multiple bit lines (not shown) extend parallel to each other along a second lateral direction (y-direction). For ease of routing, word lines 450 and bit lines can be formed in different lateral planes. In some embodiments, the memory array 400A also includes multiple word line interconnect structures 490, which are located within the array region and coupled to the word lines 450, and arranged in staggered columns along the second lateral direction (y-direction).

[0081] exist Figure 4AIn some embodiments shown, the multiple word line interconnect structures 490 can be arranged in a network configuration for each memory cell array 411. That is, the multiple word line interconnect structures 490 can include rows of multiple word line interconnect structures 490 aligned parallel to each other along a first lateral direction, and columns of multiple word line interconnect structures 490 aligned parallel to each other along a second lateral direction. In some embodiments, word line interconnect structures 490 in the same row are connected to the same word line 450. Additionally, columns of word line interconnect structures 490 can be interconnected to corresponding word line interconnect structures 490 in an interleaved manner. For example, odd-numbered columns of word line interconnect structures 490 are connected to odd-numbered word lines 450, while even-numbered columns are connected to odd-numbered word lines 450. By arranging more than one word line interconnect structure 490 for a single word line 450, the network word line interconnect structures 490 can achieve more robust word line interconnects and faster word line driving.

[0082] Figure 4B A schematic lateral cross-sectional view 400B of a memory array 400A along line AA' in the xz plane is shown according to some embodiments of the present disclosure. Figure 4C A schematic lateral cross-sectional view 400C of a memory array 400A according to some embodiments of the present disclosure is shown along line BB' in the xz plane. It should be noted that... Figure 4B The cross-sectional view 400B shown intersects with the odd-numbered word line 450, while Figure 4C The cross-sectional view 400C shown intersects with the even-numbered word line 450.

[0083] like Figure 4B and 4C As shown, a row of word line interconnect structures 490 along the first lateral direction (x-direction) can be connected to the same corresponding even / odd number line 450. In the first lateral direction (x-direction), each word line interconnect structure 490 can be located between adjacent vertical transistors 424. As described above, the vertical transistors 424 can be CAA, SMG, DMG, or TMG type vertical transistors. In the vertical direction (z-direction), each word line interconnect structure 490 can extend through a bit line 460 and a transistor layer 420 including the vertical transistors 424 and contact the word line 450. The lower end of each word line interconnect structure 490 can contact a conductive layer 480, such as a BEOL metal layer.

[0084] In some embodiments, odd-numbered word lines 450 and even-numbered word lines 450 may be coupled to the same single metal layer including a word line driving network. In such embodiments, the single metal layer may be formed using a self-aligned double patterning (SADP) process. In some other embodiments that do not use the SADP process, odd-numbered word lines 450 and even-numbered word lines 450 may be coupled to different metal layers including a word line driving network. For example, as... Figure 4B The word line interconnect structure 490, coupled to the odd-numbered word line 450, can be driven by the first conductive layer 441, and as shown... Figure 4C The word line interconnect structure 490, which is coupled to the even-numbered word line 450, can be driven by the second conductive layer 443.

[0085] In some embodiments, but not shown in the figures, each memory cell of the memory cell array 411 in the disclosed memory device may further include a memory cell coupled to a vertical transistor 424. The memory cell may include any means capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor controls the selection and / or state switching of a corresponding memory cell coupled to the vertical transistor 424. In some embodiments, the memory cell includes a capacitor. It is to be understood that the capacitor may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a pillar capacitor, a trench capacitor, or a substrate-plate capacitor.

[0086] In some implementations, one or more peripheral circuits (not shown) may be coupled to the memory cell array 411 via word lines 450, bit lines 460, and any other suitable metal lines. It should be noted that the one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the memory cell array 411 by applying and sensing voltage and / or current signals traveling to and from each vertical transistor 424 via word lines 450 and bit lines 460. The one or more peripheral circuits may include various types of peripheral circuits formed using CMOS technology.

[0087] Figure 5A A schematic plan view of a memory array 500A according to some embodiments of the present disclosure is shown in the xy plane. In some embodiments, the memory array 500A includes an array of single metal gate (SMG) type vertical transistors 524. Figure 5B A memory array 500A according to some embodiments of the present disclosure is shown. Figure 5A The schematic lateral section of line AA' in the xz plane is shown in Figure 500B. Figure 5CA memory array 500A according to some embodiments of the present disclosure is shown. Figure 5A The schematic lateral section of the BB' line in the yz plane is shown in Figure 500C.

[0088] like Figure 5A As shown, multiple word lines 550 extend parallel to each other along a first lateral direction (x-direction). Each word line 550 includes multiple gate electrodes 550 of a corresponding row of vertical transistors 524 aligned along the first lateral direction. The gate electrodes 550 are located on one side of the vertical semiconductor body 528 and are separated from the vertical semiconductor body 528 by a gate dielectric 570. Every two rows of vertical transistors 524 are laterally separated by a spacer layer 585. In some embodiments, the spacer layer 585 may include a suitable insulating material, such as a thin insulating spacer oxide (TISO) material.

[0089] In some embodiments, the memory array 500A further includes a plurality of word line interconnect structures 590, which are located within the array region and contact word lines 550, and are arranged in staggered columns along a second lateral direction (y-direction). Word lines 550 may be interconnected to corresponding word line interconnect structures 590 in an interleaved manner. Figure 5A In some embodiments shown, the word line interconnect structure 590 and the vertical semiconductor body 528 are located on the same side of adjacent word lines 550. That is, the word line interconnect structure 590 is located between the word line 550 and the spacer layer 585 along the second lateral direction (y direction), and between the two vertical semiconductor bodies 528 of two adjacent vertical transistors 524 along the first lateral direction (x direction).

[0090] like Figure 5B As shown, in the xz plane of section, the word line interconnect structure 590 extends through the insulating layer 530 and is located between the vertical semiconductor bodies 528 of two adjacent vertical transistors 524. The lower end of the word line interconnect structure 590 contacts the conductive layer 580 (e.g., a BEOL metal layer). Figure 5C As shown, in the cross-sectional yz plane, the word line interconnect structure 590 contacts one side of the word line 550 and is located between the word line 550 and its adjacent spacer layer 585.

[0091] Figure 6A A schematic plan view of a memory array 600A according to some embodiments of the present disclosure is shown in the xy plane. In some embodiments, the memory array 600A includes an array of tri-gate (TMG) type vertical transistors 624. Figure 6B A memory array 600A according to some embodiments of the present disclosure is shown. Figure 6A The schematic lateral section of line AA' in the xz plane is shown in Figure 600B. Figure 6CA memory array 600A according to some embodiments of the present disclosure is shown. Figure 6A The schematic lateral section of the BB' line in the yz plane is shown in Figure 600C.

[0092] like Figure 6A As shown, multiple word lines 650 extend along a first lateral direction (x-direction). Each word line 650 includes multiple gate electrodes 650 of a corresponding row of vertical transistors 624 aligned along the first lateral direction. The gate electrodes 650 are located on three sides of the vertical semiconductor body 628 and are separated from the vertical semiconductor body 628 by a gate dielectric 670. Every two rows of vertical transistors 624 are laterally separated by a spacer layer 685. In some embodiments, the spacer layer 685 may include a suitable insulating material, such as a thin insulating spacer oxide (TISO) material.

[0093] In some embodiments, the memory array 600A further includes a plurality of word line interconnect structures 690, which are located within the array region and contact word lines 650, and are arranged in staggered columns along a second lateral direction (y-direction). Word lines 650 may be interconnected to corresponding word line interconnect structures 690 in an interleaved manner. Figure 6A In some embodiments shown, word lines 650 partially surround word line interconnect structures 690. That is, word line interconnect structures 690 contact three sides of word lines 650. Furthermore, word line interconnect structures 690 and vertical semiconductor bodies 628 are located on the same side of adjacent word lines 650. Specifically, word line interconnect structures 690 are located between word lines 650 and spacer layers 685 along a second lateral direction (y-direction), and between the two vertical semiconductor bodies 628 of two adjacent vertical transistors 624 along a first lateral direction (x-direction).

[0094] like Figure 6B As shown, in the xz plane of section, the word line interconnect structure 690 extends through the insulating layer 630, contacts both sides of the word line 650, and is located between the vertical semiconductor bodies 628 of two adjacent vertical transistors 624. The lower end of the word line interconnect structure 690 contacts the conductive layer 680 (e.g., a BEOL metal layer). Figure 6C As shown, in the cross-sectional yz plane, the word line interconnect structure 690 contacts the third side of 650 and is located between the word line 650 and its adjacent spacer layer 685.

[0095] Figure 7A block diagram of a system 700 having a memory device according to some embodiments of the present disclosure is shown. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device having a storage component located therein. Figure 7 As shown, system 700 may include host 708 and memory system 702, memory system 702 having one or more memory devices 704 and memory controller 706. Host 708 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 708 may be configured to send or receive data to or from memory device 704. Memory device 704 may be any memory device disclosed herein, such as memory device 100. In some embodiments, memory device 704 includes one or more arrays of memory cells shown in 200A / 200B / 300A / 400A / 500A / 600A, as detailed above.

[0096] According to some embodiments, a memory controller 706 is coupled to a memory device 704 and a host 708 and is configured to control the memory device 704. The memory controller 706 can manage data stored in the memory device 704 and communicate with the host 708. The memory controller 706 can be configured to control operations of the memory device 704, such as read, write, and refresh operations. The memory controller 706 can also be configured to manage various functions related to data stored in or to be stored in the memory device 704, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 706 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, the memory type and speed, the memory particle data depth and data width, and other important parameters. Any other appropriate functions can also be performed by the memory controller 706. The memory controller 706 can communicate with external devices (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0097] Figure 8 A flowchart is shown of a manufacturing method 800 for forming a 3D memory device according to some embodiments of the present disclosure. Figures 9A-9E The 3D memory device according to various embodiments of the present disclosure is shown. Figure 8 The diagram shows a schematic side cross-sectional view of certain manufacturing stages of method 800. It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. Furthermore, operations may be performed simultaneously or with... Figure 8 The diagram shows some of the different orders in which the operations are performed.

[0098] like Figure 8 As shown, method 800 can begin with operation 810, in which multiple bit lines can be formed. Figure 9A A schematic side cross-sectional view of the 3D memory device in the xz plane is shown after operation 810 of method 800.

[0099] like Figure 9A As shown, multiple bit lines 915 can be formed on substrate 910. In some embodiments, substrate 910 can be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In such embodiments, the multiple bit lines 915 can be formed by a patterning process (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc., to remove portions of substrate 910 to form parallel trenches all extending in the second lateral direction (y-direction). The trenches can then be filled using a deposition process with any suitable insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to form spacers 917. The protruding portions of substrate 910 laterally separated by spacers 917 can form multiple bit lines 915 arranged parallel to each other in the first lateral direction (x-direction), each bit line extending in the second lateral direction (y-direction).

[0100] Re-reference Figure 8 Method 800 can proceed to operation 820, in which an array of memory cells can be formed on the bit lines. Figure 8 B shows a schematic side cross-sectional view of the 3D memory device in the xz plane after operation 820 of method 800.

[0101] like Figure 9BAs shown, the array forming the memory cells may include a transistor layer 930 forming an array of vertical transistors 932. Forming the transistor layer 930 may include forming a plurality of vertical semiconductor pillars 933, all passing through an insulating layer 939. Each column of vertical semiconductor pillars 933 along a second lateral direction (y-direction) may be in contact with a corresponding bit line 915. In some embodiments, the vertical semiconductor pillars 933 may include any suitable semiconductor material, such as polysilicon. The vertical semiconductor pillars 933 may have a leakage value below picoamperes. In some embodiments, the leakage value of the vertical semiconductor pillars 933 is lower than the intrinsic leakage value of monocrystalline silicon. In some embodiments, the material of the vertical semiconductor pillars 933 may be a metal-oxide-semiconductor material, such as IGZO.

[0102] like Figure 9B As shown, forming the transistor layer 930 may further include forming a gate electrode 935 on one or more lateral sides of the vertical semiconductor pillar 933, and forming a gate dielectric layer 937 between the gate electrode 935 and the vertical semiconductor pillar 933. In some embodiments, the gate electrodes 935 of each row of vertical transistors 932 along the first lateral direction (x-direction) may be connected to each other to form a word line 935. The gate electrode 935 may include any suitable conductive material, such as polysilicon, metal (e.g., W, Cu, Al, etc.), metal compound (e.g., TiN, TaN, etc.), or silicide. For example, the gate electrode 935 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 935 includes multiple conductive layers, such as a W layer above a TiN layer. The gate dielectric layer 937 may include any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 937 may include silicon oxide, i.e., gate oxide. In some embodiments, the gate electrode 935 and the gate dielectric layer 937 can be formed by a series of manufacturing processes, including thin film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.).

[0103] although Figure 9BNot shown, but the array forming the memory cells may further include a memory cell layer forming the memory cell array, each memory cell being coupled to a corresponding one of the vertical transistor 932 array. In some embodiments, the array of memory cells may be an array of capacitors, each capacitor including a common second electrode, a plurality of first electrodes, and a capacitor dielectric layer between the first electrodes and the common second electrode. In some embodiments, the first electrode and / or the common second electrode may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the capacitor dielectric layer includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the array of capacitors may be formed by a series of manufacturing processes, including thin film deposition processes (e.g., CVD, PVD, ALD, etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, CMP, etc.).

[0104] Re-reference Figure 8 Method 800 can proceed to operation 830, in which word line interconnection structure can be formed. Figure 9C A schematic side cross-sectional view of the 3D memory device in the xz plane is shown at a specific stage of operation 830 of method 800.

[0105] like Figure 9C As shown, a plurality of word line interconnect structures 920 can be formed to pass through the transistor layer 930 and the spacer 917 and extend into the substrate 910. In some embodiments, the plurality of word line interconnect structures 920 can be formed by removing portions of the word lines 935 and the substrate 910 to form openings, each opening extending vertically through the word lines 935 and the spacer 917 and into the substrate 910, and filling the openings with a conductive material. In some embodiments, the plurality of word line interconnect structures 920 can be formed in an array region and arranged in staggered columns along a second lateral direction (y-direction). In some embodiments, a first column of word line interconnect structures 920 aligned along the second lateral direction can be connected to odd-numbered word lines 935, while a second column of word line interconnect structures 920 aligned along the second lateral direction can be connected to even-numbered word lines 935. In some embodiments, the word line interconnect structures 920 can include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. In some implementations, the word line interconnect structure 920 may include multiple conductive layers, such as a W layer above a TiN layer.

[0106] In some other embodiments, forming the word line interconnect structure 920 may include forming a plurality of sacrificial interconnects and then replacing the plurality of sacrificial interconnects with the conductive word line interconnect structure 920. For example, the plurality of sacrificial interconnects (not shown) may be formed by removing portions of the word line 935, insulating layer 939, spacer 917, and substrate 910 to form openings, each opening extending vertically through the word line 935 into the substrate 910, and filling the openings with sacrificial material. The sacrificial material may be replaced from the back side of the substrate 910 in a subsequent process.

[0107] Re-reference Figure 8 Method 800 can proceed to operation 840, in which a conductive layer can be formed to couple with the word line interconnect structure. Figure 9D and 9E Both show schematic side cross-sectional views of the 3D memory device in the xz plane at a specific stage of operation 840 of method 800.

[0108] In some implementations, it can be flipped. Figure 9C The 3D structure shown is illustrated. A portion of the substrate 910 can be removed using any suitable process, such as dry etching, wet etching, CMP, etc., to expose the word line interconnect structure 920. (As shown...) Figure 9D As shown, portions of the substrate 910 can be further removed by any suitable process, such as dry etching, wet etching, CMP, etc., to expose portions of the spacer 917 and bit line 915. Figure 9E As shown, an insulating layer 945 may be formed to cover the exposed surface of the bit line 915. In some embodiments, the insulating layer 945 may comprise any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. A conductive layer 980 may be formed in the insulating layer 945 and contact the word line interconnect structure 920. In some embodiments, the conductive layer 980 may comprise one or more BEOL metal layers and may be formed by a range of fabrication processes, including thin film deposition processes (e.g., CVD, PVD, ALD, etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, CMP, etc.).

[0109] Figure 10 A flowchart is shown of a manufacturing method 1000 for forming a 3D memory device according to some embodiments of the present disclosure. Figure 11A-11B 12A-12B, 13 and 14 illustrate 3D memory devices according to various embodiments of the present disclosure. Figure 10The diagram shows a schematic side cross-sectional view of certain manufacturing stages of method 1000. It should be understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. Furthermore, operations may be performed simultaneously or with... Figure 10 Some of the different sequences of operations are shown.

[0110] like Figure 10 As shown, method 1000 can begin with operation 1010, in which a plurality of vertical semiconductor pillars and spacers can be formed. Figure 11A A schematic side cross-sectional view of the 3D memory device in the yz plane is shown after operation 1010 of method 1000. Figure 11B A schematic side cross-sectional view of the 3D memory device in the xz plane is shown after operation 1010 of method 1000.

[0111] like Figure 11A and 11B As shown, a plurality of vertical semiconductor pillars 1133 can be formed on substrate 1110. In some embodiments, the vertical semiconductor pillars 1133 can be arranged in an array in a lateral plane. In some embodiments, substrate 1110 can be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, a plurality of spacers 1185 can be arranged in parallel, each spacer extending in a first lateral direction (x-direction).

[0112] In this embodiment, a plurality of vertical semiconductor pillars 1133 and spacers 1185 can be formed by patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc., to remove portions of the substrate 1110 to form trenches extending in both a first lateral direction (x-direction) and a second lateral direction (y-direction). An insulating layer 1120 can be formed to fill the trenches. Further removal of protruding portions of the substrate 1110 and filling with a thin insulating spacer oxide (TISO) material can be used to form spacers 1185. The remaining portion of the substrate 1110, laterally separated by the insulating layer 1120 and spacers 1185, can form the plurality of vertical semiconductor pillars 1133.

[0113] like Figure 10 As shown, method 1000 can proceed to operation 1020, in which word line interconnection structures can be formed. Figure 12A A schematic side cross-sectional view of the 3D memory device in the yz plane is shown after operation 1020 of method 1000. Figure 12BA schematic side cross-sectional view of the 3D memory device in the xz plane is shown after operation 1020 of method 1000.

[0114] like Figure 12A and 12B As shown, multiple word line interconnect structures 1220 can be formed to penetrate the insulating layer 1120 and extend into the substrate 1110. In some embodiments, the multiple word line interconnect structures 1220 can be formed by removing portions of the insulating layer 1120 and the substrate 1110 to form openings, each opening extending vertically through the insulating layer 1120 and into the substrate 1110, and filling the openings with a conductive material. In some embodiments, the multiple word line interconnect structures 1220 can be formed in an array region and arranged in staggered columns along a second lateral direction (y-direction). In some embodiments, the word line interconnect structure 920 can include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. In some embodiments, the word line interconnect structure 920 can include multiple conductive layers, such as a W layer above a TiN layer.

[0115] In some other embodiments, forming the word line interconnect structure 1220 may include forming a plurality of sacrificial interconnects and then replacing the plurality of sacrificial interconnects with the conductive word line interconnect structure 1220. For example, the plurality of sacrificial interconnects (not shown) may be formed by removing portions of the insulating layer 1120 and the substrate 1110 to form openings, each opening extending vertically through the insulating layer 1120 into the substrate 1110, and filling the openings with a sacrificial material. The sacrificial material may be replaced from the back side of the substrate 1110 in a subsequent process.

[0116] Re-reference Figure 10 Method 1000 can proceed to operation 1030, in which multiple word lines can be formed to be coupled to the word line interconnection structure. Figure 13 A schematic side cross-sectional view of the 3D memory device in the yz plane is shown after operation 1030 of method 1000.

[0117] like Figure 13As shown, multiple word lines 1350 can be formed in contact with the word line interconnect structure 1220. In some embodiments, each word line 1350 can be formed on one or more lateral sides of a row of vertical semiconductor pillars 1133. In some embodiments, the word lines 1350 can include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. For example, the word lines 1350 can include doped polysilicon, i.e., gate polysilicon. In some embodiments, the word lines 1350 include multiple conductive layers, such as a W layer above a TiN layer. In some embodiments, the word lines 1350 can be formed by a series of fabrication processes, including thin film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.). In some embodiments, odd-numbered word lines 1350 may be formed to contact the first column word line interconnect structure 1220 aligned along the second lateral direction, while even-numbered word lines 1350 may be formed to contact the second column word line interconnect structure 920 aligned along the second lateral direction.

[0118] Re-reference Figure 10 Method 1000 can proceed to operation 1040, in which a conductive layer can be formed to couple with the word line interconnect structure. Figure 14 A schematic side cross-sectional view of the 3D memory device in the xz plane is shown after operation 1040 of method 1000.

[0119] In some implementations, it can be flipped. Figure 13 The 3D structure shown can be partially removed from the substrate 1110 using any suitable process, such as dry etching, wet etching, CMP, etc., to expose the word line interconnect structure 1220. Figure 9E As shown, conductive layer 1480 may be formed in insulating layer 1120 and contact word line interconnect structure 1220. In some embodiments, conductive layer 1480 may include one or more BEOL metal layers and may be formed by any suitable range of manufacturing processes, including thin film deposition processes (e.g., CVD, PVD, ALD, etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, CMP, etc.).

[0120] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidelines provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed implementation methods and equivalents.

[0121] The breadth and scope of this disclosure should not be limited by any of the embodiments described above, but only by the following claims and their equivalents.

Claims

1. A memory device, comprising: An array of memory cells in an array region; The character lines extend parallel to the first horizontal direction; Bit lines extending parallel to the second transverse direction; as well as An interconnect structure located in the array region and coupled to the word lines, and arranged in staggered columns along the second lateral direction.

2. The memory device according to claim 1, wherein: The first distance between two word line interconnect structures coupled to two adjacent word lines is greater than the second distance between the two adjacent word lines.

3. The memory device according to claim 1, wherein: The first column of interconnect structure is located on the first side of the center position of the array region; and The second column of interconnect structure is located on the second side opposite to the first side at the central position.

4. The memory device according to claim 1, wherein: The first column interconnect structure is located on the first side of a bit line; and The second column interconnect structure is located on the second side of the bit line opposite to the first side.

5. The memory device according to claim 3, wherein, The third distance between the first column interconnect structure and the center position is equal to the fourth distance between the second column interconnect structure and the center position.

6. The memory device according to claim 3, wherein, The third distance between the first column interconnect structure and the center position is different from the fourth distance between the second column interconnect structure and the center position.

7. The memory device according to claim 1, wherein, The first and second interconnect structures are located on the same side of the center of the array region.

8. The memory device according to claim 1, further comprising: The conductive layer connected to the first end of the interconnect structure, The second end of the interconnect structure is connected to the word line.

9. The memory device according to claim 1, wherein: The interconnect structure includes multiple rows of interconnect structures aligned parallel to each other along the first lateral direction; and The interconnect structures in the same row are connected to the same word line.

10. The memory device of claim 9, further comprising: The first conductive layer connected to the interconnect structure in the odd-numbered rows; as well as A second conductive layer connected to the interconnect structure of even-numbered rows.

11. The memory device according to claim 1, wherein: Each memory cell in the array of memory cells includes a vertical transistor and a memory cell coupled to the vertical transistor; and Each word line includes the gate structure of a vertical transistor in a corresponding row aligned along the first lateral direction.

12. The memory device according to claim 11, wherein, In each vertical transistor, the gate structure is located on the lateral side of the channel structure of the vertical transistor.

13. The memory device according to claim 12, wherein, In each vertical transistor, the gate structure is located on three lateral sides of the channel structure of the vertical transistor.

14. The memory device according to claim 13, wherein, In each vertical transistor, the gate structure laterally surrounds the channel structure of the vertical transistor.

15. A method of forming a memory device, comprising: Bit lines extending parallel to the second lateral direction are formed on the semiconductor layer; An array forming vertical transistors includes: An array forming a vertical channel structure, wherein each column of the vertical channel structure along the second lateral direction is coupled to a corresponding bit line in the bit lines, and A gate structure is formed on the lateral side of each row of the vertical channel structure along a first lateral direction, wherein the gate structure of each column of the array of vertical transistors forms a word line along the first lateral direction. An interconnect structure is formed, each of the interconnect structures extending vertically through the semiconductor layer and contacting a corresponding word line; Remove the semiconductor layer to expose portions of the interconnect structure; and A conductive layer is formed that is coupled to the interconnect structure.

16. The method of claim 15, wherein: Forming the interconnect structure includes forming a multi-column interconnect structure that is parallel and aligned along the second lateral direction; and The interconnection structure of adjacent columns is arranged in an alternating manner.

17. The method of claim 15, wherein: Forming the interconnect structure includes forming a multi-row interconnect structure that is parallel and aligned along the first lateral direction; and The interconnect structures in the same row are connected to the same word line, and the interconnect structures in adjacent rows are arranged in an interleaved manner.

18. The method according to claim 17, wherein, Forming the conductive layer includes: A first conductive layer is formed to connect to the interconnect structure of the odd-numbered rows; and A second conductive layer is formed to connect to the even-numbered rows of the interconnect structure.

19. The method of claim 16, further comprising: An array of memory cells is formed on the array of vertical transistors.

20. A method of forming a memory device, comprising: An array of semiconductor pillars is formed on a semiconductor layer; An insulating layer is formed on the semiconductor layer to laterally isolate the semiconductor pillars; Sacrificial structures are formed, each sacrificial structure extending vertically through the insulating layer and into the semiconductor layer; Conductive lines are formed, each conductive line being located on the lateral side of each row of the semiconductor pillars along a first lateral direction, wherein the conductive lines contact the sacrificial structure; Remove the semiconductor layer to expose a portion of the sacrificial structure; The sacrificial structure is replaced with an interconnect structure; and A conductive layer is formed that is coupled to the interconnect structure.

21. The method of claim 20, wherein: Forming the sacrificial structure includes forming multiple rows of sacrificial structures that are parallel and aligned along the second transverse direction; and The sacrificial structures in adjacent columns are arranged in an alternating pattern.

22. The method of claim 20, wherein: Forming the sacrificial structure includes forming multiple rows of sacrificial structures that are parallel and aligned along the first transverse direction; and The sacrificial structures in the same row are connected to the same conductive line, and the sacrificial structures in adjacent rows are arranged in an alternating manner.

23. The method according to claim 22, wherein, Forming the conductive layer includes: A first conductive layer is formed to connect to the interconnect structure of the odd-numbered rows; and A second conductive layer is formed to connect to the even-numbered rows of the interconnect structure.

24. The method of claim 21, further comprising: A bit line is formed, the bit line extending parallel to the second lateral direction and coupled to the second end of the array of semiconductor pillars; as well as An array of memory cells coupled to the second end of the array of semiconductor pillars.

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