Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, the semiconductor structure comprises bit lines, the bit lines extend in a first direction and are arranged at intervals in a second direction, and the first direction intersects with the second direction; the shielding lines are located between every two adjacent bit lines, extend in the first direction and are alternately arranged with the bit lines in the second direction; the active columns are located on the bit lines and are arranged in an array mode in the first direction and the second direction; the bit line contact structure is located between the bit line and the active column and is connected with the bit line and the active column, and the width of the bit line contact structure in the second direction is smaller than that of the bit line and the active column in the second direction. The shielding line can be connected with a direct-current power supply to form a conductive barrier, so that when one of the two adjacent bit lines 3 is powered on or powered off, the other bit line is less influenced or is not influenced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of Dynamic Random Access Memory (DRAM) technology, the size of a memory cell is getting smaller and smaller, and the array architecture thereof is changing from 8F 2 to 6F 2 to 4F 2 (F: the minimum pattern size that can be obtained under given process conditions).

[0003] However, in the structure designed at 4F 2 , how to reduce the area of a single array region transistor as much as possible and pursue higher chip area utilization rate is still a problem to be solved at present. SUMMARY

[0004] Based on this, the present application provides a semiconductor structure and a preparation method thereof, which can reduce the device volume and reduce the difficulty of the preparation process.

[0005] In one aspect, according to some embodiments, a semiconductor structure is provided, characterized by comprising:

[0006] active pillars, arranged in an array in a first direction and a second direction, the first direction intersecting the second direction;

[0007] bit lines, extending in the first direction and arranged at intervals in the second direction, and connected to the active pillars arranged along the first direction;

[0008] shield lines, located between two adjacent bit lines, extending in the first direction, and arranged alternately with the bit lines in the second direction;

[0009] bit line contact structures, located between the bit lines and the active pillars and connected to the bit lines and the active pillars, the width of the bit line contact structure in the second direction being smaller than the width of the bit line and the active pillar in the second direction.

[0010] In some embodiments, the bit line contact structure is connected to two adjacent active pillars in the second direction.

[0011] In some embodiments, the width of the shield line in a third direction is not less than the width of the bit line in the third direction, the third direction intersecting the first direction and the second direction.

[0012] In some embodiments, the width of the bit line decreases as the bit line extends to the bit line contact structure.

[0013] In some embodiments, the semiconductor structure further comprises:

[0014] a bit line protection layer, the bit line protection layer being located on a side of the bit line away from the bit line contact structure;

[0015] a bit line isolation layer, the bit line isolation layer being located between two adjacent bit lines, the shield line being located in the bit line isolation layer;

[0016] the material of the bit line protection layer and the bit line isolation layer are different.

[0017] In some embodiments, the bit line comprises at least one layer of metal material;

[0018] the shield line comprises at least one layer of metal material.

[0019] In some embodiments, the semiconductor structure further comprises:

[0020] a shield line blocking layer, the shield line blocking layer covering the shield line layer.

[0021] In some embodiments, there is a gap between the bit line isolation layer and the shield line.

[0022] In some embodiments, the shield line has a cross-sectional shape in a direction perpendicular to the first direction, which is conical, long strip-shaped, elliptical, star-shaped or other suitable shape.

[0023] In some embodiments, the semiconductor structure further comprises:

[0024] a word line, the word line extending in the second direction and being spaced apart in the first direction, the word line being connected to the active pillar in the second direction;

[0025] a storage structure, the storage structure being connected to the active pillar and being located at an end of all active pillars away from the bit line.

[0026] In another aspect, the present application also provides, according to some embodiments, a method for manufacturing a semiconductor structure, comprising:

[0027] forming an active pillar, the active pillar being arranged in an array in a first direction and a second direction, the first direction intersecting the second direction;

[0028] forming a bit line, the bit line extending in the first direction and being spaced apart in the second direction, and connecting the active pillar arranged in the first direction;

[0029] forming a shield line, the shield line being located between two adjacent bit lines and extending in the first direction and being alternately arranged with the bit line in the second direction;

[0030] forming a bit line contact structure; the bit line contact structure connects the bit line and the active pillar, a width of the bit line contact structure in the second direction is less than a width of the bit line and the active pillar in the second direction.

[0031] In some embodiments, the forming a bit line includes:

[0032] providing a substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction;

[0033] patterning and etching a bit line isolation trench on the first surface, a size of a bottom of the bit line isolation trench is greater than a size of a top of the bit line isolation trench, the bit line isolation trench extends in the first direction and is spaced apart in the second direction;

[0034] filling the bit line isolation trench to form a bit line isolation layer;

[0035] grinding the second surface to expose the bit line isolation layer, and etching the substrate to form a bit line trench using the bit line isolation layer as a mask;

[0036] filling the bit line trench with at least one layer of metal material to form the bit line;

[0037] forming a bit line protection layer on the bit line, the bit line protection layer and the bit line isolation layer are of different materials.

[0038] In some embodiments, the forming a shield line includes:

[0039] etching the bit line isolation layer to form a shield line trench using the bit line protection layer as a mask on the second surface, a depth of the shield line trench is not less than a depth of the bit line trench;

[0040] filling the shield line trench with at least one layer of metal material to form the shield line.

[0041] In some embodiments, the bit line contact structure includes a metal silicide, and forming a metal silicide includes:

[0042] depositing a layer of metal material at a bottom of the bit line trench and performing a high-temperature treatment to form the metal silicide; or

[0043] depositing a layer of metal material at a bottom of the bit line isolation trench and performing a high-temperature treatment to form the metal silicide.

[0044] In some embodiments, after filling the bit line isolation trench to form a bit line isolation layer, the method further includes:

[0045] forming word line isolation trenches on the first surface, the word line isolation trenches having a depth less than the depth of the bit line isolation trenches, the bit line isolation trenches extending in a second direction and being spaced apart in a first direction, the word line isolation trenches and the bit line isolation trenches forming the active pillars;

[0046] forming active pillars further comprises:

[0047] forming word lines in the word line isolation trenches, the word lines extending in the second direction and being spaced apart in the first direction, the word lines connecting the active pillars in the second direction;

[0048] forming memory structures at an end of the active pillars away from the bit lines.

[0049] The semiconductor structure and the preparation method thereof provided in the application have at least the following beneficial effects:

[0050] The semiconductor structure and the preparation method thereof provided in the application can reduce the resistance of the bit lines by forming the metal bit lines on the back surface of the wafer, and can reduce the coupling capacitance between adjacent bit lines by forming the metal shielding lines between the bit lines, thereby improving the stability of the device. By using different etching selectivity ratios between the substrate, the bit line isolation layer and the bit line protection layer, the number of masks can be reduced and the production cost can be reduced by using the self-aligned etching process. In addition, adjacent bit lines can share one bit line, thereby reducing the difficulty of the device process. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0052] Figure 1a the top view schematic diagram of the semiconductor structure provided for some disclosed embodiments, Figure 1b and Figure 1c the cross-sectional structure schematic diagram along the bit line and word line directions, respectively;

[0053] Figure 2 the cross-sectional structure schematic diagram along the word line direction of the semiconductor structure provided for some embodiments of the application;

[0054] Figures 3a-3e the cross-sectional structure schematic diagram along the word line direction of the semiconductor structure provided for some embodiments of the application;

[0055] Figures 4a-4lFig. 1 shows a cross-sectional structure along a word line direction of a method for manufacturing a semiconductor structure according to some embodiments of the present application;

[0056] Figures 5a-5f Fig. 2 shows a cross-sectional structure along a word line direction of a method for manufacturing a semiconductor structure according to some embodiments of the present application;

[0057] BRIEF DESCRIPTION OF DRAWINGS

[0058] 1, substrate; 2, word line; 3, bit line; 4, active pillar; 5, word line isolation trench; 6, bit line isolation trench; 601, initial bit line isolation trench; 602, first bit line isolation trench; 603, second bit line isolation trench; 7, sidewall protection layer; 8, bit line isolation layer; 9, storage contact; 10, bit line contact; 11, storage structure; 12, bit line trench; 13, bit line material layer; 301, first bit line material layer; 302, second bit line material layer; 14, bit line protection layer; 15, shield line trench; 16, shield line; 1601, first shield line material layer; 1602, second shield line material layer; 17, void; 18, shield line barrier layer. DETAILED DESCRIPTION

[0059] For the purpose of promoting an understanding of the present application, the present application will now be described in more detail with reference to the drawings. Given that the preferred embodiments of the present application are shown in the drawings, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application will be more thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0061] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In addition, it will be understood that when a term is used in the singular, it can be intended to include the plural, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] Spatially relative terms, such as "on", "above", "below", "bottom", "top", "side", "upper", "lower", "horizontal", "vertical", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features. Thus, the exemplary term "above" can encompass both an orientation that is above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0063] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] Embodiments of the application can be described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application, unless so specified.

[0065] Reference is made to Figure 1aIn some related embodiments, the semiconductor structure can include a plurality of bit lines (BL) 3 extending in a first direction (e.g., X direction) and arranged in a second direction (e.g., Y direction), a plurality of word lines (WL) 2 extending in the second direction and arranged in the first direction, the bit lines 3 and the word lines 2 intersecting at active pillars 4 in space, and a plurality of active pillars 4 extending in a third direction (e.g., Z direction) perpendicular to the substrate 1 and arranged in an array. In the preparation of the bit lines 3, first, a bit line isolation trench 6 is formed and filled, as shown in FIG. 1, then a word line isolation trench 5 is etched, as shown in FIG. 2, and the substrate is modified in the word line isolation trench by ion implantation, doping or metal diffusion to form the bit line 3. As the size of the bit line 3 becomes smaller and smaller, the resistance of the bit line 3 becomes larger and larger, and at the same time, the distance between adjacent bit lines 3 becomes smaller and smaller, and the corresponding coupling effect becomes larger and larger, which greatly affects the performance of the semiconductor structure. In addition, the process of forming the bit line 3 also causes certain damage to the word line isolation trench, the storage contact and the active pillar, etc., which greatly limits the development of the semiconductor structure preparation process. Figure 1c Figure 1b As the size of the bit line 3 becomes smaller and smaller, the resistance of the bit line 3 becomes larger and larger, and at the same time, the distance between adjacent bit lines 3 becomes smaller and smaller, and the corresponding coupling effect becomes larger and larger, which greatly affects the performance of the semiconductor structure. In addition, the process of forming the bit line 3 also causes certain damage to the word line isolation trench, the storage contact and the active pillar, etc., which greatly limits the development of the semiconductor structure preparation process.

[0066] The present application provides a semiconductor structure and a preparation method thereof, which can reduce the size of the device, and the details will be described in the subsequent embodiments.

[0067] In one aspect, the present application provides a semiconductor structure according to some embodiments.

[0068] Please refer to Figure 2 In some embodiments, the semiconductor structure can include a plurality of bit lines 3, a plurality of active pillars 4, a plurality of shield lines 16 and bit line contact structures 10. The plurality of bit lines 3 extend in a first direction (e.g., X direction) and are arranged in a second direction (e.g., Y direction) with a spacing, the first direction intersects the second direction; the plurality of shield lines 16 are located between two adjacent bit lines 3 and extend in the first direction, and are arranged in the second direction alternately with the bit lines 3; the plurality of active pillars 4 extend in a third direction (e.g., Z direction) away from the bit lines 3 and are arranged in an array in the first direction and the second direction; the bit line contact structures 10 are located between the bit lines 3 and the active pillars 4 and connect the bit lines 3 and the active pillars 4, and the width of the bit line contact structures 10 in the second direction is smaller than the width of the bit lines and the active pillars in the second direction.

[0069] ​In the semiconductor structure provided by the above embodiments, the shielding lines 16 are arranged between the adjacent bit lines 3 and are arranged alternately with the bit lines in the second direction, so that the shielding lines 16 can reduce the coupling effect between the adjacent two bit lines 3 and provide stability of the semiconductor structure. The width of the bit line contact structure 10 in the second direction is smaller than the width of the bit line 3 and the active pillar 4 in the second direction, so that the width of the bit line 3 in the second direction can be increased, the resistance of the bit line 3 can be reduced, and the manufacturing difficulty of the bit line 3 can be reduced.

[0070] Please refer to Figure 2 and Figure 3a Fig. In some embodiments, one bit line contact structure can be connected to one active pillar 4, and one bit line contact structure 10 can also be connected to the adjacent two active pillars 4 in the second direction, please refer to Figure 2 , that is, the adjacent two active pillars 4 share one bit line contact structure 10 and one bit line 3, so that the bit line density can be reduced, the integration can be improved, the distance between the bit lines can be increased, the width of the bit line 3 can be increased, the resistance of the bit line 3 can be reduced, and the performance of the device can be improved.

[0071] Please continue to refer to Figure 2 In some embodiments, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) is not less than the width D2 of the bit line 3 in the third direction (for example, the Z direction), the width D1 of the shielding line 16 in the third direction (for example, the Z direction) exceeds the width D2 of the bit line 3 in the third direction (for example, the Z direction), and optionally, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) exceeds the sum of the width of the bit line 3 and the width of the bit line contact structure 10 in the third direction (for example, the Z direction), so that the shielding line 16 can completely shield the coupling effect between the adjacent bit lines 3 and improve the performance of the device.

[0072] Please continue to refer to Figure 2 In some embodiments, the width of the bit line 3 in the second direction (for example, the Y direction) decreases as the bit line extends to the bit line contact structure, which can be understood as that the bit line is inverted trapezoidal, so that the resistance of the bit line 3 can be reduced, and the manufacturing process difficulty of the bit line 3 can be reduced.

[0073] Please continue to refer to Figure 2In some embodiments, the semiconductor structure can include a bit line protection layer 14 on the side of the bit line 3 away from the bit line contact structure 10 and extending in a first direction (e.g., X) and arranged in a second direction (e.g., Y), and a bit line isolation layer 8 between adjacent bit lines 3 to insulate and separate the adjacent bit lines. The material of the bit line protection layer 14 and the bit line isolation layer 8 is not specifically limited. For example, the material of the bit line protection layer 14 can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, or the like or a combination thereof, and the material of the bit line isolation layer 8 can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, or the like or a combination thereof. However, the materials of the bit line isolation layer 8 and the bit line protection layer 14 must be different. For example, the bit line protection layer 14 can be silicon nitride, and the bit line isolation layer can be silicon oxide. In this way, when etching the bit line isolation layer 8, a self-aligned method can be used to selectively etch the bit line isolation layer 8 using the bit line protection layer 14 as a template, which can reduce the process difficulty and save costs.

[0074] Please continue to refer to Figure 2 and refer to Figure 3c In some embodiments, the bit line 3 and the shield line 16 can be one layer or multiple layers. For example, Figure 3cIn some embodiments, the bit line 3 can include a bit line first material layer 301 and a bit line second material layer 302. The bit line first material layer 301 and the bit line second material layer 302 can be in any positional relationship, such as, for example, stacked, surrounded, half-surrounded, and the like. The shield line 16 can include a shield line first material layer 1601 and a shield line second material layer 1602. The shield line first material layer 1601 and the shield line second material layer 1602 can be in any positional relationship, such as, for example, stacked, surrounded, half-surrounded, and the like. The material of the bit line 3 and the shield line 16 is not limited, and can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line 3 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The material of the shield line 16 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the shield line 16 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The bit line 3 and the shield line 16 can include at least one metal material layer, which can reduce the resistance of the bit line 3 and the shield line 16 and improve the performance of the device.

[0075] Please continue to refer to Figure 2 In some embodiments, the semiconductor structure can include a direct current bias (DC bias) connected to the shield line 16 through a connection contact (not shown). The DC bias can provide a stable voltage to the shield line 16, so that the shield line 16 forms a conductive barrier, and when one of the two adjacent bit lines 3 is powered on or powered off, the other one of the two bit lines 3 is less affected or not affected.

[0076] Please refer to Figure 3bIn some embodiments, the shield line 16 does not fully contact the bit line isolation layer 8 at least in some portions, and there is a gap 17 between the shield line 16 and the bit line isolation layer 8. The relative position of the gap 17 between the shield line 16 and the bit line isolation layer 8 is not limited, and as an example, the gap 17 can be located at the bottom of the shield line, one side of the sidewall, and semi-surrounding the shield line, etc. The size and shape of the gap 17 are not limited, and as an example, the gap can be spherical, droplet-shaped, short tube-shaped, ellipsoidal, long strip-shaped, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of vacuum, the gap 17 and the bit line isolation layer 8 together embody a low dielectric constant effect to reduce the overall dielectric constant, which can reduce the parasitic capacitance and avoid the capacitive coupling effect between the bit line 3 and the adjacent bit line 3, thereby reducing the influence of the parasitic capacitance on the performance parameters of the device.

[0077] Referring to Figure 3d In some embodiments, the shield line 16 has an irregular structure in the cross-sectional shape perpendicular to the first direction, for example, can be conical, long strip-shaped, oval, star-shaped, or other suitable shapes. The shield line is formed in the bit line isolation layer 8, and the size of the shield line 16 is affected by the material of the bit line isolation layer 8 and the etching ability of the equipment. The shield line 16 in an irregular structure can increase the process preparation window and reduce the preparation process cost.

[0078] Referring to Figure 3e In some embodiments, a shield line blocking layer 18 can also be provided above the shield line 16, which covers the shield line 16 and can protect the shield line 16 from being damaged in subsequent processes. The material of the shield line blocking layer 18 is not limited and can be the same as or different from the material of the bit line protection layer 14.

[0079] Please continue to refer to Figure 2 and Figures 3a-3e In some embodiments, the semiconductor structure further includes a word line 2, a storage contact 9 at one end of the active pillar, a storage structure 11, and a back-end-of-line and protection layer (not shown in the figure) located on the storage structure 11. Specifically, the word line 2 extends along the second direction and is arranged in the first direction. The word line surrounds the active pillar 4 on one side, two sides, or three sides and controls the movement of the electric charge of the active pillar 4. The material of the word line is not limited, and as an example, the material of the word line 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line 2 can include but is not limited to doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0080] The storage contact 9 is located at the end of the active pillar 4 away from the bit line contact 10, connecting the active pillar 4 and the storage structure 11, and the material of the storage contact 9 is not limited, for example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi and combinations thereof, which can reduce the contact resistance between the active pillar 4 and the storage structure 11.

[0081] The storage structure 11 can be a capacitor structure including upper and lower electrode plates and a high-k dielectric material between the upper and lower electrode plates, or a variable resistance storage structure which is switched to two resistance states by an electrical pulse applied to the memory element, for example, the variable resistance storage structure can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0082] In another aspect, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments. In order to more clearly illustrate the method for manufacturing a semiconductor structure according to some embodiments of the present application, the following can be understood in combination with FIGS. 1-3.

[0083] Figures 4a-4l is a view showing an intermediate step for describing a method for manufacturing a semiconductor memory device according to some embodiments.

[0084] Reference Figure 4a A substrate 1 is provided, which has opposite first and second surfaces in a third direction (e.g., Z direction), and an initial bit line isolation trench 601 is formed by patterning and etching the first surface.

[0085] Specifically, in some embodiments, the material of the substrate 1 is not limited, for example, the material of the substrate 1 can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials, etc.

[0086] In some embodiments, the formation of the initial bit line isolation trench 601 by patterning and etching can include forming a mask layer on the first surface of the substrate 1, which can include one, two or more layers of material, depositing a photoresist layer, and after exposure and development, etching the mask layer and the substrate 1 to form the initial bit line isolation trench 601. The etching method can use dry etching, wet etching or a combination of the two, which is not limited.Figure 2 and Figure 3a A column of active pillars 4 can be connected to a column of bit lines 3, or two adjacent columns of active pillars 4 can share a column of bit lines 3. In this way, two adjacent columns of active pillars 4 sharing a bit line can reduce the space between adjacent bit lines, thereby reducing the device volume, and can also make the internal layout of the semiconductor structure more reasonable, thereby effectively improving the storage density of the semiconductor structure. This embodiment uses two columns of active pillars 4 sharing a bit line 3 as an example, and the formed initial bit line isolation trench 601 adopts a double spacing, that is, the substrate between adjacent initial bit line isolation trenches 601 is twice the distance between the active pillars 4 and a bit line isolation trench 6, which can increase the process preparation window and improve the stability of device performance.

[0087] refer to Figure 4b In some embodiments, the mask layer that is not removed by etching is modified so that its size matches the width of the bitline trench 6, or the width of the exposed substrate that is not etched is equivalent to the width of the active pillar 4. The specific width is not limited and can be determined according to process requirements, for example, any width between 10nm and 40nm. A sidewall protection layer 7 is deposited in the initial bitline isolation trench 601 and on the first surface of the substrate and the surface of the mask layer that is not removed by etching. The sidewall protection layer 7 can protect the first surface of the substrate and the surface of the mask layer that is not removed by etching from the first surface of the substrate from being damaged during subsequent processing. The sidewall protection layer 7 is etched to open the sidewall protection layer at the bottom of the initial bitline isolation trench 601. Then, a co-directional etching method is used to form the first bitline isolation trench 602. The co-directional etching method can use dry etching, wet etching, or a combination of the two, and is not specifically limited. Due to the use of unidirectional etching, the width of the first bit line isolation trench 602 in the second direction is greater than the width of the initial bit line isolation trench 601 in the second direction, and portions of the substrate on both sides of the first bit line isolation trench 602 are removed by etching.

[0088] refer to Figure 4cIn some embodiments, the initial bit line isolation trench 601 and the first bit line isolation trench 602 are filled with an insulating material, and a planarization process is performed to expose the mask layer that is not removed by etching. Specifically, in some embodiments, the insulating material can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, or a combination thereof, and the insulating material has a different material quality than the mask layer. The deposition method can include, but is not limited to, chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, high intensity deposition, or a combination thereof. The mask layer that is not removed is selectively etched, the mask layer and the bit line isolation layer 8 have different materials, and the etching can be performed without a mask using a self-alignment method. The etching method can use dry etching, wet etching, or a combination thereof. The mask layer is modified to have a size that is consistent with the bit line isolation trench 6, and the second bit line isolation trench 603 pattern is formed after the mask layer is removed.

[0089] Reference Figure 4d In some embodiments, the second bit line isolation trench 603 pattern formed according to the above steps is used to form the second bit line isolation trench 603. The second bit line isolation trench 603 extends in the first direction and is located between adjacent first bit line isolation trenches 602. The second bit line isolation trench 603 is spaced apart from the first bit line isolation trench 602 in the second direction. Since the first bit line isolation trench 602 and the second bit line isolation trench 603 are spaced apart and are formed in steps, the distance between adjacent bit line isolation trenches 6 is large when the first bit line isolation trench 602 and the second bit line isolation trench 603 are separately prepared, which increases the process window and improves the stability of the device.

[0090] Reference Figure 4eIn some embodiments, the bit line contact 10 is formed at the bottom of the second bit line isolation trench 603 and is in contact with the substrate on both sides, and is in contact with the adjacent first bit line isolation trench 602 in the second direction. Specifically, a sidewall protection layer is formed on the second bit line isolation trench 603 and the substrate surface to prevent damage or influence of the substrate in subsequent processes. The protection layer at the bottom of the second bit line isolation trench 603 and the substrate surface is etched to expose the substrate. The bit line contact 10 and the storage contact 9 are formed by ion implantation, deposition of high-concentration doping material for diffusion, or deposition of metal material for metal silicidation reaction, etc. The bit line contact 10 and the storage contact 9 can be formed in steps or in one step, without specific limitation. The material of the storage contact 9 is not limited specifically, and as an example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof. The material of the bit line contact 10 is not limited specifically, and as an example, the material of the bit line contact 10 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0091] Reference is made to Figure 4f In some embodiments, the bit line isolation layer 8 is formed by filling the second bit line isolation trench 603 with an insulating material, and planarization processing. The bit line isolation structure 8 extends in the first direction and is arranged in the second direction.

[0092] Reference is made to Figure 1b and Figure 4gIn some embodiments, the substrate first surface is patterned and etched to form word line isolation trenches 5, and the word line isolation trenches 5 and the bit line isolation trenches 6 form the active pillars 4. The word lines 2 are formed in the word line isolation trenches 5, and the word lines 2 extend in the second direction and are arranged in the first direction. The word lines 2 surround the active pillars 4 on one side, two sides, or three sides of the active pillars 4 and control the charge movement of the active pillars 4. The material of the word lines 2 is not limited in particular, and as an example, the material of the word lines 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word lines 2 can include, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0093] The storage structures 11 are formed on the storage contacts 9, and back-end-of-line (not shown in the figure) is formed on the storage structures 11. The storage structures 11 can be a capacitor structure including an upper electrode plate, a lower electrode plate, and a high-k dielectric material between the upper electrode plate and the lower electrode plate, or a variable resistance storage structure that is switched to two resistance states by an electrical pulse applied to the memory element. For example, the variable resistance storage structure can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0094] Reference is made to Figure 4h In some embodiments, the substrate is flipped, and a grinding process is used to thin the second surface of the substrate, and the bit line isolation layer 8 is used as an etching stop layer.

[0095] Reference is made to i in FIG. 4. In some embodiments, since the bit line isolation layer 8 is different in material from the substrate, a self-alignment process can be used to selectively etch and remove the substrate material to form the bit line trenches 12. The self-alignment process can reduce the number of exposures and reduce the process cost.

[0096] Reference is made to Figure 4j In some embodiments, a bit line material layer 13 is deposited in the bit line trenches 12, and the material of the bit line material is not limited in particular, and as an example, the bit line material layer 13 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0097] Reference is made to Figure 4kIn some embodiments, the etching bit line material layer 13 forms the bit line 3, and the bit line protection layer 14 is formed on the bit line 3, and the bit line protection layer 14 is planarized by using a grinding process. Specifically, a selective etching method is used to etch and remove part of the bit line material layer 13, so that the bit line material layer 13 is formed only in the bit line trench 12 to form the bit line 3. Dry etching can be used, wet etching can be used, or a combination of the two can be used. The bit line protection layer 14 is deposited on the bit line 3. The material of the bit line protection layer 14 can include but is not limited to silicon nitride, silicon oxide, silicon oxynitride, and silicon nitride, or a combination thereof. The material of the bit line protection layer 14 is different from the material of the bit line isolation layer 8.

[0098] Reference Figure 4l In some embodiments, the bit line isolation layer 8 is etched to form a shielding line trench 15 in the bit line isolation layer 8. Specifically, since the material of the bit line isolation layer 8 and the material of the bit line protection layer 14 are different, a self-aligned etching method can be used to etch and remove part of the bit line isolation layer 8 to form the shielding line trench 15. Dry etching can be used, wet etching can be used, or a combination of the two can be used. In some embodiments, dry etching can be used to form a trench with a certain depth, and then wet etching can be used to etch in the same direction at the bottom of the trench to make the width of the bottom of the trench larger, forming a different trench. Preventing the problem of open circuit caused by the inability of the shielding line material to fill the small bottom of the trench. Using a self-aligned etching process can reduce the number of photolithography processes, reduce production costs, and improve the stability of the device.

[0099] As can be seen from the foregoing steps, the width of the bit line isolation layer 8 in the second direction is large, and the process window of the shielding line trench 15 is also large. At the same time, the depth of the shielding line trench 15 in the third direction is also large. The bottom of the shielding line trench 15 is lower than the lowest plane of the bit line 3 in the third direction. In this way, the bit line shielding line 16 formed subsequently can protect the bit line 3 from signal interference from adjacent bit lines. In some embodiments, the bottom of the shielding line trench 15 can be lower than the lowest plane of the bit line contact 10 in the third direction, thereby improving the stability of the device. The shape of the shielding line trench 15 is not specifically limited. As an example, the cross-sectional shape of the shielding line trench 15 in the second direction can be conical, long strip-shaped, elliptical, star-shaped, or other suitable shapes.

[0100] Please continue to refer to Figure 2 and Figures 3a-3e The conductive material is deposited in the shielding line trench 15 to form the shielding line 16. In some embodiments, the shielding line 16 can be one layer or multiple layers, for example Figure 3cIn some embodiments, the shield line 16 can include a shield line first material layer 1601 and a shield line second material layer 1602. The shield line first material layer 1601 and the shield line second material layer 1602 can be in any positional relationship, such as, for example, stacked, surrounded, partially surrounded, and the like. The shield line 16 can be made of, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the shield line 16 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The shield line 16 includes at least one metal material layer, which can reduce the resistance of the shield line 16 and improve the performance of the device.

[0101] Please continue to refer to Figure 3b In some embodiments, the shield line 16 is not in complete contact with at least a portion of the bit line isolation layer 8, and there is a gap 17 between the shield line 16 and the bit line isolation layer 8. The relative position of the gap 17 between the shield line 16 and the bit line isolation layer 8 is not limited, and for example, the gap 17 can be located at the bottom of the shield line, on one side of the sidewall, and partially surround the shield line, and the like. The size and shape of the gap 17 are not limited, and for example, the gap can be spherical, droplet-shaped, short tube-shaped, ellipsoidal, long strip-shaped, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of vacuum, the gap 17 and the bit line isolation layer 8 together exhibit a low dielectric constant effect to reduce the overall dielectric constant, which can reduce the parasitic capacitance and avoid the capacitive coupling effect between the bit line 3 and the adjacent bit line 3, thereby reducing the influence of the parasitic capacitance on the performance parameters of the device.

[0102] Please continue to refer to Figure 3d In some embodiments, the cross-sectional shape of the shield line 16 on the third party can be an irregular structure, such as, for example, a cone, a long strip, an ellipse, a star, or other suitable shapes. The shield line is formed in the bit line isolation layer 8, and the size of the shield line 16 is affected by the material of the bit line isolation layer 8 and the etching ability of the equipment. The shield line 16 in an irregular structure can increase the process preparation window and reduce the preparation process cost.

[0103] Please continue to refer to Figure 3e In some embodiments, a shield line blocking layer 18 can be further provided above the shield line 16. The shield line blocking layer 18 covers the shield line 16 and can protect the shield line 16 from being damaged in subsequent processes. The material of the shield line blocking layer 18 is not limited and can be the same as or different from the material of the bit line protection layer 14.

[0104] Please continue to refer to Figure 2 In some embodiments, the width Dl of the shield line 16 in the third direction (e.g., Z direction) is not less than the width D2 of the bit line 3 in the third direction (e.g., Z direction), the width Dl of the shield line 16 in the third direction (e.g., Z direction) exceeds the width D2 of the bit line 3 in the third direction (e.g., Z direction), or the width Dl of the shield line 16 in the third direction (e.g., Z direction) exceeds the sum of the width of the bit line 3 and the width of the bit line contact structure 10 in the third direction (e.g., Z direction), so that the shield line 16 can completely shield the coupling effect between adjacent bit lines 3, thereby improving the performance of the device.

[0105] Please continue to refer to Figure 2 In some embodiments, the semiconductor structure can include a direct current bias (DC bias) connected to the shield line 16 through a connection contact (not shown) to give the shield line 16 a stable voltage, so that the shield line 16 forms a conductive barrier, thereby reducing or eliminating the influence of one of the two adjacent bit lines 3 when the other is powered on or off.

[0106] Figures 5a-5f is a view showing an intermediate step for describing a method for manufacturing a semiconductor memory device according to some embodiments. For the sake of convenience of description, parts that are simply described or omitted will be described or omitted in duplicate with reference to the Figures 4a-4l described parts. For reference, Figure 5a is a view showing Figure 4d the intermediate step that follows.

[0107] Please refer to Figure 5a In some embodiments, the second bit line isolation trench 603 is directly filled, and the material filling the second bit line isolation trench 603 is not specifically limited and can be the same as or different from the material filling the first bit line isolation trench 602. Planarization processing is performed to expose the first surface of the substrate 1 or not completely fill to expose the top end of the active pillar 4, and the storage contact 9 is formed at the top end of the active pillar. Specifically, the storage contact 9 is formed by ion implantation, deposition of high-concentration doped material for diffusion, deposition of metal material for metal silicidation reaction, or other suitable methods. The material of the storage contact 9 is not specifically limited, and as an example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSix, and combinations thereof.

[0108] Please refer to Figure 1b andFigure 5b In some embodiments, the first surface of the substrate is patterned and etched to form word line isolation trenches 5, and the word line isolation trenches 5 and the bit line isolation trenches 6 form the active pillars 4. Word lines 2 are formed in the word line isolation trenches, and the word lines 2 extend in the second direction and are arranged in the first direction, and the word lines 2 surround the active pillars 4 on one side, two sides, or three sides of the active pillars 4 and control the charge movement of the active pillars 4. The material of the word lines 2 is not limited, and as an example, the material of the word lines 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word lines 2 can include, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0109] The storage structures 11 are formed on the storage contacts 9, and back-end-of-line (not shown in the figure) is formed on the storage structures 11. The storage structures 11 can be a capacitor structure including upper and lower electrode plates and high-k dielectric material between the upper and lower electrode plates, or a variable resistance storage structure that is switched to two resistance states by an electrical pulse applied to the memory element, for example. The variable resistance storage structure can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0110] Referring to Figure 5c and Figure 5d In some embodiments, the substrate is flipped, the second surface of the substrate 1 is thinned, and planarization processing is performed with the first bit line isolation layer 8 as an etching stop layer.

[0111] Referring to Figure 5e In some embodiments, since the bit line isolation layer 8 is different in material from the substrate, a self-aligned process can be used to selectively etch and remove the substrate material to form the bit line trenches 12. The self-aligned process can reduce the number of exposures and reduce the process cost.

[0112] Referring to Figure 5fIn some embodiments, the bit line contact 10 is formed at the bottom of the bit line trench 12. The bit line contact 10 can be formed by ion implantation, deposition of high concentration doping material for diffusion, or deposition of metal material for metal silicidation reaction, etc. The material of the bit line contact 10 is not limited specifically. For example, the material of the bit line contact 10 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0113] Subsequently, referring to Figures 4j to 4l , the bit line 3 and the shield line 16 are formed. Thus, the semiconductor memory device described with reference to Figure 2 and Figures 3a to 3e can be manufactured.

[0114] It should be noted that the semiconductor structure preparation methods in the embodiments of the present application can be used to prepare corresponding semiconductor structures, and thus the technical features of the method embodiments and the structure embodiments can be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of the present application.

[0115] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combinations of the technical features do not conflict, they should be considered as the scope of the present application.

[0116] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, The application comprises: active columns arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; bit lines extending in the first direction and spaced apart in the second direction, and connecting the active columns arranged in the first direction; shield lines located between two adjacent bit lines and extending in the first direction, and alternating with the bit lines in the second direction; bit line contact structures located between and connecting the bit lines and the active columns, the bit line contact structures having a width in the second direction smaller than the width of the bit lines and the active columns in the second direction.

2. The semiconductor structure of claim 1, wherein, The bit line contact structures connect two adjacent active columns in the second direction.

3. The semiconductor structure according to claim 1 or 2, characterized in that The shield lines have a width in a third direction not less than the width of the bit lines in the third direction, the third direction intersecting the first direction and the second direction.

4. The semiconductor structure of claim 3, wherein, The width of the bit lines in the second direction decreases as the bit lines extend towards the bit line contact structures.

5. The semiconductor structure of claim 3, wherein, The application further comprises: bit line protection layers located on the side of the bit lines away from the bit line contact structures; bit line isolation layers located between two adjacent bit lines, the shield lines being located in the bit line isolation layers; The bit line protection layers and the bit line isolation layers are made of different materials.

6. The semiconductor structure of claim 3, wherein, The bit lines comprise at least one layer of metal material; The shield lines comprise at least one layer of metal material.

7. The semiconductor structure of any one of claims 4 to 6, wherein the semiconductor structure is a vertical semiconductor structure. The application further comprises: shield line blocking layers covering the shield line layers.

8. The semiconductor structure of claim 5, wherein, There is a gap between the bit line isolation layers and the shield lines.

9. The semiconductor structure of claim 8, wherein, The shield lines have a cross-sectional shape perpendicular to the first direction, which is conical, long strip-shaped, elliptical, star-shaped or other suitable shape.

10. The semiconductor structure of claim 3, wherein, The application further comprises word lines extending in the second direction and spaced apart in the first direction, the word lines connecting the active columns in the second direction; storage structures connected to the active columns and located at the end of all the active columns away from the bit lines.

11. A method of fabricating a semiconductor structure, characterized by, The application comprises: forming active columns arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; forming bit lines extending in the first direction and spaced apart in the second direction, and connecting the active columns arranged in the first direction; forming shield lines located between two adjacent bit lines and extending in the first direction, and alternating with the bit lines in the second direction; forming bit line contact structures connecting the bit lines and the active columns, the bit line contact structures having a width in the second direction smaller than the width of the bit lines and the active columns in the second direction.

12. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: The forming of the bit lines comprises: providing a substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction; patterning and etching bit line isolation trenches on the first surface, the bottom of the bit line isolation trenches having a size larger than the top of the bit line isolation trenches, the bit line isolation trenches extending in the first direction and spaced apart in the second direction; filling the bit line isolation trench to form a bit line isolation layer; grinding the second surface to expose the bit line isolation layer, and etching the substrate to form a bit line trench using the bit line isolation layer as a mask; filling the bit line trench with at least one layer of metal material to form the bit line; forming a bit line protection layer on the bit line, the bit line protection layer being different from the material of the bit line isolation layer.

13. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: the shield line includes: etching the bit line isolation layer to form a shield line trench using the bit line protection layer as a mask on the second surface, the depth of the shield line trench being not less than the depth of the bit line trench; filling the shield line trench with at least one layer of metal material to form the shield line.

14. The method of claim 12, wherein the method further comprises: the bit line contact structure includes a metal silicide, and forming the metal silicide includes: depositing a layer of metal material at the bottom of the bit line trench and performing heat treatment to form a metal silicide; or depositing a layer of metal material at the bottom of the bit line isolation trench and performing heat treatment to form a metal silicide.

15. The method of claim 12, wherein the method further comprises: after filling the bit line isolation trench to form a bit line isolation layer, the method further includes: patterning and etching on the first surface to form a word line isolation trench, the depth of the word line isolation trench being less than the depth of the bit line isolation trench, the bit line isolation trench extending in a second direction and being arranged at intervals in a first direction, the word line isolation trench and the bit line isolation trench forming the active pillar; after forming the active pillar, the method further includes: forming a word line in the word line isolation trench, the word line extending in the second direction and being arranged at intervals in the first direction, the word line being connected to the active pillar in the second direction; forming a storage structure at the end of the active pillar away from the bit line.

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