A trench type SiC MOSFET device structure and a manufacturing method thereof
By depositing a dielectric layer and growing a gate oxide layer in the gate trench, the problem of excessive electric field at the bottom of the gate trench in SiC MOSFET devices is solved, improving the reliability and switching characteristics of the devices and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XPT EDS (HEFEI) CO LTD
- Filing Date
- 2022-11-11
- Publication Date
- 2026-05-19
AI Technical Summary
Trench-type SiC MOSFET devices suffer from problems such as large electric field at the bottom of the gate trench, easy damage and breakdown, which limits their application in high reliability scenarios, and the existing process is also highly complex.
A first dielectric layer and a second dielectric layer are deposited in the gate trench. Part of the dielectric layer on the sidewalls is removed, the bottom dielectric layer is retained, a gate oxide layer is grown, and the gate is filled to form a thick oxide layer to protect the gate oxide layer and reduce the electric field.
The electric field distribution at the bottom of the gate trench is optimized, which improves device reliability and switching characteristics, simplifies the manufacturing process, and reduces the requirements for equipment and machines.
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Figure CN115642088B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, specifically to a trench-type SiC MOSFET device structure and its manufacturing method. Background Technology
[0002] Modern power electronic devices are developing towards higher power density and higher efficiency. Silicon carbide (SiC) power devices have seen rapid development in the field of high-efficiency power conversion in recent years due to their superior characteristics such as high voltage, high frequency, high temperature, and high power density. SiC MOSFET devices have advantages such as fast switching speed, high voltage resistance, and low power consumption. They are mainly divided into planar and trench types. Trench-type power SiC MOSFET devices have lower on-resistance and higher current density, achieving even lower on-resistance. They also have advantages such as high integration, low on-resistance, fast switching speed, and low switching losses, making them the mainstream in low-voltage and high-voltage applications. With the wide expansion of application areas and the continuous improvement of equipment performance, the reliability requirements for trench-type power SiC MOSFET devices are becoming increasingly stringent. However, trench-type power SiC MOSFET devices suffer from a large bottom electric field and are prone to breakdown or interface state injection, limiting their application in high-reliability scenarios. Summary of the Invention
[0003] This application provides a method for fabricating a trench-type SiC MOSFET device and a structure for a trench-type SiC MOSFET device, in order to solve the problem that existing trench-type power SiC MOSFET devices have a large electric field at the bottom of the gate trench, and the gate oxide is easily damaged and broken down, which limits their application in high reliability scenarios.
[0004] This application provides a method for fabricating a trench-type SiC MOSFET device, the method comprising:
[0005] A SiC epitaxial layer is formed on a SiC substrate;
[0006] In the SiC epitaxial layer forming body region;
[0007] Source injection is performed on the aforementioned body region to form a source electrode;
[0008] A gate trench is formed by etching within the body region. The bottom of the gate trench is located in the drift region of the SiC epitaxial layer. The first sidewall of the gate trench passes through the source electrode or contacts the source electrode.
[0009] A first dielectric layer and a second dielectric layer are deposited to form the first dielectric layer covering the first sidewall, the second sidewall, and the bottom of the gate trench, and the second dielectric layer filling the hollow area between the first sidewall and the second sidewall of the gate trench.
[0010] Remove part of the first dielectric layer covering the first sidewall, and at least retain part of the first dielectric layer covering the bottom of the gate trench to form a vacant area;
[0011] A gate oxide layer is grown on the surface of the first sidewall exposed in the vacant area;
[0012] A filler is filled between the gate oxide layer and the second dielectric layer to form a gate.
[0013] In some embodiments, after source implantation into the body region and before forming gate trenches in the body region by etching, the method further includes: performing P+ implantation into the body region to form a P+ region;
[0014] After filling polysilicon between the gate oxide layer and the second dielectric layer, the method further includes: forming Ni salicide on the surfaces of the source and the corresponding positions of the P+ region to obtain a source ohmic contact layer.
[0015] In some embodiments, the method further includes:
[0016] A contact hole is formed on the surface of the source ohmic contact layer;
[0017] Metal is filled into the contact hole to form a source electrode.
[0018] In some embodiments, the deposition forming a first dielectric layer and a second dielectric layer includes:
[0019] Silicon oxide is deposited so that it covers the surface of the SiC epitaxial layer and the sidewalls and bottom of the gate trench;
[0020] Silicon nitride is deposited on the upper surface of the silicon oxide to fill the remaining area of the gate trench;
[0021] Remove silicon nitride and silicon oxide from the area outside the gate trench, and retain silicon nitride and silicon oxide in the gate trench, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
[0022] In some embodiments, the removal of silicon nitride and silicon oxide outside the gate trench includes:
[0023] The top silicon nitride is removed by CMP or dry etching, and the silicon nitride protruding above the SiC epitaxial layer in the gate trench is also removed.
[0024] The silicon oxide protruding above the SiC epitaxial layer is removed using CMP.
[0025] In some embodiments, removing a portion of the first dielectric layer covering the first sidewall while retaining at least the first dielectric layer covering the bottom of the gate trench includes:
[0026] Photoresist is coated on the surface of the SiC epitaxial layer, and the photoresist is patterned using a photolithography process to form a patterned photoresist.
[0027] Based on the patterned photoresist, a wet etch-back process is used to remove part of the first dielectric layer covering the first sidewall, while at least the first dielectric layer covering the bottom of the gate trench is retained.
[0028] In some embodiments, removing a portion of the first dielectric layer covering the first sidewall while retaining at least the first dielectric layer covering the bottom of the gate trench includes:
[0029] Remove the first dielectric layer that covers the first sidewall and has the same depth as the second dielectric layer.
[0030] In some embodiments, a filler is filled between the gate oxide layer and the second dielectric layer to form a gate, including:
[0031] Polysilicon is deposited to form a polysilicon gate in the region between the gate oxide layer and the second dielectric layer, and the polysilicon on the surface of the SiC epitaxial layer is removed.
[0032] According to another aspect of the present invention, a trench-type SiC MOSFET device structure is provided, the trench-type SiC MOSFET device structure comprising:
[0033] SiC epitaxial layer located on SiC substrate;
[0034] The bulk region located in the SiC epitaxial layer;
[0035] The source electrode is located in the body region;
[0036] A gate trench located within the body region, the bottom of the gate trench being located in the drift region of the SiC epitaxial layer, and the first sidewall of the gate trench passing through or contacting the source electrode;
[0037] A gate oxide layer grown on the first sidewall of the gate trench;
[0038] A first dielectric layer covering the bottom of the gate trench and the surface of the second sidewall;
[0039] A second dielectric layer that fills the gate trench and is in contact with the first dielectric layer;
[0040] A gate that is filled within the gate trench and located between the gate oxide layer and the second dielectric layer.
[0041] In some embodiments, the trench-type SiC MOSFET device structure further includes:
[0042] The P+ region formed after P+ injection into the body region;
[0043] Source ohmic contact layers are formed on the surfaces of the corresponding positions of the source electrode and the P+ region;
[0044] The contact holes formed on the surface of the source ohmic contact layer and the source metal filling the contact holes.
[0045] Compared with the prior art, this application has the following advantages:
[0046] The method for fabricating a trench-type SiC MOSFET device provided in this application includes: growing a SiC epitaxial layer on a SiC substrate; forming a body region in the SiC epitaxial layer; performing source implantation on the body region to form a source electrode; forming a gate trench in the body region by etching, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and the first sidewall of the gate trench passes through or contacts the source electrode; depositing a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first sidewall, the second sidewall, and the bottom of the gate trench, and the second dielectric layer fills the hollow region between the first sidewall and the second sidewall of the gate trench; removing part of the first dielectric layer covering the first sidewall, and retaining at least the first dielectric layer covering the bottom of the gate trench to form a vacant region; growing a gate oxide layer on the surface of the first sidewall exposed in the vacant region; and filling the space between the gate oxide layer and the second dielectric layer to form a gate electrode. By depositing a first dielectric layer and a second dielectric layer in a gate trench, after removing a portion of the first dielectric layer covering the first sidewall and retaining at least a portion of the first dielectric layer covering the bottom of the gate trench to form a vacant region, a gate oxide layer is grown on the surface of the first sidewall exposed in the vacant region. A filler is then filled between the gate oxide layer and the second dielectric layer to form the gate. This gate trench filling method allows the remaining first and second dielectric layers in the gate trench to form a thick oxide layer to protect the gate oxide layer, reducing the electric field at the bottom of the gate trench, optimizing the electric field distribution at the bottom of the gate trench in the reverse cutoff state, and improving the reliability of the device. Furthermore, the thick oxide layer at the bottom and sidewalls of the gate trench can significantly reduce the gate charge, optimizing the switching characteristics of the device. Moreover, the above-described gate trench filling method does not require precise control of the depth of the body region or strict control of the gate position in the gate trench, simplifying the manufacturing process of trench-type SiC MOSFET devices and reducing equipment and tooling requirements, resulting in high manufacturability.
[0047] The above description is merely an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0048] Figure 1 This is a schematic flowchart of the method for fabricating a trench-type SiC MOSFET device provided in the embodiments of this application;
[0049] Figure 2 This is a schematic diagram of the trench-type SiC MOSFET device structure provided in the embodiments of this application;
[0050] Figures 3-17 This is a schematic diagram of the fabrication process of the trench-type SiC MOSFET device provided in this embodiment;
[0051] [Symbol Explanation]
[0052] 1. Substrate; 2. SiC epitaxial layer; 3. Bulk region; 4. Source; 5. Gate trench; 6. First dielectric layer; 7. Second dielectric layer; 8. Gate oxide layer; 9. P+ region; 10. Nisalicide; 11. Contact hole; 12. Source metal; 13. Dielectric layer; 14. Surface metal; 15. Back metal; 16. Photoresist; 17. Temporary protective layer; 18. Drift region; 19. First sidewall; 20. Second sidewall. Detailed Implementation
[0053] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.
[0054] Compared to traditional silicon (Si) materials, silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown electric field, high saturation drift velocity, and high thermal conductivity, making it an ideal material for fabricating high-voltage, high-power devices. It is widely used in high-efficiency, high-power, and high-temperature power electronics technology and has become a research hotspot in current power semiconductor technology. Power MOSFET devices based on SiC have advantages such as high current density, high breakdown voltage, low loss, good high-temperature characteristics, and radiation resistance. Compared to traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems, reduce system size, and lower power losses. Power SiC MOSFET devices have two structures: flat-gate and trench. Flat-gate power SiC MOSFET devices have a parasitic junction field-effect transistor (JFET) structure, which increases the on-resistance and power consumption. Because of the trench gate structure, trench power SiC MOSFET devices do not have a JFET region, which can significantly reduce the on-resistance of the device. In addition, the conductive channel is changed from horizontal to vertical, which effectively saves the device area and greatly improves the power density.
[0055] Because trench power SiC MOSFET devices have lower on-resistance and higher current density, they have advantages such as high integration, low on-resistance, fast switching speed and low switching loss. They have become the mainstream in low-voltage and high-voltage applications. With the wide expansion of application fields and the continuous improvement of equipment performance, the reliability requirements for trench power SiC MOSFET devices are also getting higher and higher.
[0056] However, trench-type power SiC MOSFET devices suffer from a large bottom electric field due to the electric field accumulation effect at the bottom corner of the trench, making them susceptible to breakdown or interface state injection, thus limiting their application in high-reliability scenarios. Specifically, trench-type power SiC MOSFET devices have lower on-resistance and higher current density, but the excessive electric field at the bottom of the gate trench makes the gate oxide layer prone to damage and breakdown, limiting their application in high-reliability scenarios. To protect the gate oxide layer of the gate trench, existing trench-type SiC MOSFET devices protect the gate oxide layer at the bottom of the gate trench by using a deep body region early depletion method. That is, the body region is located vertically below the gate trench. When the device is subjected to reverse breakdown voltage, the depletion layer widens until the depletion layers on both sides of the trench close together to protect the gate oxide layer at the bottom of the gate trench. However, this process requires precise control of the depth of the body region, which increases the process complexity. For example, if the body region depth is too shallow, the protection of the gate oxide layer will be weakened, and the surge capability of the device will be weakened; if the body region depth is too deep, the breakdown voltage of the device will be reduced.
[0057] To address the aforementioned problems of existing trench-type power SiC MOSFET devices, and to resolve the limitations imposed by the large electric field at the bottom of the gate trench, susceptibility to gate oxide damage and breakdown, which restricts their application in high-reliability scenarios, and to reduce process complexity, this application provides a method for fabricating a trench-type SiC MOSFET device and a trench-type SiC MOSFET device structure. Please refer to... Figure 1 , Figure 2 as well as Figures 3-17 Understanding this embodiment, Figure 1 This is a flowchart of the method for fabricating a trench-type SiC MOSFET device provided in this embodiment. Figure 2 This is a schematic diagram of the trench-type SiC MOSFET device structure provided in this embodiment; Figures 3-17 This is a schematic diagram of the fabrication process of the trench-type SiC MOSFET device provided in this embodiment.
[0058] like Figures 1-17 As shown, the method for fabricating a trench-type SiC MOSFET device provided in this embodiment includes the following steps:
[0059] S1: Form a SiC epitaxial layer 2 on a SiC substrate 1; specifically, a lightly doped SiC epitaxial layer 2 can be grown on the upper surface of a heavily doped SiC substrate 1.
[0060] S2: Forming bulk region 3 in SiC epitaxial layer 2 (e.g.) Figure 3 (as shown); for example, Al ion implantation is performed on SiC epitaxial layer 2, with an implantation energy of 500-800 KeV and an implantation dose of E13 atoms per square centimeter.
[0061] S3: Perform source injection on the body region 3 to form source 4 (e.g., Figure 4 As shown), for example, N+ implantation is performed on body region 3, with an implantation energy of 50-70 KeV and an implantation dose of E15 atoms per square centimeter.
[0062] S4: A gate trench 5 is formed within the body region 3 by etching. The bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2 (e.g., Figure 6 As shown, the inner wall of the gate trench 5 includes a first sidewall 19, a second sidewall 20, and a trench bottom. The first sidewall 19 of the gate trench 5 passes through the source electrode 4 or contacts the source electrode 4 to form a channel. In this embodiment, plasma dry etching can be used to form the gate trench 5. The width of the gate trench 5 is 2 μm and the depth is 1.5 μm.
[0063] S5: Deposit to form a first dielectric layer 6 and a second dielectric layer 7. The first dielectric layer 6 covers the first sidewall 19, the second sidewall 20, and the bottom of the gate trench 5. The second dielectric layer 7 fills the hollow area between the first sidewall 19 and the second sidewall 20 of the gate trench 5 (e.g., ...). Figures 7-11 (As shown).
[0064] S6: Remove part of the first dielectric layer 6 covering the first sidewall 19, and retain at least part of the first dielectric layer 6 covering the bottom of the gate trench 5, forming a vacant area (e.g., Figure 12 (As shown).
[0065] S7: Grow a gate oxide layer 9 (e.g., on the surface of the first sidewall 19 exposed in the vacant area) on the surface of the gate oxide layer 9. Figure 13 (as shown); the thickness of the gate oxide layer 9 can be 400-800 Å, and the gate oxide layer 9 can be grown isotropically using chemical vapor deposition.
[0066] S8: Fill the space between the gate oxide layer 9 and the second dielectric layer 7 to form the gate 8 (e.g., ...). Figure 14 (As shown).
[0067] By depositing a first dielectric layer 6 and a second dielectric layer 7 in the gate trench 5, and after removing part of the first dielectric layer 6 covering the first sidewall 19 while retaining at least a portion of the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, a gate oxide layer 9 is grown on the surface of the first sidewall 19 exposed in the vacant area. A filler is then filled between the gate oxide layer 9 and the second dielectric layer 7 to form the gate 8. This gate trench 5 filling method allows the remaining first dielectric layer 6 and the second dielectric layer 7 to form a thick oxide layer protecting the gate oxide layer 9, reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device. Furthermore, the thick oxide layer at the bottom and sidewalls of the gate trench 5 can significantly reduce the gate charge, optimizing the switching characteristics of the device. Moreover, the above-described gate trench 5 filling method does not require precise control of the depth of the body region 3 or strict control of the position of the gate 8 in the gate trench 5, simplifying the manufacturing process and reducing requirements for equipment and machinery, resulting in high manufacturability.
[0068] In this embodiment, after source implantation into the body region 3 and before forming the gate trench 5 by etching within the body region 3, the method further includes: performing P+ implantation into the body region 3 to form a P+ region 10 (e.g., ...). Figure 5(as shown); and, after filling the space between the gate oxide layer 9 and the second dielectric layer 7 with polysilicon, the method further includes: forming Nisalicide 11 on the corresponding surfaces of the source 4 and the P+ region 10 to obtain a source ohmic contact layer. Specifically, this process can be: depositing a 400 Å thick silicon oxide layer as a temporary protective layer 18, and forming openings (as shown) at the corresponding positions of the source 4 and the P+ region 10. Figure 15 As shown), a 1000 Å thick layer of metallic nickel (Ni) is deposited. After annealing at 400-500℃, excess Ni is removed from the silicon oxide (temporary protective layer 18) surface. Then, after annealing at 600-700℃, Nisalicide 11 is formed on the surface of the SiC epitaxial layer 2 at the corresponding positions of source 4 and P+ region 10. Figure 16 (As shown).
[0069] In this embodiment, after filling the space between the gate oxide layer 9 and the second dielectric layer 7 to form the gate electrode 8, the method further includes: forming a contact hole 12 on the surface of the source ohmic contact layer; specifically, the dielectric layer 14 can be formed after the ILD deposition process, and the contact hole 12 can be formed using a photolithography etching process; filling the contact hole 12 with metal to form the source electrode 13, for example, filling the contact hole 12 with tungsten metal using a W-plug process. Based on this, the surface metal 15 and the back metal 16 are assembled to finally form a... Figure 2 The trench-type SiC MOSFET device shown.
[0070] In this embodiment, the first dielectric layer 6 can be silicon oxide, and the second dielectric layer 7 can be silicon nitride. In step S5 above, the deposition to form the first dielectric layer 6 and the second dielectric layer 7 specifically includes the following:
[0071] First, deposit silicon dioxide (such as...) Figure 7 As shown), the thickness can be 7000 Å, so that silicon oxide covers the surface of the SiC epitaxial layer 2 and the sidewalls (first sidewall 19 and second sidewall 20) and bottom of the gate trench 5;
[0072] Next, silicon nitride is deposited on the surface of the silicon oxide, with a thickness of 6000 Å, so that the silicon nitride covers the surface of the silicon oxide and fills the remaining area of the gate trench 5 (e.g., Figure 8 (as shown);
[0073] Finally, the silicon nitride and silicon oxide outside the gate trench 5 are removed, while the silicon nitride and silicon oxide in the gate trench 5 are retained, so that the height of the silicon oxide and silicon nitride in the gate trench 5 is consistent with the height of the SiC epitaxial layer 2 (e.g., ...). Figure 9 Figure 11As shown in the figure, the silicon oxide in the gate trench 5 forms the first dielectric layer 6, and the silicon nitride in the gate trench 5 forms the second dielectric layer 7.
[0074] In this embodiment, the silicon nitride and silicon oxide in the area outside the gate trench 5 can be removed as follows: First, the silicon nitride on the top surface is removed using CMP or dry etching to expose the silicon oxide (e.g., Figure 9 (as shown), and remove the silicon nitride (e.g., silicon nitride protruding above the SiC epitaxial layer 2 in the gate trench 5). Figure 10 (as shown); secondly, CMP process is used to remove the silicon oxide protruding above the SiC epitaxial layer 2 (as shown). Figure 11 As shown in the figure. CMP (Chemical Mechanical Polishing) is a process that combines mechanical friction and chemical etching to flatten the surface of semiconductor materials. Compared with mechanical polishing, CMP can make the surface of semiconductor materials flatter, and it has lower processing costs and simpler processing methods.
[0075] In step S6 above, the first dielectric layer 6 covering the first sidewall 19 is removed, and at least a portion of the first dielectric layer 6 covering the bottom of the gate trench 5 is retained. This means that in the depth direction of the gate trench 5, only a portion of the first dielectric layer 6 covering the first sidewall 19 is removed, and the first dielectric layer 6 retained at the bottom of the gate trench 5 can be part or all of the first dielectric layer 6 covering the bottom of the gate trench 5. This allows for the retention of part or all of the first dielectric layer 6 at the bottom of the gate trench 5 while the gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5. In this embodiment, the first dielectric layer 6 covering the first sidewall 19 and at the same depth as the second dielectric layer 7 can be removed, that is, the first dielectric layer 6 between the first sidewall 19 and the second dielectric layer 7 is removed, so that this area forms a vacant area, and all of the first dielectric layer 6 at the bottom of the gate trench 5 is retained. In this embodiment, the process of removing part of the first dielectric layer 6 can be implemented as follows: Photoresist 17 is coated on the surface of the SiC epitaxial layer 2, and the photoresist 17 is patterned using a photolithography process to form a patterned photoresist 17; based on the patterned photoresist 17, a wet etch-back process is used to remove part of the first dielectric layer 6 covering the first sidewall 19, while retaining at least the first dielectric layer 6 covering the bottom of the gate trench 5 (e.g., ...). Figure 12 (As shown). It should be noted that when the silicon nitride (second dielectric layer 7) is partially removed from the first dielectric layer 6 covering the first sidewall 19, the first dielectric layer 6 covering the second sidewall 20 is exempt from removal.
[0076] In this embodiment, the filling between the gate oxide layer 9 and the second dielectric layer 7 in step S8 above to form the gate 8 can specifically refer to: depositing phosphorus-doped polysilicon with an implantation dose of 1E20 atoms per square centimeter, so that a polysilicon gate is formed in the region between the gate oxide layer 9 and the second dielectric layer 7, and removing the polysilicon on the surface of the SiC epitaxial layer 2.
[0077] Through the above process, the remaining first dielectric layer 6 and second dielectric layer 7 in the gate trench 5 can form a thick oxide layer to protect the gate oxide layer 9, reduce the electric field at the bottom of the gate trench 5, optimize the electric field distribution at the bottom of the gate trench 5 in the reverse cut-off state, and improve the reliability of the device; in addition, the thick oxide layer (the remaining first dielectric layer 6 and second dielectric layer 7) at the bottom and sidewalls of the gate trench 5 can significantly reduce the gate charge and optimize the switching characteristics of the device.
[0078] The trench-type SiC MOSFET device fabrication method provided in this embodiment involves growing a SiC epitaxial layer 2 on a SiC substrate 1; forming a body region 3 in the SiC epitaxial layer 2; performing source implantation on the body region 3 to form a source electrode 4; forming a gate trench 5 in the body region 3 by etching, with the bottom of the gate trench 5 located in the drift region of the SiC epitaxial layer 2, and the first sidewall 19 of the gate trench 5 passing through or contacting the source electrode 4; depositing a first dielectric layer 6 and a second dielectric layer 7, with the first dielectric layer 6 covering the first sidewall 19, the second sidewall 20, and the bottom of the gate trench 5, and the second dielectric layer 7 filling the hollow region between the first sidewall 19 and the second sidewall 20 of the gate trench 5; removing part of the first dielectric layer 6 covering the first sidewall 19, and retaining at least the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant region; growing a gate oxide layer 9 on the surface of the first sidewall 19 exposed in the vacant region; and filling the space between the gate oxide layer 9 and the second dielectric layer 7 to form a gate electrode 8. This method involves depositing a first dielectric layer 6 and a second dielectric layer 7 in a gate trench 5. After removing part of the first dielectric layer 6 covering the first sidewall 19 and retaining at least the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, a gate oxide layer 9 is grown on the surface of the first sidewall 19 exposed in the vacant area. A filler is then filled between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8. Through this gate trench 5 filling method, the remaining first dielectric layer 6 and the second dielectric layer 7 in the gate trench can form a thick oxide layer to protect the gate oxide layer 9, reduce the electric field at the bottom of the gate trench 5, optimize the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improve the reliability of the device. Furthermore, the thick oxide layer at the bottom and sidewall of the gate trench 5 (the remaining first dielectric layer 6 and the second dielectric layer 7 in the gate trench) can significantly reduce the gate charge and optimize the switching characteristics of the device. Furthermore, the above-mentioned gate trench 5 filling method does not require precise control of the depth of the body region 3, nor does it require strict control of the position of the gate 8 in the gate trench 5, which simplifies the manufacturing process and reduces the requirements for equipment and machines, thus having high manufacturability.
[0079] Another embodiment of this application provides a trench-type SiC MOSFET device structure, which is fabricated using the trench-type SiC MOSFET device fabrication method provided in the above embodiments. Figure 2 As shown, the trench-type SiC MOSFET device structure includes:
[0080] SiC epitaxial layer 2 is located on SiC substrate 1;
[0081] The body region 3 is located in the SiC epitaxial layer 2;
[0082] The source electrode 4 is located in the body region 3;
[0083] The gate trench 5 is located in the body region 3, the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2, and the first sidewall 19 of the gate trench 5 passes through the source electrode 4 or contacts the source electrode 4;
[0084] A gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5;
[0085] A first dielectric layer 6 covers the bottom of the gate trench 5 and the surface of the second sidewall 20;
[0086] A second dielectric layer 7 is filled within the gate trench 5 and is in contact with the first dielectric layer 6;
[0087] A gate 8 is filled within the gate trench 5 and located between the gate oxide layer 9 and the second dielectric layer 7.
[0088] In this embodiment, the above-mentioned trench SiC MOSFET device structure further includes: a P+ region 10 formed after P+ implantation into the body region 3; a source ohmic contact layer formed on the corresponding positions of the source electrode 4 and the P+ region 10; a contact hole 12 formed on the surface of the source ohmic contact layer; and a source electrode 13 filled in the contact hole 12.
[0089] The trench-type SiC MOSFET device structure provided in this embodiment has a gate oxide layer 9 grown on the first sidewall 19 of the gate trench 5; a first dielectric layer 6 covering the bottom of the gate trench 5 and the surface of the second sidewall 20; a second dielectric layer 7 filling the gate trench 5 and contacting the first dielectric layer 6; and a gate 8 filling the gate trench 5 and located between the gate oxide layer 9 and the second dielectric layer 7. This gate trench filling method allows the first dielectric layer 6 and the second dielectric layer 7 in the gate trench to form a thick oxide layer for protecting the gate oxide layer 9, reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device. Furthermore, the thick oxide layers (first dielectric layer 6 and second dielectric layer 7) at the bottom and sidewalls of the gate trench 5 can significantly reduce the gate charge and optimize the switching characteristics of the device.
[0090] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0091] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. A method for fabricating a trench-type SiC MOSFET device, characterized in that, The method includes: A SiC epitaxial layer is formed on a SiC substrate; In the SiC epitaxial layer forming body region; Source injection is performed on the aforementioned body region to form a source electrode; P+ injection is performed on the body region to form the P+ region; A gate trench is formed by etching within the body region. The bottom of the gate trench is located in the drift region of the SiC epitaxial layer. The first sidewall of the gate trench passes through the source electrode or contacts the source electrode. A first dielectric layer and a second dielectric layer are deposited sequentially. The first dielectric layer covers the first sidewall, the second sidewall, and the bottom of the gate trench, and the second dielectric layer fills the hollow area between the first sidewall and the second sidewall of the gate trench. Remove part of the first dielectric layer covering the first sidewall, and at least retain part of the first dielectric layer covering the bottom of the gate trench to form a vacant area; A gate oxide layer is grown on the surface of the first sidewall exposed in the vacant area; A filler is filled between the gate oxide layer and the second dielectric layer to form a gate; A source ohmic contact layer is formed on the corresponding positions of the source electrode and the P+ region. A contact hole is formed on the surface of the source ohmic contact layer. Metal is filled into the contact hole to form a source electrode. On this basis, the surface metal and the back metal are assembled to obtain the trench SiC MOSFET device.
2. The method according to claim 1, characterized in that, The deposition forms a first dielectric layer and a second dielectric layer, including: Silicon oxide is deposited so that it covers the surface of the SiC epitaxial layer and the sidewalls and bottom of the gate trench; Silicon nitride is deposited on the upper surface of the silicon oxide to fill the remaining area of the gate trench; Remove silicon nitride and silicon oxide from the area outside the gate trench, and retain silicon nitride and silicon oxide in the gate trench, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
3. The method according to claim 2, characterized in that, The removal of silicon nitride and silicon oxide outside the gate trench includes: The top silicon nitride is removed by CMP or dry etching, and the silicon nitride protruding above the SiC epitaxial layer in the gate trench is also removed. The silicon oxide protruding above the SiC epitaxial layer is removed using CMP.
4. The method according to claim 1, characterized in that, The removal of a portion of the first dielectric layer covering the first sidewall, while retaining at least the first dielectric layer covering the bottom of the gate trench, includes: Photoresist is coated on the surface of the SiC epitaxial layer, and the photoresist is patterned using a photolithography process to form a patterned photoresist. Based on the patterned photoresist, a wet etch-back process is used to remove part of the first dielectric layer covering the first sidewall, while at least the first dielectric layer covering the bottom of the gate trench is retained.
5. The method according to claim 1 or 4, characterized in that, The removal of a portion of the first dielectric layer covering the first sidewall, while retaining at least the first dielectric layer covering the bottom of the gate trench, includes: Remove the first dielectric layer that covers the first sidewall and has the same depth as the second dielectric layer.
6. The method according to claim 1, characterized in that, A gate is formed by filling the space between the gate oxide layer and the second dielectric layer with a filler, comprising: Polysilicon is deposited to form a polysilicon gate in the region between the gate oxide layer and the second dielectric layer, and the polysilicon on the surface of the SiC epitaxial layer is removed.
7. A trench-type SiC MOSFET device structure, characterized in that, The trench-type SiC MOSFET device structure includes: SiC epitaxial layer located on SiC substrate; The bulk region located in the SiC epitaxial layer; The source electrode is located in the body region; A gate trench located within the body region, the bottom of the gate trench being located in the drift region of the SiC epitaxial layer, and the first sidewall of the gate trench passing through or contacting the source electrode; A gate oxide layer grown on the first sidewall of the gate trench; A first dielectric layer covering the bottom of the gate trench and the surface of the second sidewall; A second dielectric layer is filled in the gate trench and is in contact with the first dielectric layer, the second dielectric layer being located on the upper surface of the first dielectric layer; A gate electrode that fills the gate trench and is located between the gate oxide layer and the second dielectric layer; The P+ region formed after P+ injection into the body region; Source ohmic contact layers are formed on the surfaces of the corresponding positions of the source electrode and the P+ region; The contact hole formed on the surface of the source ohmic contact layer and the source electrode filled in the contact hole, as well as the surface metal and the back metal.