A Micro-LED chip structure and preparation method thereof

Abstract

The present invention discloses a Micro-LED chip structure and a method for preparing the same. The method comprises: using a first etching process to etch an epitaxial wafer to remove a portion of the second nitride layer, a portion of the multi-quantum well light-emitting layer, and a portion of the first nitride layer on the epitaxial wafer, thereby forming an etched groove and multiple mesas, with the first nitride layer exposed in the etched groove; using a second etching process to perform a first repair treatment on quantum well damage on the sidewalls of the etched groove, thereby forming a sloped sidewall; and using a third etching process to perform a second repair treatment on quantum well damage on a portion of the sidewalls of the etched groove, thereby forming the sidewalls of the etched groove with at least two slopes. By repairing the damaged quantum wells twice, the adverse effects of the size effect of the Micro-LED are reduced, and the sloped wall reflection of the upper and lower layers can be additionally increased, thereby improving the quantum efficiency of the Micro-LED.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a Micro-LED chip structure and a preparation method thereof. Background Art

[0002] Micro-LED display technology uses self-luminous micron-sized LEDs as pixel units, assembled onto a driver panel to form a high-density LED array. Due to their small chip size, high integration, and self-luminescence, Micro-LEDs offer significant advantages over LCDs and OLEDs in terms of brightness, resolution, contrast, energy consumption, lifespan, response speed, and thermal stability.

[0003] However, Micro-LED units are relatively small. As the size of individual chips continues to shrink, the resulting size effect intensifies. This reduction in chip size reduces the light absorption area and increases the ratio of chip sidewall to chip surface area, thereby reducing light absorption efficiency and increasing dark current, thereby reducing sidewall recombination. During chip fabrication, quantum wells at the sidewall edges are lost, further exacerbating the size effect. Researching how to reduce ineffective quantum wells and increase the effective chip area is crucial for improving the quantum efficiency of Micro-LED displays. Summary of the Invention

[0004] The purpose of the present invention is to provide a Micro-LED chip structure and a preparation method thereof, which repairs the damaged quantum well through a two-step repair process, reduces the adverse effects of the size effect of the Micro-LED chip structure, and can also additionally increase the slope wall reflection of the upper and lower layers, thereby improving the internal quantum efficiency and external quantum efficiency of the Micro-LED chip structure.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] A method for preparing a Micro-LED chip structure, comprising:

[0007] An epitaxial wafer is etched using a first etching process, wherein the epitaxial wafer includes a growth substrate, a first nitride layer, a multi-quantum well light-emitting layer, and a second nitride layer stacked from bottom to top, and a portion of the second nitride layer, a portion of the multi-quantum well light-emitting layer, and a portion of the first nitride layer on the epitaxial wafer are removed to form an etched groove and a plurality of mesas, wherein the first nitride layer is exposed at the etched groove;

[0008] Performing a first repair process on the quantum well damage on the sidewall of the etched groove by using a second etching process, so that the sidewall of the etched groove forms a slope;

[0009] A third etching process is used to perform a second repair process on the quantum well damage on a portion of the sidewalls of the etched groove, so that the sidewalls of the etched groove include at least two inclined surfaces.

[0010] Preferably, after the second repair process, the sidewall of the etched groove is V-shaped, and the tip of the V-shaped etched groove is located on the multi-quantum well light-emitting layer.

[0011] Preferably, the first etching process is a dry etching process;

[0012] The second etching process is a dry etching process or a wet etching process. When the second etching process is a dry etching process, the etching power of the second etching process is less than the etching power of the first etching process.

[0013] The third etching process is a wet etching process.

[0014] Preferably, in the first etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 280-520 sccm, the Cl2 gas flow rate is 12-28 sccm, and the etching power is 200-300 W;

[0015] When the second etching process is a dry etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 70-130 sccm, the Cl2 gas flow rate is 3-7 sccm, and the etching power is 17-23 W;

[0016] When the second etching process is a wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220° C., and the etching time is 10-20 minutes;

[0017] In the third etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220° C., and the etching time is 10-20 minutes.

[0018] Preferably, after the first repair process, the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, or a trapezoidal groove structure that is wide at the top and narrow at the bottom;

[0019] When the second etching process uses a dry etching process to perform a first repair treatment, so that the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the second etching process includes: first forming a thermal expansion layer on the upper surface of the mesa, then forming a patterned second mask layer on the thermal expansion layer and at the bottom of the etched groove, heating the epitaxial wafer so that a portion of the second mask layer on the mesa near the edge of the etched groove is warped upward, using a dry etching process to repair quantum well damage on the sidewall of the etched groove, and then removing the thermal expansion layer and the second mask layer;

[0020] When the second etching process uses a wet etching process to perform the first repair treatment, so that the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the second etching process includes: first forming a patterned second mask layer on the upper surface of the mesa and the bottom of the etched groove, the second mask layer covering the upper surface of the mesa and extending to the edge of the mesa, using a wet etching process to repair quantum well damage on the sidewall of the etched groove, so that the sidewall of the etched groove forms a trapezoidal groove structure that is narrow at the top and wide at the bottom, and then removing the second mask layer;

[0021] When the second etching process uses a wet etching process to perform the first repair treatment, so that the etching groove has a trapezoidal groove structure that is wide at the top and narrow at the bottom, the second etching process includes: first forming a patterned second mask layer on the upper surface of the table and the bottom of the etching groove, the second mask layer covers the upper surface of the table and does not extend to the edge of the table, using a wet etching process to repair the quantum well damage on the side wall of the etching groove, the side wall of the etching groove forms an inclined structure, and then removing the second mask layer.

[0022] Preferably, when the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the third etching process includes: first forming a patterned third mask layer on the upper surface of the mesa, the bottom of the etched groove, and the lower half of the sidewall of the etched groove, wherein the third mask layer covers the upper surface of the mesa but does not extend to the edge of the mesa; repairing quantum well damage on the sidewall of the etched groove by a wet etching process so that the sidewall of the etched groove includes at least two inclined surfaces; and then removing the third mask layer;

[0023] When the etched groove has a trapezoidal groove structure that is wide at the top and narrow at the bottom, the third etching process includes: first forming a patterned third mask layer on the upper surface of the mesa, the bottom of the etched groove and the upper half of the side wall of the etched groove, the third mask layer covers the upper surface of the mesa and extends to the edge of the mesa, and using a wet etching process to repair the quantum well damage on the side wall of the etched groove so that the side wall of the etched groove includes at least two inclined surfaces, and then removing the third mask layer.

[0024] Preferably, when the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the first etching process includes: removing part of the second nitride layer, part of the multi-quantum well light-emitting layer, and part of the first nitride layer on the epitaxial wafer to form an etched groove and multiple mesas, wherein the growth substrate is exposed at the etched groove; the third etching process includes: forming a first bonding metal layer on the mesas, providing a transfer substrate, on which a second bonding metal layer is provided, inverting the transfer substrate and bonding it to the epitaxial wafer so that the first bonding metal layer and the second bonding metal layer are fused into a third bonding metal layer, removing the growth substrate, and then forming a patterned third mask layer on the upper surface of the mesas, the bottom of the etched groove, and the upper half of the sidewalls of the etched groove, the third mask layer covering the upper surface of the mesas and extending to the edges of the mesas, repairing quantum well damage on the sidewalls of the etched groove using a wet etching process so that the sidewalls of the etched groove include at least two inclined surfaces, and then removing the third mask layer;

[0025] When the etched groove has a trapezoidal groove structure that is wider at the top and narrower at the bottom, the first etching process includes: removing part of the second nitride layer, part of the multi-quantum well light-emitting layer, and part of the first nitride layer on the epitaxial wafer to form an etched groove and multiple mesas, with the growth substrate exposed at the etched groove; the third etching process includes: forming a first bonding metal layer on the mesas, providing a transfer substrate, on which a second bonding metal layer is provided, inverting the transfer substrate and bonding it to the epitaxial wafer so that the first bonding metal layer and the second bonding metal layer are fused into a third bonding metal layer, removing the growth substrate, and then forming a patterned third mask layer on the upper surface of the mesas, the bottom of the etched groove, and the lower half of the sidewalls of the etched groove, wherein the third mask layer covers the upper surface of the mesas and does not extend to the edge of the mesas, using a wet etching process to repair quantum well damage on the sidewalls of the etched groove so that the sidewalls of the etched groove include at least two inclined surfaces, and then removing the third mask layer.

[0026] Preferably, the thermal expansion layer is a Ni layer, and the temperature for heating the epitaxial wafer is 352-362°C.

[0027] Preferably, the preparation method also includes: forming a second electrode electrically connected to the second nitride layer on the table, and forming a first electrode electrically connected to the first nitride layer at the bottom of the etched groove; after forming the second electrode and the first electrode, forming a passivation layer, the passivation layer covering the upper surface of the table not covered by the second electrode, the partial surface of the second electrode, the sidewalls of the etched groove, the first nitride layer at the bottom of the etched groove not covered by the first electrode, and the partial surface of the first electrode.

[0028] Preferably, a roughening layer is formed on the passivation layer, and the root mean square roughness of the roughening layer is 15-20 nm.

[0029] Preferably, the epitaxial wafer further comprises: a buffer layer and a current spreading layer, wherein the buffer layer is located between the growth substrate and the first nitride layer, and the current spreading layer is located on the second nitride layer;

[0030] When the first nitride layer is an N-type nitride layer, the second nitride layer is a P-type nitride layer; when the first nitride layer is a P-type nitride layer, the second nitride layer is an N-type nitride layer.

[0031] A Micro-LED chip structure is obtained by any of the preparation methods described above.

[0032] Compared with the prior art, the beneficial effects of the present invention include at least:

[0033] The quantum well damage on the side wall of the etched groove is repaired through two repair processes, and the damaged quantum well is removed. The side wall of the etched groove forms at least two inclined planes and protrudes toward the etched groove, which is conducive to the formation of a passivation layer. It can also increase the upper and lower two layers of slope wall reflection to enhance the light output efficiency of the vertical surface of the Micro-LED chip structure, thereby reducing the adverse effects of the size effect of the Micro-LED chip structure and improving the internal quantum efficiency and external quantum efficiency of the Micro-LED chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a flow chart of a method for preparing a Micro-LED chip structure according to an embodiment of the present invention.

[0035] Figures 2a to 2g 2 is a schematic diagram of the cross-sectional structure of the Micro-LED chip structure in each step of Example 1 of the present invention.

[0036] Figure 3 This is a schematic diagram of the partial cross-sectional structure of an epitaxial wafer after heating in step S102 according to embodiment 3 of the present invention.

[0037] Figure 4 Schematic diagram of the formation of dangling bonds by breaking Ga and N in a multi-quantum well layer according to an embodiment of the present invention.

[0038] Figure 5 1 is a schematic diagram of a linear expansion coefficient curve of nickel according to an embodiment of the present invention.

[0039] Figure 6 2 is a schematic diagram of the cross-sectional structure of the Micro-LED chip structure in each step of Example 2 of the present invention.

[0040] Figures 7a to 7c 2 is a schematic diagram of the cross-sectional structure of the Micro-LED chip structure in each step of Example 3 of the present invention.

[0041] Figures 8a to 8h 2 is a schematic diagram of the cross-sectional structure of the Micro-LED chip structure in step by step according to Example 4 of the present invention.

[0042] In the figure: 100, epitaxial wafer; 101a, growth substrate; 101b, transfer substrate; 102, buffer layer; 103, first nitride layer; 104, multi-quantum well light-emitting layer; 105, second nitride layer; 106, etched groove; 107, current spreading layer; 108, first electrode; 109, second electrode; 110, thermal expansion layer; 111, passivation layer; 112, insulating layer; 113, protective layer; 114, roughening layer; 115, first bonding metal layer; 116, second bonding metal layer; 117, third bonding metal layer; 118, second mask layer; 119, third mask layer. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the drawings represent identical or similar structures, and thus repeated descriptions thereof will be omitted.

[0044] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but can be modified as needed, and all such modifications are within the scope of protection of the present invention.

[0045] Example 1:

[0046] Reference Figure 1 and Figures 2a-2g The method for preparing a Micro-LED chip structure provided by the present invention includes steps S101-S103.

[0047] Step S101: etching the epitaxial wafer using a first etching process to form an etched groove 106 and a plurality of mesas.

[0048] Specifically, refer to Figure 2a Epitaxial wafer 100 includes a growth substrate 101a, a first nitride layer 103, a multi-quantum well light-emitting layer 104, and a second nitride layer 105, stacked sequentially from bottom to top. When first nitride layer 103 is an N-type layer, second nitride layer 105 is a P-type layer; when first nitride layer 103 is a P-type layer, second nitride layer 105 is an N-type layer. The N-type layer is an N-type nitride layer, preferably an N-type gallium nitride layer, and the P-type layer is a P-type nitride layer, preferably a P-type gallium nitride layer.

[0049] In a specific embodiment, the growth substrate 101a can be made of materials such as sapphire, silicon, gallium nitride, or silicon carbide. In this embodiment, the growth substrate 101a is preferably sapphire. The first nitride layer 103 is located on the growth substrate 101a, the multi-quantum well light-emitting layer 104 is located on the first nitride layer 103, and the second nitride layer 105 is located on the multi-quantum well light-emitting layer 104. The multi-quantum well light-emitting layer 104 is preferably made of a gallium nitride system and is used for carrier recombination and light emission.

[0050] like Figure 2bAs shown, step S101 may specifically include: forming a photoresist layer on the surface of the epitaxial wafer 100, exposing and developing the photoresist layer to form a patterned first mask layer (not shown), the photoresist adopts positive photoresist or negative photoresist; etching the epitaxial wafer 100 using a first etching process to remove part of the second nitride layer 105, part of the multi-quantum well light-emitting layer 104 and part of the first nitride layer 103 on the epitaxial wafer 100, forming an etched groove 106 and a plurality of mesas, exposing the first nitride layer 103 at the etched groove 106, wherein the thickness of the first nitride layer 103 can be approximately etched by half. The first etching process is a dry etching process, and a high-power dry etching process can be used to increase the etching rate. As a preferred method, the etching gases in the dry etching process are BCl3 and Cl2, with a BCl3 gas flow rate of 280-520 sccm, a Cl2 gas flow rate of 12-28 sccm, and an etching power of 200-300 W. As an example, the BCl3 gas flow rate is 300 sccm, the Cl2 gas flow rate is 15 sccm, and the etching power is 200 W. Then, a developer is used to remove the remaining first mask layer, and the residual glue is removed by O2 plasma. The process is then ultrasonically cleaned with an ethanol solution to obtain multiple mesas. Each mesa includes a first nitride layer 103, a multi-quantum well light-emitting layer 104, and a second nitride layer 105 stacked from bottom to top. Each mesa can correspond to a Micro-LED chip structural unit. The number of mesas can be set according to actual needs, and the size of each mesa and the spacing between adjacent mesas can also be set according to actual needs.

[0051] Step S102: a second etching process is used to perform a first repair process on the quantum well damage on a portion of the sidewalls of the etched groove 106 , so that the sidewalls of the etched groove 106 are formed into a slope.

[0052] Specifically, if Figure 4 As shown, the damaged quantum well is, for example, the Ga and N in the multi-quantum well light-emitting layer 104 on the sidewall of the etched groove 106 are broken during the process of forming the etched groove 106, forming bonding damage, resulting in the appearance of dangling bonds. First, a thermal expansion layer 110 is formed on the upper surface of the mesa after the first mask layer is removed. The thermal expansion layer 110 can be formed by deposition. The thickness of the thermal expansion layer 110 is 30-80nm. The thermal expansion layer 110 can expand when heated. Then, a second mask layer 118 is formed on the thermal expansion layer 110 and the bottom of the etched groove 106. The second mask layer 118 covers the thermal expansion layer 110 and the bottom of the etched groove 106. Figure 3As shown, the epitaxial wafer 100 is then heated to cause a portion of the second mask layer 118 on the mesa near the edge of the etched groove 106 to warp upward. After the warping, the warping height of the portion of the second mask layer 118 can gradually decrease from the edge of the etched groove 106 toward the center line of the mesa. The thermal expansion layer 110 is made of a material that is more easily expanded than the second mask layer 118 and other layers after being heated. The temperature of the heated epitaxial wafer 100 is related to the material of the thermal expansion layer 110. After the portion of the second mask layer 118 is warped upward, a second etching process is then used to repair the quantum well damage on the sidewall of the etched groove 106, as shown in FIG. Figure 2c As shown, a portion of the second nitride layer 105, a portion of the multi-quantum well light-emitting layer 104, and the first nitride layer 103 on the epitaxial wafer 100 are removed, thereby removing the damaged quantum wells. Because the etching power of the second etching process is lower than that of the first etching process, it can not only effectively remove the quantum well damage caused by the first etching process, but also prevent secondary quantum well damage from occurring on the sidewalls of the etched grooves 106. In addition, the second etching process uses low-power dry etching to stably and effectively etch a regular crystal surface morphology, overcoming the defect of poor uniformity caused by anisotropic etching of the crystal during wet etching, and avoiding drastic changes in the etching morphology of the tiny core particles that affect the overall luminous efficiency of the tiny chip. As a preferred method, in the second etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 70-130sccm, the Cl2 gas flow rate is 3-7sccm, and the etching power is 17-23W. As an example, the BCl3 gas flow rate is 100sccm, the Cl2 gas flow rate is 5sccm, and the etching power is 20W.

[0053] like Figure 3 As shown, because the portion of the second mask layer 118 near the edge of the etched groove 106 is tilted upward, the plasma during the second etching process can etch obliquely in the direction of the arrow, forming a trapezoidal groove structure with a narrow top and a wide bottom. The sidewalls of the etched groove 106 also form a sloped shape. The sloped sidewalls of the etched groove 106 enhance the light extraction efficiency of light reflected from the sidewalls and entering the vertical surface, effectively improving the quantum efficiency of the Micro-LED chip structure.

[0054] As a preferred embodiment, the thermal expansion layer 110 is a nickel layer (Ni layer), the temperature of the heated epitaxial wafer 100 is 352-362° C. Nickel is a ferromagnetic metal, such as Figure 5As shown in the linear expansion coefficient curve of nickel, when the temperature rises to near the Curie point (Tc), a ferromagnetic-paramagnetic transition occurs. At this time, the thermal expansion coefficient will show obvious anomalies, that is, a λ-shaped expansion peak appears with the apex at Tc. The experimental value of the Curie point Tc of nickel is in the range of 352-362°C. By using a pure nickel layer as the thermal expansion layer 110 and setting the temperature of the heated epitaxial wafer 100 to 352-362°C, the thermal expansion layer 110 can be rapidly heated and expanded at this relatively low temperature, thereby causing the portion of the second mask layer 118 on the table near the edge of the etched groove 106 to warp upward. In addition, the above heating temperature is relatively low and will not affect the Micro-LED chip.

[0055] Then, the thermal expansion layer 110 is dissolved by wet etching or dry etching, and the remaining second mask layer 118 is removed by a developer. The residual glue is removed by O2 plasma, and ultrasonic cleaning is performed with an ethanol solution.

[0056] Step S103 : performing a second repair process on the quantum well damage on a portion of the sidewall of the etched groove 106 by using a third etching process, so that the sidewall of the etched groove 106 includes at least two inclined surfaces.

[0057] Step S103 may specifically include: Figure 2d As shown, a photoresist layer is formed on the surface of the epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned third mask layer 119. The third mask layer 119 covers part of the upper surface of the mesa, the bottom of the etched groove 106, and the lower half of the sidewall of the etched groove 106. The third mask layer 119 covers the upper surface of the mesa but does not extend to the edge of the mesa, that is, the third mask layer 119 does not completely cover the mesa, and the third mask layer 119 is not covered at the four sides of the mesa. A third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106. The third etching process is a wet etching process, such as Figure 2e As shown, a wet etching process is used to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum wells on the sidewalls of the etched groove 106. The sidewalls of the etched groove 106 can also include at least two inclined surfaces. For example, the sidewalls of the etched groove 106 form a V-shape and protrude toward the etched groove 106. The V-shape means that the longitudinal cross-section of the sidewalls of the etched groove 106 along the thickness direction of the Micro-LED chip structure is V-shaped. The tip of the V-shape is preferably located on the multi-quantum well light-emitting layer 104, which is beneficial to improving the uniformity of light emission.

[0058] A two-step repair process is used to repair the sidewalls of tiny chips. The two-step repair process can better eliminate invalid quantum wells, and can also add two additional layers of sloped wall reflection on the upper and lower layers to enhance the light extraction efficiency of the vertical surface of the tiny core particles. The two-step repair process can more perfectly repair the damage to the sidewalls of tiny core particles, bringing the light extraction efficiency of the Micro-LED chip structure to a new level. As a preferred method, in the wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220°C, and the etching time is 10-20 minutes. As an example, the etching temperature is 200°C and the etching time is 15 minutes.

[0059] Afterwards, the remaining third mask layer 119 is removed using a developer, and the residual adhesive is removed using O2 plasma, followed by ultrasonic cleaning using an ethanol solution.

[0060] As a preferred embodiment, a second electrode 109 electrically connected to the second nitride layer 105 is formed on the mesa, and a first electrode 108 electrically connected to the first nitride layer 103 is formed at the bottom of the etched groove 106 .

[0061] Specifically, if Figure 2f As shown, a second electrode 109 is formed on the second nitride layer 105 by electron beam evaporation, plasma sputtering, or thermal evaporation, and a first electrode 108 is formed on the first nitride layer 103 at the bottom of the etched groove 106. The second electrode 109 and the first electrode 108 are used for bonding wires. As a preferred embodiment, the second electrode 109 and the first electrode 108 include an ohmic contact layer, a reflective layer, an adhesive transition layer and a welding layer stacked in sequence. The ohmic contact layer is a Cr layer with a thickness of 50-100 nm. The Cr layer serves to improve the ohmic contact between the electrode and the N-type GaN layer or the P-type GaN layer. The reflective layer is an Al layer with a thickness of 50-100 nm. The adhesive transition layer is a Ti layer, a Ni layer and a Pt layer arranged in sequence from bottom to top. The thickness of the Ti layer, the Ni layer and the Pt layer are respectively 10-50 nm. The adhesive transition layer ensures that the entire electrode structure has better adhesion to prevent the second electrode 109 and the first electrode 108 from falling off the epitaxial wafer 100. The thickness of the Au layer is 1500-2500 nm and the Au layer is used for welding. It should be noted that the first electrode 108 and the second electrode 109 may be formed before or after step S102 , and the first electrode 108 and the second electrode 109 may be formed before or after step S103 .

[0062] As a preferred method, after forming the second electrode 109 and the first electrode 108, a passivation layer 111 is formed on the epitaxial wafer 100, and the passivation layer 111 covers the upper surface of the table not covered by the second electrode 109, part of the surface of the second electrode 109, the side walls of the etched groove 106, the bottom of the etched groove 106 not covered by the first electrode 108, and part of the surface of the first electrode 108.

[0063] Specifically, a passivation layer 111 is formed on the epitaxial wafer 100. The passivation layer 111 can be deposited by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). In this embodiment, atomic layer deposition (ALD) is preferably used. The passivation layer 111 includes an insulating layer 112 and a protective layer 113 stacked in sequence. The protective layer 113 covers a portion of the insulating layer 112. The insulating layer 112 is a silicon nitride layer or a silicon oxide layer. The protective layer 113 includes a Cr layer, an Al layer and an Au layer stacked in sequence. The insulating layer 112 separates the protective layer 113 from the second electrode 109 and the first electrode 108, thereby preventing the protective layer 113 from connecting the second electrode 109 and the first electrode 108 and causing a short circuit. The insulating layer 112 can also separate the protective layer 113 from the second nitride layer 105 and the first nitride layer 103. The Cr layer of the protective layer 113 can improve the adhesion between the Al layer and the insulating layer 112, preventing the insulating layer 112 and the protective layer 113 from peeling off. The Al layer can reflect the light reflected back by the Micro-LED chip again, thereby improving the luminous efficiency of the Micro-LED chip structure. The Au layer has better coating and oxidation resistance, which can better protect the micro-light-emitting diode structure, and is beneficial to improving the reliability and thermal stability of the Micro-LED chip structure tube.

[0064] As a preferred method, a roughening layer 114 is formed on the passivation layer 111 by laser irradiation, and the root mean square roughness of the surface after surface roughening is 15-20 nm. Since the refractive index of Au is generally 1.35 and the refractive index of air is 1.0, in this pair of media, Au is a light-dense medium and air is a light-sparse medium. According to Snel1's law, a portion of light with an incident angle less than the critical angle θ can be emitted into the air, but light with an incident angle greater than θ will undergo total internal reflection when it is incident on the interface. This results in the presence of many large-angle light rays in the light emitted by the micro-LED, and these light rays will not be emitted into the air due to the total internal reflection phenomenon, resulting in a decrease in the luminous efficiency of the micro-LED. Surface roughening can greatly reduce the occurrence of total reflection, thereby improving luminous efficiency.

[0065] As a preferred method, Figure 2gAs shown, the epitaxial wafer 100 in step S101 further includes a buffer layer 102 and a current spreading layer 107. The buffer layer 102 is located between the growth substrate 101a and the first nitride layer 103. The buffer layer 102 improves the lattice matching and crystal quality between the first nitride layer 103 and the growth substrate 101a. The buffer layer 102 may be an aluminum nitride layer. The current spreading layer 107 is located on the second nitride layer 105 and may be formed on the second nitride layer 105 using electron beam evaporation, plasma sputtering, or thermal evaporation. The current spreading layer 107 may be a single metal layer, multiple metal layers, or an indium tin oxide (ITO) layer. The current spreading layer 107 is preferably a nickel / gold alloy, an aluminum-based metal, or indium tin oxide (ITO). Preferably, an ITO layer is used for the current spreading layer 107, as the ITO layer has excellent electrical conductivity and light transmittance, which is beneficial to the optoelectronic performance of the chip. When the current spreading layer 107 is provided, the second electrode 109 is formed on the current spreading layer 107 .

[0066] Finally, the epitaxial wafer 100 is cut by laser or mechanical means, and then tested and sorted to obtain the Micro-LED chip structure unit. The cutting can be done by known methods, which will not be described in detail here.

[0067] Example 2:

[0068] Reference Figures 2a-2g and Figure 6 The method for preparing the Micro-LED chip structure provided by the present invention includes steps S201-S203.

[0069] The difference between Example 2 and Example 1 is that step S202 of Example 2 is different from step S102 of Example 1.

[0070] The difference between step S202 and step S102 of embodiment 1 is that a photoresist layer is first formed on the surface of the epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned second mask layer 118, such as Figure 6 As shown, the second mask layer 118 covers the upper surface of the mesa and the bottom of the etched groove 106. The second mask layer 118 covers the upper surface of the mesa and extends to the edge of the mesa. Then, a second etching process is used to repair the quantum well damage on the sidewall of the etched groove 106. The second etching process is a wet etching process to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum well on the sidewall of the etched groove 106. And, as shown in FIG. Figure 2cAs shown, because the second mask layer 118 covers the top surface of the mesa and extends to the edge of the mesa, the wet etching process forms a trapezoidal groove structure in the etched groove 106, which is narrow at the top and wide at the bottom. The sidewalls of the etched groove 106 are sloped, enhancing the efficiency of light reflected from the sidewalls into the vertical surface, effectively improving the quantum efficiency of the Micro-LED chip structure. As a preferred embodiment, the wet etching process uses a mixed solution of phosphoric acid and sulfuric acid, with an etching temperature of 180-220°C and an etching time of 10-20 minutes. As an example, the etching temperature is 200°C and the etching time is 15 minutes.

[0071] Example 3:

[0072] Reference Figures 2a-2g and Figures 7a-7c The method for preparing the Micro-LED chip structure provided by the present invention includes steps S301-S303.

[0073] The difference between Example 3 and Example 1 is that step S302 of Example 3 is different from step S102 of Example 1, and step S303 of Example 3 is different from step S103 of Example 1.

[0074] The difference between step S302 of embodiment 3 and step S102 of embodiment 1 is that a photoresist layer is first formed on the surface of the epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned second mask layer 118, such as Figure 7a As shown, the second mask layer 118 covers part of the upper surface of the mesa and the bottom of the etched groove 106. The second mask layer 118 covers the upper surface of the mesa but does not extend to the edge of the mesa. In other words, the second mask layer 118 does not completely cover the mesa, and the second mask layer 118 is not covered on the periphery of the mesa. Then, a second etching is performed to repair the quantum well damage on the sidewall of the etched groove 106. The second etching process is a wet etching process to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum well on the sidewall of the etched groove 106. And, as shown in FIG. Figure 7b As shown, because the second mask layer 118 covers the upper surface of the mesa but does not extend to the edge of the mesa, the wet etching process forms a trapezoidal groove structure in the etched groove 106, which is wide at the top and narrow at the bottom. The sidewalls of the etched groove 106 are sloped, enhancing the efficiency of light reflected from the sidewalls into the vertical surface, effectively improving the quantum efficiency of the Micro-LED chip structure. As a preferred embodiment, the wet etching process uses a mixed solution of phosphoric acid and sulfuric acid, with an etching temperature of 180-220°C and an etching time of 10-20 minutes. As an example, the etching temperature is 200°C and the etching time is 15 minutes.

[0075] The difference between step S303 of embodiment 3 and step S103 of embodiment 1 is that Figure 7c As shown, a photoresist layer is formed on the surface of the epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned third mask layer 119. The third mask layer 119 covers the upper surface of the mesa, the bottom of the etched groove 106, and the upper half of the sidewall of the etched groove 106. The third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa. A third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106. The third etching process is a wet etching process, such as Figure 2f As shown, a wet etching process is used to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum wells on the sidewalls of the etched groove 106. In addition, the sidewalls of the etched groove 106 include at least two inclined surfaces. For example, the sidewalls of the etched groove 106 form a V-shape and protrude toward the etched groove 106. The V-shape means that the longitudinal cross-section of the sidewalls of the etched groove 106 along the thickness direction of the Micro-LED chip structure is V-shaped.

[0076] Example 4:

[0077] Reference Figures 2a-2g and Figures 8a-8h The method for preparing the Micro-LED chip structure provided by the present invention includes steps S401-S403.

[0078] Step S401: etching the epitaxial wafer using a first etching process to form an etched groove 106 and a plurality of mesas.

[0079] The difference between step S401 and step S101 in embodiment 1 is that Figure 8a As shown, the first etching process includes: removing part of the second nitride layer 105, part of the multi-quantum well light-emitting layer 104 and part of the first nitride layer 103 on the epitaxial wafer 100 to form an etched groove 106 and multiple mesas, and the growth substrate 101a is exposed at the etched groove 106.

[0080] Step S402: a second etching process is used to perform a first repair process on the quantum well damage on a portion of the sidewall of the etched groove 106, so that the sidewall of the etched groove 106 forms a slope.

[0081] The second etching process in step S402 can be a dry etching process or a wet etching process. Step S402 can be the same as or similar to step S102 in embodiment 1, or the same as or similar to step S202 in embodiment 2, or the same as or similar to step S302 in embodiment 3, and will not be described in detail here.

[0082] Step S403: performing a second repair process on the quantum well damage on a portion of the sidewall of the etched groove 106 using a third etching process, so that the sidewall of the etched groove 106 includes at least two inclined surfaces.

[0083] When step S402 is the same as or similar to step S102 in embodiment 1, or the same as or similar to step S202 in embodiment 2, step S403 is different from step S103 in embodiment 1 in that: Figures 8b-8e As shown, a first bonding metal layer 115 is formed on the mesa, a transfer substrate 101b is provided, and a second bonding metal layer 116 is arranged on the transfer substrate 101b. The transfer substrate 101b is inverted and bonded to the epitaxial wafer 100, so that the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the growth substrate 101a is removed. Then, a patterned third mask layer 119 is formed on the upper surface of the mesa, the bottom of the etching groove 106 and the upper half of the side wall of the etching groove 106. The third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa. A third etching process is used to repair the quantum well damage on the side wall of the etching groove 106, so that the side wall of the etching groove 106 includes at least two inclined surfaces, and then the third mask layer 119 is removed.

[0084] Specifically, a first bonding metal layer 115 is formed on the second nitride layer 105 by evaporation. The first bonding metal layer 115 can be one or more of Au, Ti, Sn, Ni, and Mn, preferably a titanium-gold alloy. A transfer substrate 101b is provided. The transfer substrate 101b is made of a material with good light transmittance. The transfer substrate 101b can be made of sapphire, silicon, gallium nitride, etc. In this embodiment, the transfer substrate 101b is preferably sapphire. A second bonding metal layer 116 is deposited on the transfer substrate 101b by electron beam evaporation, plasma sputtering, or thermal evaporation. The second bonding metal layer 116 can be one or more of Au, Ti, Sn, Mn, and Ni, preferably a titanium-gold alloy. The second bonding metal layer 116 and the first bonding metal layer 115 are preferably made of the same material. The transfer substrate 101b is inverted and bonded to the epitaxial wafer 100, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into the third bonding metal layer 117, and the substrate 101a is removed. Figure 8c As shown, the transfer substrate 101b on which the second bonding metal layer 116 is deposited is inverted and bonded to the epitaxial wafer 100 on which the first bonding metal layer 115 is deposited using a bonding device with an alignment function. The first bonding metal layer 115 and the second bonding metal layer 116 are coated with BCB bonding glue, as shown in FIG. Figure 8dAs shown, under a high temperature and high pressure environment, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the Micro-LED chip structure uses a laser lift-off device to remove the substrate 101a.

[0085] A photoresist layer is formed on the surface of the bonded epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned third mask layer 119. The third mask layer 119 covers the upper surface of the mesa, the bottom of the etching groove 106, and the upper half of the sidewall of the etching groove 106. The third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa. The specific structure is the same as Figure 7c The third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106. The third etching process is a wet etching process, such as Figure 8e As shown, a wet etching process is used to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum wells on the sidewalls of the etched groove 106. In addition, the sidewalls of the etched groove 106 include at least two inclined surfaces. For example, the sidewalls of the etched groove 106 form a V-shape and protrude toward the etched groove 106. The V-shape means that the longitudinal cross-section of the sidewalls of the etched groove 106 along the thickness direction of the Micro-LED chip structure is V-shaped.

[0086] When step S402 is the same as or similar to step S302 in embodiment 3, step S403 is different from step S303 in embodiment 3 in that: Figure 8b and Figure 8g As shown, a first bonding metal layer 115 is formed on the mesa, a transfer substrate 101b is provided, and a second bonding metal layer 116 is arranged on the transfer substrate 101b. The transfer substrate 101b is inverted and bonded to the epitaxial wafer 100, so that the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the growth substrate 101a is removed. Then, a patterned third mask layer 119 is formed on the upper surface of the mesa, the bottom of the etched groove 106 and the lower half of the sidewall of the etched groove 106. The third mask layer 119 covers the upper surface of the mesa and does not extend to the edge of the mesa. A third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106, so that the sidewall of the etched groove 106 includes at least two inclined surfaces, and then the third mask layer 119 is removed.

[0087] Specifically, a first bonding metal layer 115 is formed on the second nitride layer 105 by evaporation. The first bonding metal layer 115 can be one or more of Au, Ti, Sn, Ni, and Mn, preferably a titanium-gold alloy. A transfer substrate 101b is provided. The transfer substrate 101b is made of a material with good light transmittance. The transfer substrate 101b can be made of sapphire, silicon, gallium nitride, etc. In this embodiment, the transfer substrate 101b is preferably sapphire. A second bonding metal layer 116 is deposited on the transfer substrate 101b by electron beam evaporation, plasma sputtering, or thermal evaporation. The second bonding metal layer 116 can be one or more of Au, Ti, Sn, Mn, and Ni, preferably a titanium-gold alloy. The second bonding metal layer 116 and the first bonding metal layer 115 are preferably made of the same material. The transfer substrate 101b is inverted and bonded to the epitaxial wafer 100, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into the third bonding metal layer 117, and the substrate 101a is removed. Figure 8g As shown, the transfer substrate 101b on which the second bonding metal layer 116 is deposited is inverted and bonded to the epitaxial wafer 100 on which the first bonding metal layer 115 is deposited using a bonding device with an alignment function. The first bonding metal layer 115 and the second bonding metal layer 116 are coated with BCB bonding glue, as shown in FIG. Figure 8h As shown, under a high temperature and high pressure environment, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the Micro-LED chip structure uses a laser lift-off device to remove the substrate 101a.

[0088] A photoresist layer is formed on the surface of the bonded epitaxial wafer 100, and the photoresist layer is exposed and developed to form a patterned third mask layer 119. The third mask layer 119 covers the upper surface of the mesa, the bottom of the etching groove 106, and the lower half of the sidewall of the etching groove 106. The third mask layer 119 covers the upper surface of the mesa and does not extend to the edge of the mesa. The specific structure is the same as that of the third mask layer 119. Figure 2d The third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106. The third etching process is a wet etching process, such as Figure 8e As shown, a wet etching process is used to remove part of the second nitride layer 105 and part of the multi-quantum well light-emitting layer 104 on the epitaxial wafer 100, and remove the damaged quantum wells on the sidewalls of the etched groove 106. In addition, the sidewalls of the etched groove 106 include at least two inclined surfaces. For example, the sidewalls of the etched groove 106 form a V-shape or an arch and protrude toward the etched groove 106. The V-shape means that the longitudinal cross-section of the sidewalls of the etched groove 106 along the thickness direction of the Micro-LED chip structure is V-shaped.

[0089] As a preferred embodiment, a second electrode 109 electrically connected to the second nitride layer 105 is formed on the mesa, and a first electrode 108 electrically connected to the first nitride layer 103 is formed at the bottom of the etched groove 106 .

[0090] Specifically, if Figure 8f As shown, a first electrode 108 is formed on the first nitride layer 103 by electron beam evaporation, plasma sputtering, or thermal evaporation, and a second electrode 109 is formed on the second bonding metal layer 116 at the bottom of the etched groove 106. The second electrode 109 and the first electrode 108 are used for bonding wires. Preferably, the second electrode 109 and the first electrode 108 include an ohmic contact layer, a reflective layer, an adhesive transition layer, and a soldering layer stacked in sequence. The ohmic contact layer is a Cr layer with a thickness of 50-100 nm, which improves the ohmic contact between the electrode and the N-type GaN layer or the P-type GaN layer. The reflective layer is an Al layer with a thickness of 50-100 nm. The adhesive transition layers are Ti, Ni, and Pt layers arranged in sequence from bottom to top, with the thickness of each Ti, Ni, and Pt layer being 10-50 nm. The adhesive transition layers ensure better adhesion of the entire electrode structure and prevent the second electrode 109 and the first electrode 108 from falling off the epitaxial wafer 100. The Au layer has a thickness of 1500-2500 nm and is used for soldering. It should be noted that the first electrode 108 and the second electrode 109 can be formed before or after step S403.

[0091] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes shall fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a Micro-LED chip structure, characterized in that: include: An epitaxial wafer is etched using a first etching process, wherein the epitaxial wafer includes a growth substrate, a first nitride layer, a multi-quantum well light-emitting layer, and a second nitride layer stacked from bottom to top, and a portion of the second nitride layer, a portion of the multi-quantum well light-emitting layer, and a portion of the first nitride layer on the epitaxial wafer are removed to form an etched groove and a plurality of mesas, wherein the first nitride layer is exposed at the etched groove; The first etching process is a dry etching process; A second etching process is used to perform a first repair treatment on the quantum well damage on the sidewall of the etched groove, wherein the sidewall of the etched groove is formed into a slope and the etched groove is formed into a trapezoidal groove structure; the second etching process is a dry etching process or a wet etching process, and when the second etching process is a dry etching process, the etching power of the second etching process is less than the etching power of the first etching process; A third etching process is used to perform a second repair treatment on the quantum well damage on part of the sidewall of the etched groove, so that the sidewall of the etched groove includes at least two inclined surfaces and the sidewall of the etched groove is V-shaped; the third etching process is a wet etching process.

2. The method for preparing a Micro-LED chip structure according to claim 1, wherein: The V-shaped tip of the etched groove is located on the multi-quantum well light-emitting layer.

3. The method for preparing a Micro-LED chip structure according to claim 1, wherein: In the first etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 280-520 sccm, the Cl2 gas flow rate is 12-28 sccm, and the etching power is 200-300 W; When the second etching process is a dry etching process, the etching gases are BCl3 and Cl2, the BCl3 gas flow rate is 70-130 sccm, the Cl2 gas flow rate is 3-7 sccm, and the etching power is 17-23 W; When the second etching process is a wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220° C., and the etching time is 10-20 minutes; In the third etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220° C., and the etching time is 10-20 minutes.

4. The method for preparing a Micro-LED chip structure according to claim 1, wherein: After the first repair process, the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, or a trapezoidal groove structure that is wide at the top and narrow at the bottom; When the second etching process uses a dry etching process to perform a first repair treatment, so that the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the second etching process includes: first forming a thermal expansion layer on the upper surface of the mesa, then forming a patterned second mask layer on the thermal expansion layer and at the bottom of the etched groove, heating the epitaxial wafer so that a portion of the second mask layer on the mesa near the edge of the etched groove is warped upward, using a dry etching process to repair quantum well damage on the sidewall of the etched groove, and then removing the thermal expansion layer and the second mask layer; When the second etching process uses a wet etching process to perform the first repair treatment, so that the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the second etching process includes: first forming a patterned second mask layer on the upper surface of the mesa and the bottom of the etched groove, the second mask layer covering the upper surface of the mesa and extending to the edge of the mesa, using a wet etching process to repair quantum well damage on the sidewall of the etched groove, so that the sidewall of the etched groove forms a trapezoidal groove structure that is narrow at the top and wide at the bottom, and then removing the second mask layer; When the second etching process uses a wet etching process to perform the first repair treatment, so that the etching groove has a trapezoidal groove structure that is wide at the top and narrow at the bottom, the second etching process includes: first forming a patterned second mask layer on the upper surface of the table and the bottom of the etching groove, the second mask layer covers the upper surface of the table and does not extend to the edge of the table, using a wet etching process to repair the quantum well damage on the side wall of the etching groove, the side wall of the etching groove forms an inclined structure, and then removing the second mask layer.

5. The method for preparing a Micro-LED chip structure according to claim 4, wherein: When the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the third etching process includes: first forming a patterned third mask layer on the upper surface of the mesa, the bottom of the etched groove, and the lower half of the sidewall of the etched groove, wherein the third mask layer covers the upper surface of the mesa but does not extend to the edge of the mesa; using a wet etching process to repair quantum well damage on the sidewall of the etched groove so that the sidewall of the etched groove includes at least two inclined surfaces; and then removing the third mask layer; When the etched groove has a trapezoidal groove structure that is wide at the top and narrow at the bottom, the third etching process includes: first forming a patterned third mask layer on the upper surface of the mesa, the bottom of the etched groove and the upper half of the side wall of the etched groove, the third mask layer covers the upper surface of the mesa and extends to the edge of the mesa, and using a wet etching process to repair the quantum well damage on the side wall of the etched groove so that the side wall of the etched groove includes at least two inclined surfaces, and then removing the third mask layer.

6. The method for preparing a Micro-LED chip structure according to claim 4, wherein: When the etched groove has a trapezoidal groove structure that is narrow at the top and wide at the bottom, the first etching process includes: removing a portion of the second nitride layer, a portion of the multi-quantum well light-emitting layer, and a portion of the first nitride layer on the epitaxial wafer to form an etched groove and a plurality of mesas, wherein the growth substrate is exposed at the etched groove; the third etching process includes: forming a first bonding metal layer on the mesas, providing a transfer substrate, on which a second bonding metal layer is provided, inverting the transfer substrate and bonding it to the epitaxial wafer so that the first bonding metal layer and the second bonding metal layer are fused into a third bonding metal layer, removing the growth substrate, and then forming a patterned third mask layer on the upper surface of the mesas, the bottom of the etched groove, and the upper half of the sidewalls of the etched groove, the third mask layer covering the upper surface of the mesas and extending to the edges of the mesas, repairing quantum well damage on the sidewalls of the etched groove using a wet etching process so that the sidewalls of the etched groove include at least two inclined surfaces, and then removing the third mask layer; When the etched groove has a trapezoidal groove structure that is wider at the top and narrower at the bottom, the first etching process includes: removing part of the second nitride layer, part of the multi-quantum well light-emitting layer, and part of the first nitride layer on the epitaxial wafer to form an etched groove and multiple mesas, with the growth substrate exposed at the etched groove; the third etching process includes: forming a first bonding metal layer on the mesas, providing a transfer substrate, on which a second bonding metal layer is provided, inverting the transfer substrate and bonding it to the epitaxial wafer so that the first bonding metal layer and the second bonding metal layer are fused into a third bonding metal layer, removing the growth substrate, and then forming a patterned third mask layer on the upper surface of the mesas, the bottom of the etched groove, and the lower half of the sidewalls of the etched groove, wherein the third mask layer covers the upper surface of the mesas and does not extend to the edge of the mesas, using a wet etching process to repair quantum well damage on the sidewalls of the etched groove so that the sidewalls of the etched groove include at least two inclined surfaces, and then removing the third mask layer.

7. The method for preparing a Micro-LED chip structure according to claim 4, wherein: The thermal expansion layer is a Ni layer, and the temperature of heating the epitaxial wafer is 352-362°C.

8. The method for preparing a Micro-LED chip structure according to claim 1, wherein: The preparation method also includes: forming a second electrode electrically connected to the second nitride layer on the table, and forming a first electrode electrically connected to the first nitride layer at the bottom of the etched groove; after forming the second electrode and the first electrode, forming a passivation layer, the passivation layer covering the upper surface of the table not covered by the second electrode, a portion of the surface of the second electrode, the sidewalls of the etched groove, the first nitride layer at the bottom of the etched groove not covered by the first electrode, and a portion of the surface of the first electrode.

9. The method for preparing a Micro-LED chip structure according to claim 8, wherein: A roughening layer is formed on the passivation layer, and the root mean square roughness of the roughening layer is 15-20 nm.

10. The method for preparing a Micro-LED chip structure according to claim 1, wherein: The epitaxial wafer further includes: a buffer layer and a current spreading layer, wherein the buffer layer is located between the growth substrate and the first nitride layer, and the current spreading layer is located on the second nitride layer; When the first nitride layer is an N-type nitride layer, the second nitride layer is a P-type nitride layer; when the first nitride layer is a P-type nitride layer, the second nitride layer is an N-type nitride layer.

11. A Micro-LED chip structure, characterized in that: Obtained according to the preparation method according to any one of claims 1 to 10.

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