A micro-power clock calibration method and circuit for a passive chip

Abstract

The present invention provides a micro-power consumption clock calibration method and circuit for a passive chip. An ultra-low power consumption temperature sensor is added to the chip. After air interface calibration is completed at the factory, the temperature sensor detects temperature changes when the chip is in use. A digital calibration circuit then generates a compensation logic sequence based on the temperature quantization value, adjusts the charge and discharge currents, and performs secondary compensation on the clock frequency, so that the frequency is stabilized within a smaller tolerance range. This allows the generation of a micro-power consumption, high-precision, temperature-invariant clock signal. Through the calibration method of the present invention, the internal clock of the chip only needs to be calibrated once before it leaves the factory, reducing the necessary processes and workload during the actual use and testing of the chip, and resulting in low application costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of passive Internet of Things ultra-low power consumption node chips, and in particular relates to a micro-power consumption clock calibration method and circuit for a passive chip. Background Art

[0002] With the development of wireless network communication technology, data technology, sensor technology and artificial intelligence technology, the Internet of Things technology is developing towards the passive Internet of Things. With its characteristics of micro power consumption, self-powered, low cost and small area, the passive Internet of Things has become a hot technology.

[0003] When upgrading from active IoT to passive IoT, the bottleneck problem to be solved is the passivity of terminal nodes. Wireless energy harvesting technology is used to collect wireless energy from the surrounding environment to provide working power for the chip; at the same time, communication data is transmitted wirelessly. Therefore, the passive IoT can realize "energy-carrying communication" or "simultaneous transmission of data and energy", which greatly reduces the cost, volume and power consumption of the terminal, and increases the breadth of the node's application scenarios and the amount of data on the node.

[0004] During the implementation process, the passive Internet of Things requires that the passive node chip support micro-power consumption, low cost, high integration and clock accuracy can meet the requirements of communication protocol parameters. The digital baseband in the chip contains a protocol processing module. The clock signal required for normal operation is provided by the chip's internal integrated clock under micro-power self-powered conditions, rather than by a crystal oscillator outside the chip. The chip's internal clock is affected by different production batches, temperature, etc., and the provided clock frequency has a large offset, which cannot meet the passive node chip's micro-power consumption and high-precision requirements during communication, especially the communication requirements of current commercial network relays such as BLE and WiFi.

[0005] To address the large frequency deviations in internal chip clocks, various high-precision clock generation methods and circuits have been proposed. These methods can be categorized into two main categories. The first method uses an external, precise clock as a reference to calibrate the internal clock. This calibrated internal clock then provides the high-precision clock required by the digital circuits. The second method improves the internal chip clock structure and employs positive and negative temperature coefficient compensation to reduce the resulting frequency errors, thereby improving clock frequency accuracy.

[0006] The first clock calibration method requires an external precise clock signal as a reference. Only after the internal clock of the chip is calibrated can the internal clock of the chip meet the high-precision requirements. Before each use and test of the internal clock of the chip, an off-chip real-time calibration method must be used to offset the frequency deviation caused by temperature and production process. This increases the necessary procedures and workload during the actual use and testing of the chip, and the application cost is high. In addition, to calibrate the internal clock of the chip through this calibration method, the chip must have an interface compatible with the commercial air interface protocol. For passive node chips that do not have such an interface, the clock cannot be calibrated through this calibration method. In summary, the existing clock calibration technology solutions cannot be widely used in the field of highly integrated, low-cost passive Internet of Things.

[0007] The second clock calibration method improves the on-chip clock structure and usually adopts the positive and negative temperature coefficient compensation method. However, the structure is relatively complex, and the positive and negative temperature coefficients are nonlinear, making it difficult to achieve relatively accurate offset compensation over the full temperature range or long temperature range. Therefore, the temperature compensation effect is limited, and the process deviation is large, which will also reduce the compensation accuracy. In addition, this method based on positive and negative temperature coefficient compensation is relatively energy-inefficient. It is usually applicable to clock frequencies in the KHz range and can have low power consumption. Once the clock frequency increases, the power consumption usually increases significantly in a linear relationship with the frequency. When the frequency reaches the MHz range, the power consumption can increase by several orders of magnitude. It is difficult to apply to passive chip applications with high clock frequency (above several MHz) and power consumption (sub-microwatt), such as passive RFID and new passive BLE, passive WIFI, or other on-chip clock source applications with certain communication rate requirements. Summary of the Invention

[0008] In order to solve the above problems existing in the prior art, the present invention provides a passive chip micro-power clock calibration method and circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0009] The present invention provides a micro-power consumption clock calibration method for a passive chip, which is applied to the passive chip. The passive chip includes an RC oscillator circuit, a memory circuit, and a digital calibration circuit. The method is characterized in that a temperature sensor is integrated inside the passive chip. The method includes:

[0010] During the air interface calibration phase,

[0011] The digital calibration circuit is configured to generate a calibration logic sequence and send it to the RC oscillator circuit, thereby controlling some transistors of the current branch of the RC oscillator circuit to turn off or on to implement air interface calibration, and save the calibration logic sequence in the memory circuit;

[0012] The temperature sensor is used to detect the internal temperature of the passive chip and store the internal temperature in the memory circuit;

[0013] During the use phase,

[0014] The memory circuit is configured to send the internal temperature stored during the air interface calibration phase and the calibration logic sequence to the digital calibration circuit;

[0015] The temperature sensor is used to detect the internal temperature of the passive chip and transmit the internal temperature to the digital calibration circuit;

[0016] The digital calibration circuit is configured to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence based on the internal temperature difference obtained by the subtraction, and send the compensation logic sequence and the calibration logic sequence to the RC oscillator circuit;

[0017] The RC oscillator circuit is used to control the transistor of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, thereby compensating for the impact of temperature changes on the internal clock frequency of the passive chip by controlling the current size of the current branch.

[0018] Optionally, the digital calibration circuit is configured to generate a calibration logic sequence and send it to the RC oscillator circuit, thereby controlling some transistors in the current branch of the RC oscillator circuit to turn off or on to achieve air interface calibration, and saving the calibration logic sequence in the memory circuit includes:

[0019] The digital calibration circuit is used to receive an external clock transmitted through the air interface, use each clock cycle of the external clock as a reference cycle, count the rising edges of the clock generated by the RC oscillator circuit within the reference cycle, subtract the count result from a preset logical value, count the positive difference values ​​obtained by the difference, accumulate the positive difference values ​​in each reference cycle, generate the RC oscillator circuit, and control the switching on or off of some transistors in its own current branch according to the calibration logic sequence.

[0020] Optionally, the temperature sensor output is respectively connected to the memory circuit input and the digital calibration circuit input, the output of the memory circuit is connected to the input of the digital calibration circuit, and the output of the digital calibration circuit is connected to the input of the memory and the input of the RC oscillator circuit.

[0021] Optionally, the RC oscillator circuit includes a current branch and an RS trigger, and the current branch includes a plurality of transistors and a charge-discharge capacitor;

[0022] The RC oscillator circuit is configured to control the transistors of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, so as to compensate for the effect of temperature changes on the internal clock frequency of the passive chip by controlling the current of the current branch. The method includes:

[0023] The RC oscillator circuit is used to control the transistor of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, so as to charge or discharge the charging and discharging capacitor, thereby changing the current size of the current branch, thereby compensating for the impact of temperature changes on the internal clock frequency of the passive chip.

[0024] Optionally, the digital calibration circuit subtracts the internal temperature P1 stored in the internal memory from the internal temperature P2 directly transmitted by the temperature sensor to obtain an internal temperature difference ΔP;

[0025] The relationship between the internal temperature difference ΔP and the current change ΔI of the branch circuit in the RC oscillator circuit is:

[0026]

[0027] in, C is the capacitance of the equivalent capacitor in the RC oscillator circuit, V is twice the RC oscillator flip voltage, and f is the internal clock frequency of the passive chip.

[0028] Optionally, the digital calibration circuit includes: a counter 1, a counter 2, a subtractor, and an adder.

[0029] During the air interface calibration phase,

[0030] The counter 1 is configured to receive an external clock transmitted via an air interface, use each clock cycle of the external clock as a reference cycle, and count rising edges of the clock generated by the RC oscillator circuit within the reference cycle;

[0031] The logic unit is used to calculate the difference between the counting result of the counter 1 and a preset logic value;

[0032] The counter 2 is used to count the positive difference values ​​obtained by subtracting the value from the counter 1;

[0033] The adder is used to accumulate the positive difference value of each reference cycle to generate a calibration logic sequence;

[0034] During the use phase,

[0035] The subtractor is used to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence according to the internal temperature difference obtained by the subtraction, and send the compensation logic sequence to the RC oscillator circuit.

[0036] The present invention provides a passive chip micro-power consumption clock calibration circuit, which is calibrated using the passive chip micro-power consumption clock calibration method.

[0037] 1. The present invention provides a micro-power clock calibration method and circuit for a passive chip. By incorporating an ultra-low-power temperature sensor into the chip, after factory-qualified air interfaces, the temperature sensor detects temperature changes when the chip is in use. A digital calibration circuit then generates a compensation logic sequence based on the quantized temperature value, adjusts the charge and discharge currents, and performs secondary compensation on the clock frequency, stabilizing the frequency within a narrow tolerance range. This generates a micro-power, high-precision, temperature-invariant clock signal. The calibration method of the present invention only requires a single chip internal clock calibration, reducing the necessary procedures and workload during actual chip use and testing, resulting in low application costs.

[0038] 2. Compared with existing technical solutions, in which the clock frequency is usually in the KHz range, once the clock frequency increases, the power consumption will increase significantly, and it is impossible to achieve high energy efficiency in the MHz range. The calibration and generation of the micro-power, high-precision clock of the present invention are all implemented by the analog front-end circuit inside the chip, without involving the digital baseband circuit. The entire implementation scheme is simple, the circuit energy efficiency is high, the clock frequency can reach the MHz level, and the overall power consumption is at the sub-microwatt level.

[0039] 3. The calibration method of the present invention adopts temperature compensation. The chip's internal clock only needs to be initialized and calibrated once after the chip is packaged. This avoids the use of interfaces that must be compatible with commercial air interfaces. Therefore, it can be widely used in highly integrated, low-cost passive IoT chips. In addition, when the chip is used and tested, the frequency is compensated twice by the temperature compensation module. It is not necessary to calibrate the chip with an external precise clock as a reference every time the chip is used and tested. This reduces the necessary processes and workload during the actual use and testing of the chip, and the application cost is low.

[0040] 4. The method of calibrating the internal clock of a chip according to the present invention does not require any external components and has high integration. It uses the original RC oscillator inside the chip, does not need to change the original internal structure of the chip, and simplifies the clock structure. Moreover, the RC oscillator has a high energy efficiency ratio when using the calibration method of the present invention, so the cost of the chip itself and the system application cost are low.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 An internal schematic diagram of a passive chip used in a micro-power consumption clock calibration method for a passive chip provided by the present invention;

[0043] Figure 2 A schematic diagram of a process for calibrating a micro-power clock of a passive chip provided by the present invention;

[0044] Figure 3 1 is a schematic structural diagram of an RC oscillator circuit according to an embodiment of the present invention;

[0045] Figure 4 This is a block diagram of the digital calibration circuit architecture according to an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the temperature sensor structure according to an embodiment of the present invention;

[0047] Figure 6 This is a simulation diagram of the effect of temperature on clock frequency according to an embodiment of the present invention;

[0048] Figure 7 This is a diagram showing the expected effects of an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0050] The present invention provides a micro-power consumption clock calibration method for a passive chip, which is applied to a passive chip, wherein a temperature sensor is integrated inside the passive chip. Figure 1 The passive chip includes an RC oscillator circuit, a memory circuit, and a digital calibration circuit. The digital calibration circuit includes: Counter 1, a logic unit, Counter 2, a subtractor, and an adder. The temperature sensor output is connected to the memory circuit input and the digital calibration circuit input, respectively. The memory circuit output is connected to the digital calibration circuit input, and the digital calibration circuit output is connected to the memory input and the RC oscillator circuit input. The RC oscillator circuit includes a current branch and an RS trigger. The current branch includes multiple transistors and charge and discharge capacitors.

[0051] It is worth noting that the temperature sensor integrated inside the passive chip of the present invention is a low-power temperature sensor, and its power consumption is below the microwatt level.

[0052] refer to Figure 2 The present invention provides a method for calibrating a micro-power clock of a passive chip, comprising:

[0053] During the air interface calibration phase,

[0054] The digital calibration circuit is configured to generate a calibration logic sequence and send it to the RC oscillator circuit, control some transistors of the current branch of the RC oscillator circuit to turn off or on to implement air interface calibration, and save the calibration logic sequence in the memory circuit;

[0055] Furthermore, the digital calibration circuit is used to receive an external clock transmitted through the air interface, use each clock cycle of the external clock as a reference cycle, count the rising edges of the clock generated by the RC oscillator circuit within the reference cycle, and subtract the counting result from a preset logical value, and count the positive difference values ​​obtained by the difference, accumulate the positive difference values ​​of each reference cycle, and generate the RC oscillator circuit, which is used to control the switching on or off of some transistors of its own current branch according to the calibration logic sequence.

[0056] After the chip is packaged, when the logic calibration (air interface calibration) begins, the internal clock of the chip is initialized. At this time, the clock frequency is the largest. Then the chip uses an external precise clock as the reference period for the frequency calibration process of the internal RC oscillator clock circuit. In each calibration cycle, the counter 1 in the digital calibration circuit samples and counts the rising edge of the clock, and compares the sampled value with the subsequent logic value K. When the sampled value is greater than K, counter 2 starts counting. The count value is used as a digital signal to control the shutdown of the current branch, thereby generating a new clock frequency, and the cycle ends; in the next calibration cycle, the above process is repeated, except that the value counted by counter 2 is added to the previous count value of counter 2 through the adder circuit and acts together on the current branch for control until the count value sampled by counter 1 is equal to the logic value K, and an enable signal is output to save the calibrated calibration logic sequence and the temperature P1 during calibration to the memory circuit, and the calibration process is completed.

[0057] Furthermore, during the air interface calibration phase,

[0058] The counter 1 is configured to receive an external clock transmitted via an air interface, use each clock cycle of the external clock as a reference cycle, and count rising edges of the clock generated by the RC oscillator circuit within the reference cycle;

[0059] The logic unit is used to calculate the difference between the counting result of the counter 1 and a preset logic value;

[0060] It is worth noting that the logic unit is composed of AND, OR, and NOT gates, etc., and is used to form a logic value K. When the count value of counter 1 is greater than K, counter 2 starts counting.

[0061] The counter 2 is used to count the positive difference values ​​obtained by subtracting the value from the counter 1;

[0062] The adder is used to accumulate the positive difference value of each reference cycle to generate a calibration logic sequence;

[0063] It is worth noting that the adder is used to sample and count the rising edges of the clock within a fixed period and output a corresponding logic sequence N0, N1, ..., NN for signal processing or controlling the switch current.

[0064] It is worth noting that: in the air interface calibration stage, a one-way calibration method is adopted, that is, initially all the current branches in the RC oscillator clock circuit inside the chip are turned on, and the clock frequency reaches the highest value; an external precision clock provides a precise clock signal, which serves as a fixed period U for the counter 1 in the digital calibration circuit to work and count; counter 1 counts the rising edges of the internal RC oscillator clock output frequency signal within the period U, and when the count value is greater than K, counter 2 starts counting within the same period U, and the count output value is used as a control signal to turn off some current branches, thereby reducing the clock frequency, and the first period U ends; when the second period U comes, the counter Counter 1 continues to detect the rising edge of the clock signal after the first calibration. When the count value is greater than the logical value K, counter 2 starts counting. The count output value is added to the previous output value through the adder, and together they shut down some current branches, further reducing the clock frequency. When the third, fourth, and so on cycle U arrives, the above process is repeated until the count value of counter 1 equals K. An enable signal is output to shut down the digital calibration clock circuit. At the same time, the logic sequence generated by the digital calibration circuit and the chip temperature signal P1 collected by the temperature sensor are stored in the memory circuit. The calibration process ends, and the clock deviation caused by the process is calibrated.

[0065] The temperature sensor is used to detect the internal temperature of the passive chip and store the internal temperature in the memory circuit;

[0066] During the use phase,

[0067] The memory circuit is configured to send the internal temperature stored during the air interface calibration phase and the calibration logic sequence to the digital calibration circuit;

[0068] It is worth noting that: after the frequency of the RC oscillator clock circuit in the chip is calibrated by the digital calibration circuit using the external precise clock connected to the chip at the factory, that is, after the air interface calibration phase is completed, the memory saves the digital signal P1 output by the temperature sensor after quantization and the logic sequence generated by the first calibration of the digital calibration circuit; when the chip is actually used and tested, the internal temperature P1 and logic sequence saved in the air interface calibration phase are sent to the digital calibration circuit for processing.

[0069] The temperature sensor is used to detect the internal temperature of the passive chip and transmit the internal temperature to the digital calibration circuit;

[0070] It is worth noting that the temperature sensor circuit includes a forward-biased diode structure connected to a PNP transistor, two ring oscillators, a frequency divider circuit and a counter. The PNP voltage Vbe and the reference voltage Vref are respectively used as inputs of the two ring oscillators as comparison voltages to charge and discharge the capacitor through the ring oscillator to generate periodic signals T1 and T2. The periodic signal T1 is 2 n After the frequency is divided by multiples, an enable signal EN is generated. The enable signal EN is used as the control signal of the counter, and n represents the number of frequency division bits. The periodic signal T2 serves as the clock signal of the counter. Finally, the obtained frequency signal is quantized into a digital signal P as the output.

[0071] The digital calibration circuit is configured to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence based on the internal temperature difference obtained by the subtraction, and send the compensation logic sequence and the calibration logic sequence to the RC oscillator circuit;

[0072] The digital calibration circuit calculates the difference between the internal temperature P1 stored in the internal memory and the internal temperature P2 directly transmitted by the temperature sensor to obtain the internal temperature difference ΔP;

[0073] The relationship between the internal temperature difference ΔP and the current change ΔI of the branch circuit in the RC oscillator circuit is:

[0074]

[0075] in, C is the capacitance of the equivalent capacitor in the RC oscillator circuit, V is twice the RC oscillator flip voltage, and f is the internal clock frequency of the passive chip.

[0076] Furthermore, during the use phase,

[0077] The subtractor is used to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence according to the internal temperature difference obtained by the subtraction, and send the compensation logic sequence to the RC oscillator circuit.

[0078] It is worth noting that when the chip is in use, the digital signal P2 quantized by the temperature sensor is subtracted from the digital signal P1 stored in the memory circuit to generate ΔP.

[0079] The RC oscillator circuit is used to control the transistor of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, thereby compensating for the impact of temperature changes on the internal clock frequency of the passive chip by controlling the current size of the current branch.

[0080] The RC oscillator circuit charges or discharges the charge-discharge capacitor, thereby changing the current magnitude of the current branch, thereby compensating for the effect of temperature change on the internal clock frequency of the passive chip.

[0081] Among them, the current branches are 1, 2, ..., 2 n Its on and off is directly controlled by the multi-bit logic sequence of the digital calibration circuit.

[0082] It is worth noting that: when the chip is actually used and tested, the temperature sensor inside the circuit automatically detects the temperature and quantifies it to generate a temperature quantization signal P2, and then sends P2 to the digital calibration circuit. The memory circuit simultaneously sends the calibration logic sequence and temperature P1 of the logic calibration stage to the digital calibration circuit. The subtractor in the digital calibration circuit performs subtraction calculation on P1 and P2 to generate and output a temperature difference signal ΔP (ΔP = P2-P1). When ΔP is positive, it indicates that the temperature has risen, and the control turns off part of the compensation logic array, and the clock frequency decreases; when ΔP is negative, it indicates that the temperature has dropped, and the control turns on part of the compensation logic array, and the clock frequency increases, so that the frequency reaches the frequency error range of the previous calibration, and the frequency compensation process is completed. After a logic calibration, this method uses the internal temperature sensor of the chip to detect temperature changes and feedback signal compensation to adjust the current size during actual use and testing of the chip, thereby reducing the frequency error and compensating for the impact of temperature on the internal clock output frequency of the calibrated chip. At the same time, there is no need to calibrate the chip with an external precise clock every time it is used and tested, which reduces the necessary processes and workload during the actual use and testing of the chip, and significantly reduces the application cost and system cost.

[0083] refer to Figure 3 , which is used to continuously charge and discharge capacitors C1 and C2 through an adjustable current branch, and at the same time feed back to the switch to control oscillation through the RS trigger, so as to generate a clock cycle. The output frequency is inversely proportional to the capacitance value (C1=C2) and the comparator flip-flop voltage, and is proportional to the charging current. The purpose of adjusting the clock frequency can be achieved by adjusting the current size of the current branch.

[0084] Example 1:

[0085] Digital calibration circuit, reference Figure 4 The system consists of two parts: a digital calibration unit and a digital compensation unit. The digital calibration unit connects the crystal oscillator and the RC oscillator to process the frequency offset, ultimately achieving the effect of calibrating the clock frequency. The digital compensation unit, composed of a subtractor, analyzes and processes the temperature difference, generates a compensation logic sequence, and adjusts the current branch in the RC oscillator to achieve the purpose of frequency compensation.

[0086] Temperature sensor, reference Figure 5, used to connect the memory circuit and the digital calibration circuit, detect the chip temperature during calibration and the chip temperature when the chip is actually in use, and then save the temperature information to the memory circuit and send it to the digital calibration circuit for frequency temperature compensation.

[0087] The memory circuit is used to connect the temperature sensor and the digital calibration circuit, save the calibrated calibration logic sequence and the temperature information during calibration, and send them to the digital calibration circuit for use or processing when the chip is used.

[0088] The following analysis shows the expected effect of secondary temperature compensation and the minimum current relationship corresponding to a one-bit compensation logic array:

[0089] First, we systematically analyze the impact of temperature on the clock frequency caused by the REF, LDO and other internal chip modules together with the RC oscillator:

[0090] according to Figure 6 As shown by the ab line segment in the middle, the relationship curve between the clock frequency value and the temperature shows that the influence of temperature on the clock frequency to be compensated is close to a proportional linear relationship, so the first-order linear compensation method can be used. The temperature quadratic compensation mentioned in this solution is a compensation method based on the first-order linear coupling. The sampling relationship of the temperature sensor to the temperature is as follows: Figure 6 As shown by the CD line segment in the middle, the frequency and temperature are highly linearly correlated. Therefore, the clock offset caused by temperature can be compensated to within the error tolerance range through temperature detection. This shows that this method can compensate for the impact of temperature changes on the internal clock frequency of the chip after logic calibration. The system will also introduce nonlinear calibration errors, and the error value is much less than 0.5%.

[0091] The idealized slope is

[0092]

[0093] Depend on

[0094]

[0095] have to

[0096]

[0097] Where C is the capacitance of the equivalent capacitor in the RC oscillator circuit, and V is twice the RC oscillator flip voltage, which is slightly smaller than the clock oscillator voltage VDD.

[0098] Depend on

[0099]

[0100] have to

[0101]

[0102] Substituting equations (1-1) and (1-3) into equation (1-5), we get

[0103]

[0104] That is, when designing a clock frequency deviation that is adjusted to compensate for temperature changes, the ratio of ΔP to ΔI may be considered with reference to the following relationship.

[0105]

[0106] With reference to Example 1, Example 2 further illustrates the implementation process of the temperature compensation portion.

[0107] like Figure 7 As shown, the frequency calibration of the clock is performed at T1°C (point A), and after calibration, the calibration logic sequence and temperature (T1=20°C) at this time are saved in the memory circuit.

[0108] When the chip is in use:

[0109] In case 1, the temperature reaches T2°C (T2 = 80°C) (point C). The temperature sensor sends the current temperature T2 to the digital calibration circuit. At the same time, the memory circuit sends the calibration logic sequence and temperature T1 to the digital calibration circuit. The subtractor in the digital calibration circuit processes T1 and T2 to generate ΔT (ΔT = T2 - T1). Based on the value of ΔT and using equation (1-7) as a reference, a compensation logic sequence is generated to reduce the current charging and discharging the capacitor, so that the frequency reaches point E from point C.

[0110] In the second case, the temperature reaches T3°C (T3=0°C) (point C). The temperature sensor sends the current temperature T3 to the digital calibration circuit. At the same time, the memory circuit sends the calibration logic sequence and temperature T1 to the digital calibration circuit. The subtractor in the digital calibration circuit processes T1 and T3 to generate ΔT (ΔT=T3-T1). Based on the value of ΔT and with equation (1-7) as a reference, a compensation logic sequence is generated to reduce the current charging and discharging the capacitor, so that the frequency reaches point D from point B.

[0111] Case 3: The temperature is exactly T1°C, the frequency during calibration. At this time, ΔT is 0 and the frequency remains unchanged.

[0112] The above three situations can be divided into frequency deviation, frequency deviation and frequency unchanged, and the working process and method are explained at the same time, such as Figure 7 As shown, the conversion from curve BAC to curve DAE fully demonstrates the frequency compensation effect that can be expected. Figure 7The two dotted lines are the upper and lower limits of the allowable deviation after frequency compensation. The frequency error within the limits is ±0.5%)

[0113] The present invention adds a temperature sensor to the chip to compensate the internal clock frequency based on the linear relationship between temperature and frequency, and temperature and current. The temperature compensation process, i.e., the use phase process, is as follows:

[0114] After starting work, the temperature sensor detects the chip temperature and sends the collected temperature signal P2 to the digital calibration circuit. At the same time, the memory circuit sends the temperature signal P1 and the logic sequence saved at the end of the logic calibration to the digital calibration circuit. The subtractor in the digital calibration circuit performs a subtraction operation on P1 and P2 to generate ΔP (ΔP=P2-P1). ΔP is used as a compensation logic sequence to directly control the shutdown or conduction of some current branches. When the temperature deviates upward, ΔP is positive, the clock frequency increases, and some current branch switches are closed, so that the current decreases by ΔI, thereby reducing the frequency; when the temperature deviates downward, ΔP is negative, the clock frequency decreases, and some current branch switches are opened, so that the current increases by ΔI, thereby increasing the frequency. Finally, the output frequency of the RC oscillator is adjusted to be within the frequency tolerance range. Experiments show that the frequency error does not exceed ±0.5%. The present invention can solve the impact of temperature on the frequency of the chip internal clock after process calibration.

[0115] The present invention provides a micro-power clock calibration circuit for a passive chip, which is calibrated using a micro-power clock calibration method for a passive chip. Figure 1 As shown, the calibration process is similar to the calibration method introduced in the present invention and will not be described in detail here.

[0116] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0117] Although the present application is described herein with reference to various embodiments, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments in practicing the claimed application by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0118] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A micro-power clock calibration method for a passive chip, applied to a passive chip, wherein the passive chip includes an RC oscillator circuit, a memory circuit, and a digital calibration circuit, characterized in that: A temperature sensor is integrated inside the passive chip, and the micro-power consumption clock calibration method of the passive chip includes: During the air interface calibration phase, The digital calibration circuit is configured to generate a calibration logic sequence and send it to the RC oscillator circuit, thereby controlling some transistors of the current branch of the RC oscillator circuit to turn off or on to implement air interface calibration, and save the calibration logic sequence in the memory circuit; The temperature sensor is used to detect the internal temperature of the passive chip and store the internal temperature in the memory circuit; During the use phase, The memory circuit is configured to send the internal temperature stored during the air interface calibration phase and the calibration logic sequence to the digital calibration circuit; The temperature sensor is used to detect the internal temperature of the passive chip and transmit the internal temperature to the digital calibration circuit; The digital calibration circuit is configured to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence based on the internal temperature difference obtained by the subtraction, and send the compensation logic sequence and the calibration logic sequence to the RC oscillator circuit; The RC oscillator circuit is used to control the transistors of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, thereby compensating for the impact of temperature changes on the internal clock frequency of the passive chip by controlling the current size of the current branch; The digital calibration circuit is configured to generate a calibration logic sequence and send it to the RC oscillator circuit, thereby controlling some transistors of the current branch of the RC oscillator circuit to turn off or on to implement air interface calibration, and save the calibration logic sequence to the memory circuit, including: The digital calibration circuit is configured to receive an external clock transmitted via an air interface, use each clock cycle of the external clock as a reference cycle, count rising edges of the clock generated by the RC oscillator circuit within the reference cycle, subtract the count result from a preset logical value, count positive differences obtained by the subtraction, accumulate the positive differences in each reference cycle, and generate the RC oscillator circuit, which is configured to control the switching on or off of some transistors in its own current branch according to the calibration logic sequence; The digital calibration circuit calculates the difference between the internal temperature P1 stored in the internal memory and the internal temperature P2 directly transmitted by the temperature sensor to obtain the internal temperature difference. ; Internal temperature difference The current changes of the branch circuit in the RC oscillator circuit The relationship is: in, , , C is the capacitance of the equivalent capacitor in the RC oscillator circuit, and the value of V is twice the RC oscillator flip voltage. is the internal clock frequency of the passive chip.

2. The micro-power consumption clock calibration method of a passive chip according to claim 1, characterized in that: The temperature sensor output is connected to the memory circuit input and the digital calibration circuit input respectively, the memory circuit output is connected to the digital calibration circuit input, and the digital calibration circuit output is connected to the memory input and the RC oscillator circuit input.

3. The micro-power consumption clock calibration method of a passive chip according to claim 1, characterized in that: The RC oscillator circuit includes a current branch and an RS trigger, wherein the current branch includes a plurality of transistors and a charge-discharge capacitor; The RC oscillator circuit is configured to control the transistors of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, so as to compensate for the effect of temperature changes on the internal clock frequency of the passive chip by controlling the current of the current branch. The method includes: The RC oscillator circuit is used to control the transistor of its own current branch to turn off or on according to the calibration logic sequence and the compensation logic sequence, so as to charge or discharge the charging and discharging capacitor, thereby changing the current size of the current branch, thereby compensating for the impact of temperature changes on the internal clock frequency of the passive chip.

4. The micro-power consumption clock calibration method of a passive chip according to claim 1, characterized in that: The digital calibration circuit includes: counter 1, counter 2, subtractor, adder and logic unit. During the air interface calibration phase, The counter 1 is configured to receive an external clock transmitted via an air interface, use each clock cycle of the external clock as a reference cycle, and count rising edges of the clock generated by the RC oscillator circuit within the reference cycle; The logic unit is used to calculate the difference between the counting result of the counter 1 and a preset logic value; The counter 2 is used to count the positive difference values ​​obtained by subtracting the value from the counter 1; The adder is used to accumulate the positive difference value of each reference cycle to generate a calibration logic sequence; During the use phase, The subtractor is used to subtract the internal temperature stored in the memory from the internal temperature directly transmitted by the temperature sensor, generate a compensation logic sequence according to the internal temperature difference obtained by the subtraction, and send the compensation logic sequence to the RC oscillator circuit.

5. A passive chip micro-power clock calibration circuit, characterized in that: Calibration is performed using the micro-power consumption clock calibration method for a passive chip as described in any one of claims 1 to 4.

Images