A design method for a single VP port multi-resolution data multiplexing transmission module

Abstract

The present invention discloses a design method for a single VP port multi-resolution data multiplexing transmission module, wherein the multiplexing transmission module comprises an image receiving module and an image sending module; the image receiving module is responsible for receiving and identifying small image header information, and writing each valid data into a memory according to a configuration; the image sending module reads out a small resolution image in the memory according to the configuration, fills it into a large resolution VP timing, and sends it to a receiving end. The present invention uses a large resolution VP timing to fill multiple small resolution image data into a valid area data area, and adds customized specification information to the header of each small resolution image. While maintaining stable and continuous transmission of the VP port, it supports flexible changes in the size and number of small images to be transmitted, and can achieve transmission of multiple video sources with different resolutions while maintaining the VP timing working mode unchanged and the transmission timing uninterrupted, providing the possibility of realizing more video transmission when the VP port resources of the DSP chip are limited.

Description

Technical Field

[0001] The invention belongs to the field of video data transmission, and in particular relates to a design method for a single VP port multi-resolution data multiplexing transmission module. Background Art

[0002] The Video port interface is the basic interface for video transmission. The timing is described in detail in the VESA (Video Electronics Standards Association) standard. This standard specifies the timing standards for display monitors of various resolutions and refresh rates in the computer (VESA) format. The standard specifies the specifications of video timing at different resolutions, including the number of row pixels, the number of column pixels, the row synchronization frequency, the field synchronization frequency, the pixel clock, the total row time, the total field time, the row blanking time, the field blanking time, the data bit width, and other information.

[0003] In the prior art, when using a video port to transmit image data, a video port only transmits a fixed resolution video data format at a fixed time. If the image resolution needs to be changed, or even just the video stream source needs to be changed, the video port working mode needs to be reconfigured and timing signals such as pixel clock and line field synchronization need to be switched.

[0004] In the media exchange system, the multi-point control center can support more video data interactions at the same time, which reflects the stronger product performance and is an important competitive indicator. In order to make full use of the limited vp port resources of the media sub-board and transmit more image data, the design of the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a design method for a single VP port multi-resolution data multiplexing transmission module, which can realize the transmission of multiple video sources with different resolutions while keeping the video port timing working mode unchanged and the transmission timing uninterrupted, and provide the possibility of realizing more video transmission when the VP port resources of a DSP chip are limited.

[0006] The technical solution of the present invention is:

[0007] A design method for a single VP port multi-resolution data multiplexing transmission module, the designed single VP port multi-resolution data multiplexing transmission module includes an image receiving module and an image sending module;

[0008] The image receiving module is responsible for receiving and identifying the small image header information and writing each valid data into the memory according to the configuration;

[0009] The image sending module reads the small-resolution image in the memory according to the configuration, fills it into the large-resolution VP timing, and sends it to the receiving end.

[0010] Preferably, the image format of the data sent by the VP is:

[0011] Insert multiple small-resolution image data into the large-resolution VP sequence;

[0012] Add custom header information at the beginning of each small-resolution image data: including image number, image size specification, and image data format information;

[0013] Each small-resolution image data is no longer arranged according to the number of row pixels of the resolution size, but is continuously arranged in the effective row of the large-resolution VP timing;

[0014] At the end of the small-resolution image data, in order to align with the number of pixels in the large-resolution image row, invalid data is added at the end for alignment;

[0015] The invalid data segment between each small-resolution image is variable and can be adjusted according to the actual needs of the video bitstream;

[0016] When the current frame timing cannot fit a complete small-resolution image, the remaining portion of the image will be distributed at the front of the next frame.

[0017] Preferably, the data sent down by the VP is the decoded data prepared by the DSP in the DDR, the DSP calls the VP port controller to read the large resolution format from the memory, and sends it to the image receiving module via the VP downlink, the receiving module identifies the valid small image in the VP timing, and writes the image into the corresponding memory according to the parameters configured by the software;

[0018] When an image needs to be sent, the DSP configures the image sending module, selects the image number to be sent in the memory, starts the image sending module, and the sending module reads the target image from the DDR, adds the valid data to the valid area according to the VP timing, and sends it to the DSP. After receiving the image, the DSP disassembles the image in the same way.

[0019] Preferably, the image receiving module includes:

[0020] The image timing capture module parses the timing of VP downlink according to the VP port specification information configured by the software in the register module, identifies the line-field synchronization, identifies the small image header information, interprets the information in the header information, and caches the valid data into the image data cache;

[0021] Image data cache, temporarily storing the image data of the image timing capture module in RAM;

[0022] The process control module is responsible for the overall process control module of the image receiving module, which is responsible for reading the software configuration information from the register module and mobilizing the write memory module to write the data in the small image data cache module into the corresponding position of the memory;

[0023] The register module provides a software interface for software to configure the image receiving module;

[0024] The write memory module is connected to the DDR controller and is responsible for writing the data in the cache RAM to the memory.

[0025] Preferably, the image sending module includes:

[0026] The image timing generation module is responsible for reading image data from the RAM cache and generating VP timing according to the specification parameters of VP in the register module;

[0027] The image data cache module caches the image data read by the memory read module in RAM by line;

[0028] The process control module is responsible for the full process control of the image sending module, reads the software configuration information from the register module, and mobilizes the memory reading module to read the small image data from the memory and write it into the image data cache module;

[0029] Register module, all configuration information of this module is accessed by software interface;

[0030] The read memory module is connected to the DDR controller and is responsible for writing the data in the memory to the cache RAM.

[0031] The advantages of the present invention are:

[0032] The design method of the single VP port multi-resolution data multiplexing transmission module proposed in the present invention uses a large-resolution VP timing sequence to fill multiple small-resolution image data into the valid area data area, and adds customized specification information to the header of each small-resolution image. While maintaining the stable and continuous transmission of the VP port, it supports flexible changes in the size and number of small images to be transmitted, and can achieve the transmission of multiple video sources with different resolutions while keeping the video port timing working mode unchanged and the transmission timing uninterrupted. For the case where the VP port resources of the DSP chip are limited, it is possible to realize the transmission of more channels of video. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0034] Figure 1 It is a schematic diagram of small image data included in the VP timing sequence;

[0035] Figure 2 It is a schematic diagram of transmission and reception between DSP and transceiver module;

[0036] Figure 3 The structural diagram of the image receiving and sending module

[0037] Figure 4 Publish flowcharts for software. DETAILED DESCRIPTION

[0038] The design idea of ​​the present invention is to use the large-resolution VP timing to fill multiple small-resolution image data into the valid area data area, and add customized specification information to the header of each small-resolution image. While maintaining the stable and continuous transmission of the VP port, it supports flexible changes in the size and number of small images transmitted.

[0039] The present invention includes an image receiving module and an image sending module. The image receiving module is responsible for receiving data sent by VP, identifying small image header information, and writing each valid data into the memory according to the configuration. The image sending module reads the small resolution image in the memory according to the configuration, fills it into the large resolution VP timing, and sends it to the receiving end.

[0040] like Figure 1 As shown, the image format of the data sent by the VP is: inserting 3 small-resolution image data into the large-resolution VP sequence;

[0041] Add custom header information at the beginning of each small image data: including image number, image size specification, image data format and other information.

[0042] Each small image data is no longer arranged according to the number of row pixels of the resolution size, but is arranged continuously in the effective row of the large resolution VP timing;

[0043] At the end of the small image data, in order to align with the number of pixels in the large image row, invalid data needs to be added at the end for alignment;

[0044] The invalid data segment between each small image is variable and can be adjusted according to the actual needs of the video bitstream;

[0045] When the current frame timing cannot fit a complete small image, the remaining part of the image will be distributed at the front part of the next frame.

[0046] The above-mentioned VP timing multiplexing format requires software and hardware collaborative design to be implemented. This embodiment mainly describes the design and implementation of digital circuits. The digital circuit design of this embodiment includes an "image receiving module" and an "image sending module". Verilog coding is used to implement RTL design, which can be integrated in FPGA and IC chips. Taking the docking of the image processing DSP chip with the "image transceiver module" designed by us as an example, the working principle is briefly described.

[0047] like Figure 2 As shown, dsp is the codec processing chip, which prepares the decoded data in ddr. Figure 1The format in the vp downstream port supports the maximum resolution to prepare the memory data, the dsp calls the vp port controller to read the large resolution format from the memory, and sends it to the image receiving module via the vp downstream, the receiving module identifies the valid small image in the VP timing, and writes the image into the corresponding memory according to the parameters configured by the software.

[0048] When an image needs to be sent, the DSP will configure the image sending module, select the image number that needs to be sent in the memory, start the image sending module, the sending module reads the target image from the DDR, adds the valid data to the valid area according to the VP timing, and sends it to the DSP. After receiving the image, the DSP disassembles the image in the same way.

[0049] like Figure 3 As shown in the figure, the design block diagram of the image transceiver module briefly describes the composition and functions of the transceiver module:

[0050] Video donload "image receiving module" includes:

[0051] VP timing Capture module: This module parses the timing of VP downlink, identifies the line-field synchronization, identifies the small image header information, interprets the information in the header information, and caches the valid data into the "image data cache" according to the VP port specification information configured by the software in the "register module";

[0052] RAM buffer "image data cache", temporarily stores the image data of the "image timing capture" module in RAM;

[0053] flow_contrl "flow control" module, responsible for the overall flow control module of the "image receiving" module, responsible for reading the software configuration information from the reg if "register" module, and mobilizing the DDR_write_if "write memory" module to write the data in the small "image data cache" module to the corresponding location in the memory;

[0054] reg_if "register" module, which provides a software interface for software to configure the "image receiving module";

[0055] The DDR_write_if "write memory" module is connected to the DDR controller and is responsible for writing the data in the cache RAM to the memory.

[0056] Video upload "image sending module" includes:

[0057] VP timing generator, the "image timing generation" module, is responsible for reading image data from the RAM cache and generating VP timing according to the VP specification parameters in the "register module";

[0058] ram buffer, the "image data cache" module, caches the image data read by the "read memory" module in RAM by line;

[0059] flow_contrl, the "flow control" module, is responsible for the full process control of the "image sending module", reads the software configuration information from the reg if "register" module, and calls the DDR_read_if module to read the small image data from the memory and write it to the rambuffer "image data cache" module;

[0060] reg_if "register" module, all configuration information of this module is accessed by the software interface;

[0061] DDR_read_if "read memory module", connected to the DDR controller, is responsible for writing the data in the memory to the cache RAM.

[0062] like Figure 4 As shown in the figure, the process from the software perspective is:

[0063] In the image sending process, the software configures the "image transceiver module", prepares the image data on the host computer, configures the VP port working mode, configures the write memory start address corresponding to the small image, starts the "image capture" module, sends the image data from the host computer, and the image data is captured into the memory of the slave computer.

[0064] The image upload process is roughly the same as the image download process, except that the direction is opposite, so I will not go into details.

[0065] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A design method for a single VP port multi-resolution data multiplexing transmission module, characterized in that: The designed single VP port multi-resolution data multiplexing transmission module includes an image receiving module and an image sending module; The image receiving module is responsible for receiving data sent by VP, identifying the header information of the small-resolution image, and writing each valid data into the memory according to the configuration; The image sending module reads the small-resolution image in the memory according to the configuration, fills it into the large-resolution VP timing, and sends it to the receiving end; The image format of the data sent by the VP is: Insert multiple small-resolution image data into the large-resolution VP sequence; Add custom header information at the beginning of each small-resolution image data: including image number, image size specification, and image data format information; Each small-resolution image data is no longer arranged according to the number of row pixels of the resolution size, but is continuously arranged in the effective row of the large-resolution VP timing; At the end of the small-resolution image data, in order to align with the number of pixels in the large-resolution image row, invalid data is added at the end for alignment; The invalid data segment between each small-resolution image is variable and can be adjusted according to the actual needs of the video bitstream; When the current frame sequence cannot fit a complete small-resolution image, the remaining part of the image will be distributed at the front of the next frame; The image receiving module comprises: The image timing capture module parses the timing of VP downlink according to the VP port specification information configured by the software in the register module, identifies the line-field synchronization, identifies the header information of the small-resolution image, interprets the information in the header information, and caches the valid data into the image data cache; Image data cache, temporarily storing the image data of the image timing capture module in RAM; The process control module is responsible for the overall process control of the image receiving module, is responsible for reading the software configuration information from the register module, and mobilizes the write memory module to write the data in the image data cache module to the corresponding location of the memory; The register module provides a software interface for software to configure the image receiving module; The write memory module is connected to the DDR controller and is responsible for writing the data in the cache RAM into the memory; The image timing generation module is responsible for reading image data from the RAM cache and generating VP timing according to the specification parameters of VP in the register module; The image data cache module caches the image data read by the memory read module in RAM by line; The process control module is responsible for the full process control of the image sending module, reads the software configuration information from the register module, and mobilizes the memory reading module to read the low-resolution image data from the memory and write it into the image data cache module; Register module, all configuration information of this module is accessed by software interface; The read memory module is connected to the DDR controller and is responsible for writing the data in the memory to the cache RAM.

2. The design method of a single VP port multi-resolution data multiplexing transmission module according to claim 1, characterized in that: The VP sent data is data prepared in the memory after being decoded by the DSP. The DSP calls the VP port controller to read the large resolution format from the memory and sends it to the image receiving module via the VP downlink. The receiving module identifies the valid small resolution image in the VP timing and writes the image into the corresponding memory according to the parameters configured by the software. When an image needs to be sent, the DSP configures the image sending module, selects the image number that needs to be sent in the memory, starts the image sending module, and the sending module reads the target image from the memory, adds the valid data to the valid area according to the VP timing, and sends it to the DSP. After receiving the image, the DSP disassembles the image in the same way.

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