Semiconductor structure manufacturing methods and semiconductor structures

Abstract

This invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate and a dielectric layer on the substrate; forming a first conductive pillar, a second conductive pillar, and a third conductive pillar within the dielectric layer; the first conductive pillar is located in an array region, the second conductive pillar is located in a peripheral region, and the third conductive pillar is located in a core region; forming a mask layer covering the dielectric layer, the first conductive pillar, the second conductive pillar, and a portion of the third conductive pillar; using the third mask layer as a mask, etching a portion of the thickness of the third conductive pillar to form a stacked third lower conductive pillar and a third upper conductive pillar; the top surface area of ​​the third lower conductive layer is larger than the top surface area of ​​the third upper conductive layer, and the third upper conductive pillar, the third lower conductive pillar, and the dielectric layer form a groove; forming a capping layer filling the groove, the capping layer exposing the top surface of the third upper conductive pillar. This invention can optimize the manufacturing process of semiconductor structures and improve the performance of semiconductor structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the process nodes of semiconductor structures are constantly shrinking, leading to increasingly higher integration levels. Increased integration levels bring several benefits: First, it increases the functionality of the semiconductor structure; second, according to Moore's Law, increased integration levels directly result in lower costs; and third, it reduces the overall supply voltage of the semiconductor structure, thereby reducing power consumption.

[0003] In pursuit of smaller process nodes, the manufacturing process and performance of semiconductor structures need further improvement. Summary of the Invention

[0004] This invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, in order to optimize the manufacturing process of the semiconductor structure and improve its performance.

[0005] This invention provides a method for manufacturing a semiconductor structure, the semiconductor structure including an array region, a peripheral region, and a core region, comprising: providing a substrate and a dielectric layer on the substrate; forming a first conductive pillar, a second conductive pillar, and a third conductive pillar located within the dielectric layer; the first conductive pillar being located in the array region, the second conductive pillar being located in the peripheral region, and the third conductive pillar being located in the core region; forming a mask layer covering the dielectric layer, the first conductive pillar, the second conductive pillar, and a portion of the third conductive pillar, the mask layer also exposing the top surface of a portion of the third conductive pillar; using the third mask layer as a mask, etching a portion of the thickness of the third conductive pillar to form a stacked third lower conductive pillar and a third upper conductive pillar; the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar, and the third upper conductive pillar, the third lower conductive pillar, and the dielectric layer form a groove; forming a capping layer filling the groove, the capping layer exposing the top surface of the third upper conductive pillar.

[0006] Additionally, one of the third upper conductive pillars is used to form a groove.

[0007] Additionally, all the sidewalls of one of the third upper conductive posts are used to form a groove, and the groove surrounds the third upper conductive post.

[0008] Alternatively, the three sidewalls of the third upper conductive post are used to form the groove; or, the two connected sidewalls of the third upper conductive post are used to form the groove; or, the one sidewall of the third upper conductive post is used to form the groove.

[0009] Additionally, one of the third upper conductive pillars is used to form two grooves, and the two opposite sidewalls of the third upper conductive pillar are respectively used to form two grooves.

[0010] In addition, the ratio of the top surface area of ​​the third upper conductive pillar to the top surface area of ​​the third lower conductive pillar is less than 4 / 5.

[0011] In addition, the ratio of the etching depth of the groove to the thickness of the third conductive post is greater than 1 / 5.

[0012] In addition, the substrate has multiple active regions, which are electrically connected to the first conductive post, the second conductive post and the third conductive post, respectively.

[0013] In addition, the core region has a gate in the substrate, and the gate is electrically connected to the third conductive post.

[0014] In addition, the step of forming the capping layer includes: forming an initial capping layer covering the dielectric layer, the first conductive pillar, the second conductive pillar, the third upper conductive pillar, and the third lower conductive pillar; removing a portion of the initial capping layer to expose the top surface of the first conductive pillar, the top surface of the second conductive pillar, and the top surface of the third upper conductive pillar, with the remaining initial capping layer serving as the capping layer.

[0015] This invention also provides a semiconductor structure, comprising: a substrate having a dielectric layer thereon; a first conductive pillar, a second conductive pillar, and a third conductive pillar located within the dielectric layer; the first conductive pillar being located in the array region, the second conductive pillar being located in the peripheral region, and the third conductive pillar being located in the core region; the third conductive pillar comprising a third lower conductive pillar and a third upper conductive pillar stacked thereon, wherein the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar; and a capping layer located within the region enclosed by the third upper conductive pillar, the third lower conductive pillar, and the dielectric layer.

[0016] In addition, the orthographic projection of the top surface of the third upper conductive post onto the top surface of the third lower conductive post falls within the top surface of the third lower conductive post.

[0017] In addition, the capping layer surrounds the third upper conductive post, and the capping layer is a closed annular structure.

[0018] In addition, in a direction parallel to the top surface of the substrate, the cross-sectional shape of the third upper conductive post and the third lower conductive post is rectangular; one side wall of the third upper conductive post is directly opposite to one side wall of the third lower conductive post; or, the two side walls of the third upper conductive post are directly opposite to the two side walls of the third lower conductive post; or, the three side walls of the third upper conductive post are directly opposite to the three side walls of the third lower conductive post.

[0019] In addition, the ratio of the thickness of the third upper conductive post to that of the third lower conductive post is in the range of 3 / 5 to 2 / 5.

[0020] The technical solution provided by the embodiments of the present invention has at least the following advantages:

[0021] In this embodiment of the invention, a mask layer is formed covering the first conductive pillar, the second conductive pillar, and a portion of the third conductive pillar; a portion of the thickness of the third conductive pillar is etched to form a third lower conductive pillar, a third upper conductive pillar, and a groove; a capping layer is formed to fill the groove. This allows for the consideration of manufacturing processes for the array region, the peripheral region, and the core region, changing the size of the third conductive pillar while maintaining the original sizes of the first and second conductive pillars. Furthermore, the top surface area of ​​the third lower conductive pillar is larger than that of the third upper conductive pillar, meaning the third lower conductive pillar has a larger size, which reduces the resistance of the third conductive pillar and improves electrical performance; additionally, the exposed top surface area of ​​the third upper conductive pillar is smaller, reducing the probability of erroneous electrical connections between the third upper conductive pillar and other conductive structures.

[0022] Furthermore, the ratio of the top surface area of ​​the third upper conductive post to the top surface area of ​​the third lower conductive post is less than 4 / 5. When the area ratio is within the above range, the probability of incorrect electrical connection of the third upper conductive post can be reduced, and the resistance of the third lower conductive post can also be reduced. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figures 1-12 The diagram shows the structural schematics corresponding to each step in the semiconductor structure manufacturing method provided in the embodiments of the present invention. Detailed Implementation

[0025] Semiconductor structures typically consist of an array region, a peripheral region, and a core region. The core region is closely connected to the array region and has unique device structures such as word-line drivers. The peripheral region is used to ensure that the core region's functions are realized. When the size of a semiconductor structure is reduced, the size of all three regions must be continuously reduced. This results in the conductive pillars in the core region exhibiting high resistance, and the electrical performance of the core region cannot be effectively improved.

[0026] This invention provides a method for manufacturing a semiconductor structure, comprising: forming a mask layer covering a first conductive pillar, a second conductive pillar, and a portion of a third conductive pillar; etching a portion of the thickness of the third conductive pillar to form a third lower conductive pillar and a third upper conductive pillar; thereby, while changing the morphology and size of the third conductive pillar, the original morphology of the first and second conductive pillars can be maintained, thus balancing the manufacturing processes of the three regions. The top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar, and the third upper conductive pillar, the third lower conductive pillar, and the dielectric layer form a groove; forming a capping layer to fill the groove; the larger size of the third lower conductive pillar can reduce resistance and improve electrical performance, while the capping layer exposes the smaller-sized third upper conductive pillar, which can prevent the third upper conductive pillar from making incorrect electrical connections with other conductive structures.

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0028] One embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figures 1-12 The accompanying drawings are schematic diagrams of each step in the semiconductor structure manufacturing method provided in this embodiment. The following will provide a detailed description in conjunction with the accompanying drawings.

[0029] refer to Figure 1 The semiconductor structure includes an array region a, a peripheral region b, and a core region c. In this embodiment, the semiconductor structure can be a dynamic random access memory (DRAM). The array region a is suitable for forming structures such as transistors, word lines, and bit lines. The core region c is suitable for forming device structures such as word line drivers. The peripheral region b is used to ensure that the functions of the core region c are realized.

[0030] A substrate 100 and a dielectric layer 110 located on the substrate 100 are provided. Specifically, the substrate 100 of the array region a, the peripheral region b, and the core region c each has a substrate 101, an isolation structure 103, and an active region 102. The substrate 101 can be made of a semiconductor material, such as an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon germanide, gallium arsenide, or indium gallium nitride, etc. The substrate 101 may also contain doped ions, such as boron or phosphorus. The isolation structure 103 is made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. The active region 102 is made of a semiconductor material and also contains doped ions. Furthermore, the doping type of the active region 102 can be opposite to the doping type of the substrate 101.

[0031] Furthermore, in this embodiment, the substrate 100 of the core region c also has a gate (not shown), and the substrate 100 of the array region a also has a word line 104. The gate and the word line 104 can be made of the same material, such as tungsten. In other embodiments, the gate and the word line can also be made of different materials.

[0032] Multiple conductive pillars will subsequently be formed within the dielectric layer 110, which isolates the conductive pillars. In this embodiment, the dielectric layer 110 has a double-layer structure, comprising a lower dielectric layer 111 and an upper dielectric layer 112 stacked together. In other embodiments, the dielectric layer may also be a single-layer structure, or a structure with three or more layers. The material of the dielectric layer 110 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0033] In this embodiment, the dielectric layer 110 of the array region a also includes a bit line contact layer 141 and a bit line conductive layer 142.

[0034] refer to Figures 2-3 A first conductive pillar 131, a second conductive pillar 132, and a third conductive pillar 133 are formed within the dielectric layer 110; the first conductive pillar 131 is located in the array region a, the second conductive pillar 132 is located in the peripheral region b, and the third conductive pillar 133 is located in the core region c.

[0035] The first conductive post 131 is electrically connected to the active region 102 in the array region a, the second conductive post 132 is electrically connected to the active region 102 in the peripheral region b, and the third conductive post 133 is electrically connected to the active region 102 and the gate in the core region c.

[0036] Specifically, refer to Figure 2The dielectric layer 110 is etched using a mask 200 to form a first via 113, a second via 114, and a third via 115 located within the dielectric layer 110. The first via 113 is located in array region a, the second via 114 is located in peripheral region b, and the third via 115 is located in core region c. That is, the first via 113, the second via 114, and the third via 115 are formed in the same step, thereby simplifying the manufacturing process.

[0037] The first through hole 113 is subsequently used to fill the first conductive post, the second through hole 114 is subsequently used to fill the second conductive post, and the third through hole 115 is subsequently used to fill the third conductive post.

[0038] refer to Figure 3 This forms a filling of the first through-hole 113 (reference). Figure 2 The first conductive post 131 and the second through hole 114 are filled (reference). Figure 2 The second conductive post 132 and the filling of the third through hole 115 (reference) Figure 2 The third conductive post 133.

[0039] In this embodiment, the first conductive pillar 131, the second conductive pillar 132, and the third conductive pillar 133 are formed in the same step, thereby simplifying the manufacturing process. Specifically, the method for forming the first conductive pillar 131, the second conductive pillar 132, and the third conductive pillar 133 can be physical vapor deposition; in other embodiments, the method can also be chemical vapor deposition.

[0040] In this embodiment, the first conductive pillar 131, the second conductive pillar 132, and the third conductive pillar 133 are made of the same material, and all are conductive materials, such as tungsten, copper, gold, silver, or polycrystalline silicon. In other embodiments, the materials of the first conductive pillar, the second conductive pillar, and the third conductive pillar may be different.

[0041] In this embodiment, the first conductive post 131, the second conductive post 132, and the third conductive post 133 are cuboids. In other embodiments, the first conductive post, the second conductive post, and the third conductive post can also be cylindrical.

[0042] refer to Figure 4 A mask layer 120 is formed, which covers the dielectric layer 110, the first conductive pillar 131, the second conductive pillar 132, and a portion of the third conductive pillar 133. The mask layer 120 also exposes the top surface of a portion of the third conductive pillar 133. In this example, the material of the mask layer 120 is photoresist. In other embodiments, the material of the mask layer can also be a hard mask material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0043] refer to Figure 5 With the third mask layer 120 (reference) Figure 4Using a mask, a portion of the thickness of the third conductive pillar 133 is etched to form a third lower conductive pillar 1331 and a third upper conductive pillar 1332 stacked together; the top surface area of ​​the third lower conductive layer 1331 is larger than the top surface area of ​​the third upper conductive pillar 1332, and the third upper conductive pillar 1332, the third lower conductive pillar 1331 and the dielectric layer 110 form a groove 1333.

[0044] Etching the third conductive pillar 133 alters its size and morphology, while the size and morphology of the first conductive pillar 131 and the second conductive pillar 132, which are covered by the mask layer 120, remain unchanged.

[0045] A capping layer will subsequently form to fill the groove 1333, exposing the top surface of the third upper conductive post 1332. The third upper conductive post 1332 will then be electrically connected to the corresponding conductive structure. It is understood that if the third upper conductive post 1332 also has a large size, it may connect to other conductive structures that should not be connected, causing a short circuit. Therefore, the third upper conductive post 1332 and the third lower conductive post 1331 provided in this embodiment can reduce resistance while avoiding incorrect electrical connections.

[0046] The ratio of the etching depth of the groove 1333 to the thickness of the third conductive post 133 is greater than 1 / 5, for example, it can be 2 / 5, 1 / 2, or 3 / 5. It is understood that the etching depth affects the process time, the resistance and stability of the third conductive post 133, and the density of the subsequent capping layer. When the ratio of the etching depth of the groove 1333 to the thickness of the third conductive post 133 is within the above range, the process time is shorter, the third conductive post 133 can maintain lower resistance and higher stability, and the capping layer subsequently filled in the groove 1333 can have a higher density, thus providing good isolation.

[0047] The ratio of the top surface area of ​​the third upper conductive post 1332 to the top surface area of ​​the third lower conductive post 1331 is less than 4 / 5, for example, it can be 1 / 2, 1 / 3 or 1 / 4. When the area ratio is within the above range, the probability of incorrect electrical connection of the third upper conductive post 1332 can be reduced, and the resistance of the third lower conductive post 1331 can be further reduced.

[0048] The relative positions of the groove 1333, the third upper conductive post 1332, and the third lower conductive post 1331 will be described in detail below.

[0049] In this embodiment, a third upper conductive post 1332 is used to form a groove 1333.

[0050] In one example, referring to the reference Figure 5 and Figure 6 , Figure 6 for Figure 5 A top view of the central core area c; it should be noted that... Figure 6 The left or right area in the middle corresponds to Figure 5 The core area c is shown. Figure 6 The middle area in Figure 5 The third lower conductive post 1331 in the middle region is electrically connected to the gate in the substrate 100 of the core region c. All the sidewalls of a third upper conductive post 1332 form a groove 1333, and the groove 1333 surrounds the third upper conductive post 1332. That is, all the sidewalls of the third upper conductive post 1332, the top surface of the third lower conductive post 1331, and the dielectric layer 110 form a groove 1333.

[0051] At this point, the length of the third lower conductive post 1331 is greater than the length of the third upper conductive post 1332, and the width of the third lower conductive post 1331 is greater than the width of the third upper conductive post 1332. That is, the area of ​​the top surface of the third lower conductive post 1331 used to form the groove 1333 can be maximized, thereby further improving and reducing the resistance of the third lower conductive post 1331.

[0052] Furthermore, the central axis of the third upper conductive post 1332 in a direction perpendicular to the top surface of the substrate 100 coincides with the central axis of the third lower conductive post 1331 in a direction perpendicular to the top surface of the substrate 100. In other embodiments, the central axis of the third upper conductive post may not coincide with the center of the third lower conductive post.

[0053] In another example, refer to Figure 7 The three sidewalls of the third upper conductive post 1332 form a groove 1333. That is, the three sidewalls of the third upper conductive post 1332, the top surface of the third lower conductive post 1331, and the dielectric layer 110 form a groove 1333. In other words, the groove 1333 only surrounds the three sidewalls of the third upper conductive post 1332, and the other sidewall of the third upper conductive post 1332 is directly opposite one sidewall of the third lower conductive post 1331.

[0054] In another example, refer to Figure 8 The two connected sidewalls of the third upper conductive post 1332 form a groove 1333. That is, the two connected sidewalls of the third upper conductive post 1332, the top surface of the third lower conductive post 1331, and the dielectric layer 110 form a groove 1333. The other two connected sidewalls of the third upper conductive post 1332 are directly opposite the two sidewalls of the third lower conductive post 1331.

[0055] In another example, refer to Figure 9One sidewall of the third upper conductive post 1332 is used to form a groove 1333. That is, one sidewall of the third upper conductive post 1332, the top surface of the third lower conductive post 1331, and the dielectric layer 110 form a groove 1333. The other three sidewalls of the third upper conductive post 1332 are directly opposite the three sidewalls of the third lower conductive post 1331.

[0056] In other embodiments, reference is made to Figure 10 A third upper conductive post 1332 is used to form two grooves 1333, and the two opposite sidewalls of the third upper conductive post 1333 are used to form two grooves 1333 respectively. That is to say, the two opposite sidewalls of the third upper conductive post 1332, the top surface of the third lower conductive post 1331, and the dielectric layer 110 form two grooves 1333.

[0057] Furthermore, the central axis of the third upper conductive post 1332 in the direction perpendicular to the top surface of the substrate 100 can also coincide with the central axis of the third lower conductive post 1331 in the direction perpendicular to the top surface of the substrate 100.

[0058] refer to Figures 11-12 A cover layer 140 is formed to fill the groove 1333, and the cover layer 140 exposes the top surface of the third upper conductive post 1332.

[0059] Specifically, refer to Figure 11 An initial capping layer 141 is formed, covering the dielectric layer 110, the first conductive pillar 131, the second conductive pillar 132, the third upper conductive pillar 1332, and the third lower conductive pillar 1331. In this embodiment, the initial capping layer 141 can be formed by chemical vapor deposition. The initial capping layer 141 is an insulating material. In this embodiment, the material of the initial capping layer 141 is the same as the material of the upper dielectric layer 112. For example, both can be silicon nitride. In other embodiments, the material of the initial capping layer 141 can also be different from the material of the upper dielectric layer 112.

[0060] refer to Figure 12 A portion of the initial capping layer 141 is removed to expose the top surfaces of the first conductive pillar 131, the second conductive pillar 132, and the third upper conductive pillar 133, leaving the remaining initial capping layer 141 as the capping layer. Specifically, the initial capping layer 141 is planarized to remove the portion of the initial capping layer 141 above the top surface of the dielectric layer 110. In this embodiment, planarization is performed by chemical mechanical polishing; in other embodiments, etching may also be used to remove a portion of the initial capping layer.

[0061] In summary, in this embodiment, a third upper conductive pillar 1332 and a third lower conductive pillar 1331 are formed, and the top surface area of ​​the third upper conductive pillar 1332 is smaller than the top surface area of ​​the third lower conductive pillar 1331. This reduces the probability of a short circuit between the third upper conductive pillar 1332 and other conductive structures, and also reduces the resistance of the third conductive pillar 133, thereby improving its electrical performance. Furthermore, the formation processes of the array region a and the peripheral region b are also considered during the formation of the third conductive pillar 133, thus optimizing the semiconductor structure manufacturing process.

[0062] Another embodiment of the present invention provides a semiconductor structure, which can be manufactured by the manufacturing method of the semiconductor structure provided in the previous embodiment. Figure 12 This is a schematic diagram of the semiconductor structure provided in this embodiment, with reference to... Figure 12 The semiconductor structure includes: a substrate 100, on which a dielectric layer 110 is formed; a first conductive pillar 131, a second conductive pillar 132, and a third conductive pillar 133 located within the dielectric layer 110; the first conductive pillar 131 is located in array region a, the second conductive pillar 132 is located in peripheral region b, and the third conductive pillar 133 is located in core region c; the third conductive pillar 133 includes a third lower conductive pillar 1331 and a third upper conductive pillar 1332 stacked together, and the top surface area of ​​the third lower conductive pillar 1331 is larger than the top surface area of ​​the third upper conductive pillar 1332; and a capping layer 140 located within the area enclosed by the third upper conductive pillar 1332, the third lower conductive pillar 1331, and the dielectric layer 110. For parts of this embodiment that are the same as or similar to the previous embodiment, please refer to the detailed description of the previous embodiment, which will not be repeated here.

[0063] The following explanation will be provided in conjunction with the accompanying drawings.

[0064] The substrates 100 of array region a, peripheral region b, and core region c each have a substrate 101, an isolation structure 103, and an active region 102. In this embodiment, the substrate 100 of core region c also has a gate, and the substrate 100 of array region a also has a word line 104.

[0065] The first conductive post 131 is electrically connected to the active region 102; the second conductive post 132 is electrically connected to the active region 102; and the third conductive post 133 is electrically connected to the gate or the active region 102.

[0066] The third conductive post 133 includes a third lower conductive post 1331 and a third upper conductive post 1332 stacked together. In this embodiment, the third upper conductive post 1332 and the third lower conductive post 1331 are cuboid in shape, that is, in the direction parallel to the top surface of the substrate 100, the cross-sectional shape of the third upper conductive post 1332 and the third lower conductive post 1331 is rectangular. In other embodiments, the third upper conductive post 1332 and the third lower conductive post 1331 may also be cylindrical.

[0067] In this embodiment, the orthographic projection of the top surface of the third upper conductive post 1332 onto the top surface of the third lower conductive post 1331 falls within the top surface of the third lower conductive post 1331. At this time, the third upper conductive post 1332 and the third lower conductive post 1331 are directly opposite each other, and the contact area between them is the largest, resulting in the smallest contact resistance.

[0068] The thickness ratio of the third upper conductive post 1332 to the third lower conductive post 1331 ranges from 3 / 5 to 2 / 5, for example, it can be 1 / 2. When the thickness ratio is within the above range, the third lower conductive post 1331 can have a larger volume, and therefore, the third lower conductive post 1331 has a smaller resistance.

[0069] In this embodiment, the capping layer 140 surrounds the third upper conductive post 1332, and the capping layer 140 is a closed annular structure. When the capping layer 140 is a closed annular structure, it indicates that the capping layer 140 has a large volume. Since the capping layer 140 is located directly above the third lower conductive post 1331, the third lower conductive post 1331 can also have a large volume, which helps to reduce the resistance of the third lower conductive post 1331. When the capping layer 140 surrounds the third upper conductive post 1332, the sidewalls of the third upper conductive post 1332 and the sidewalls of the third lower conductive post 1331 are not directly opposite each other; in other embodiments, a portion of the sidewalls of the third upper conductive post and a portion of the sidewalls of the third lower conductive post may also be directly opposite each other.

[0070] Specifically, refer to Figure 7 One sidewall of the third upper conductive post 1332 is directly opposite one sidewall of the third lower conductive post 1331; Reference Figures 8-9 The two sidewalls of the third upper conductive post 1332 are directly opposite the two sidewalls of the third lower conductive post 1331; Reference Figure 10 The three sidewalls of the third upper conductive pillar 1332 are directly opposite the three sidewalls of the third lower conductive pillar 1331. That is, the capping layer 140 (reference) Figure 12 The third upper conductive pillar 1332 is surrounded only by a portion of its sidewalls, while the remaining sidewalls of the third upper conductive pillar 1332 that are not surrounded by the capping layer 140 are directly opposite a portion of the sidewalls of the third lower conductive pillar 1331.

[0071] In summary, the top surface area of ​​the third upper conductive post 1332 is smaller than that of the third lower conductive post 1331, which can reduce the probability of short circuit between the third upper conductive post 1332 and other conductive structures, and also reduce the resistance of the third conductive post 133, thereby improving the electrical performance of the third conductive post 133.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, said semiconductor structure comprising an array region, a peripheral region, and a core region, characterized in that, include: Provide a substrate and a dielectric layer located on the substrate; A mask is formed on the dielectric layer, and the dielectric layer is etched using the mask to form a first via, a second via, and a third via within the dielectric layer; a first conductive post is formed to fill the first via, a second conductive post to fill the second via, and a third conductive post to fill the third via, wherein the first conductive post, the second conductive post, and the third conductive post are formed in the same step; The first conductive pillar is located in the array region, the second conductive pillar is located in the peripheral region, and the third conductive pillar is located in the core region; A mask layer is formed, which covers the dielectric layer, the first conductive pillar, the second conductive pillar and a portion of the third conductive pillar, and the mask layer also exposes a portion of the top surface of the third conductive pillar; Using the mask layer as a mask, a portion of the thickness of the third conductive pillar is etched to form a stacked third lower conductive pillar and a third upper conductive pillar; the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar, and the third upper conductive pillar, the third lower conductive pillar and the dielectric layer form a groove. A capping layer is formed to fill the groove, the capping layer exposing the top surface of the third upper conductive post.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, One of the third upper conductive pillars is used to form a groove.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, All the sidewalls of the third upper conductive post are used to form a groove, and the groove surrounds the third upper conductive post.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The three sidewalls of the third upper conductive post are used to form the groove; or, the two connected sidewalls of the third upper conductive post are used to form the groove; or, the one sidewall of the third upper conductive post is used to form the groove.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, One of the third upper conductive pillars is used to form two grooves, and the two opposite sidewalls of the third upper conductive pillar are used to form two grooves respectively.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The ratio of the top surface area of ​​the third upper conductive pillar to the top surface area of ​​the third lower conductive pillar is less than 4 / 5.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The ratio of the etching depth of the groove to the thickness of the third conductive post is greater than 1 / 5.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The substrate has multiple active regions, which are electrically connected to the first conductive post, the second conductive post, and the third conductive post, respectively.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The core region has a gate within its substrate, and the gate is electrically connected to the third conductive pillar.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the capping layer includes: forming an initial capping layer covering the dielectric layer, the first conductive pillar, the second conductive pillar, the third upper conductive pillar, and the third lower conductive pillar; removing a portion of the initial capping layer to expose the top surfaces of the first conductive pillar, the second conductive pillar, and the third upper conductive pillar, with the remaining initial capping layer serving as the capping layer.

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