OLED display panel, manufacturing method thereof, and display terminal

Abstract

The present application discloses an OLED display panel, a preparation method thereof, and a display terminal. The OLED display panel includes an array substrate including a first auxiliary electrode, a second auxiliary electrode, a third auxiliary electrode, and an interlayer insulating layer. The interlayer insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode, and between the second auxiliary electrode and the third auxiliary electrode, and the second auxiliary electrode is arranged on the first auxiliary electrode; the third auxiliary electrode is arranged on the second auxiliary electrode; the third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode at the same time; a protective layer is arranged on the third auxiliary electrode, and the protective layer has an undercut opening, which is used to expose a portion of the third auxiliary electrode; an anode is arranged on the protective layer; a light-emitting functional layer is arranged on the anode; and a cathode is arranged on the light-emitting functional layer, and the cathode extends to the undercut opening and is connected to the third auxiliary electrode to improve the problem of uneven display caused by the large impedance of the cathode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an OLED display panel, a preparation method thereof, and a display terminal. Background Art

[0002] In flat panel display technology, organic light-emitting diode (OLED) displays have many advantages, such as being thin and light, actively emitting light, fast response speed, large viewing angle, wide color gamut, high brightness and low power consumption.

[0003] In existing OLED display panels, in order to increase the transmittance of top emission, the thickness of the metal cathode is relatively thin, resulting in a large square resistance and a serious current voltage drop (IR-drop). This leads to obvious brightness unevenness in the OLED display panel, seriously affecting the display effect of the OLED display device. Summary of the Invention

[0004] The object of the present invention is to provide an OLED display panel and a method for manufacturing the same, and a display terminal, so as to solve the technical problem that a thin cathode has a large impedance, resulting in poor display effects of the OLED display panel.

[0005] To achieve the above-mentioned objectives, the present invention provides an OLED display panel, comprising: an array substrate, comprising a first auxiliary electrode, a second auxiliary electrode, a third auxiliary electrode and an interlayer insulating layer, wherein the interlayer insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode, and between the second auxiliary electrode and the third auxiliary electrode, and the second auxiliary electrode is arranged on the first auxiliary electrode; the third auxiliary electrode is arranged on the second auxiliary electrode; wherein the third auxiliary electrode is simultaneously connected to the first auxiliary electrode and the second auxiliary electrode; a protective layer, which is arranged on the third auxiliary electrode, and the protective layer has an undercut opening, and the undercut opening is used to expose a portion of the third auxiliary electrode; an anode, which is arranged on the protective layer; a light-emitting functional layer, which is arranged on the anode; and a cathode, which is arranged on the light-emitting functional layer, and the cathode extends to the undercut opening and is connected to the third auxiliary electrode.

[0006] Furthermore, the third auxiliary electrode is connected to the first auxiliary electrode through at least one first conductive via; and the third auxiliary electrode is connected to the second auxiliary electrode through at least one second conductive via.

[0007] Furthermore, the third auxiliary electrode is connected to the first auxiliary electrode through two first conductive holes, one of the two first conductive holes is connected to one side of the first auxiliary electrode, and the other first conductive hole is connected to the other side of the first auxiliary electrode; wherein the second auxiliary electrode is located between the two first conductive holes.

[0008] Furthermore, the third auxiliary electrode is connected to the second auxiliary electrode through two of the second conductive vias at the same time.

[0009] Furthermore, the array substrate further includes: a light shielding layer, which is provided in the same layer as the first auxiliary electrode; a gate, which is provided in the same layer as the second auxiliary electrode; and a source and drain, which are provided in the same layer as the third auxiliary electrode.

[0010] Furthermore, the OLED display panel further includes: a substrate layer, the light-shielding layer and the first auxiliary electrode are arranged on the substrate layer; a buffer layer, which is arranged on the substrate layer and covers the light-shielding layer and the first auxiliary electrode; an active layer, which is arranged on the buffer layer, and the orthographic projection of the active layer on the substrate layer falls within the orthographic projection of the light-shielding layer on the substrate layer; a first gate insulating layer, which is correspondingly arranged on the active layer; a second gate insulating layer, which is correspondingly arranged on the buffer layer; the gate is correspondingly arranged on the first gate insulating layer, the second auxiliary electrode is correspondingly arranged on the second gate insulating layer, and the first gate insulating layer is correspondingly arranged on the second auxiliary electrode. The orthographic projections of the second auxiliary electrodes on the substrate layer at least partially overlap with the orthographic projection of the first auxiliary electrode on the substrate; a dielectric layer, which covers the gate and the second auxiliary electrode and extends onto the buffer layer; and the source and drain are arranged on the dielectric layer and connected to the active layer, and the third auxiliary electrode is arranged on the dielectric layer and is simultaneously connected to the first auxiliary electrode and the second auxiliary electrode, wherein the orthographic projection of the third auxiliary electrode on the substrate layer at least partially overlaps with the orthographic projection of the first auxiliary electrode on the substrate; wherein the interlayer insulating layer includes the buffer layer, the dielectric layer and the protective layer.

[0011] Furthermore, the protective layer includes: a passivation layer, which is arranged on the third auxiliary electrode, and the passivation layer is provided with a first through hole; and a flat layer, which is arranged on the passivation layer, and the flat layer is provided with a second through hole, the second through hole is connected to the first through hole, and the orthographic projection of the second through hole on the array substrate completely falls within the orthographic projection of the first through hole on the array substrate, so that the undercut opening is formed between the flat layer and the passivation layer.

[0012] Furthermore, the OLED display panel also includes: a pixel definition layer, which is arranged on the protective layer, the pixel definition layer is provided with a third through hole and a pixel opening, the third through hole is connected to the second through hole, and the pixel opening is used to expose the anode; wherein, the light-emitting functional layer is arranged on the anode and the pixel definition layer; the cathode is arranged on the light-emitting functional layer, extends to the third through hole, the undercut opening, and is connected to the third auxiliary electrode.

[0013] To achieve the above-mentioned objectives, the present invention also provides a method for preparing an OLED display panel, comprising the following steps: forming an array substrate, the steps of forming the array substrate comprising: forming a first metal layer; patterning the first metal layer to form a first auxiliary electrode; forming a second metal layer above the first metal layer; patterning the second metal layer to form a second auxiliary electrode; forming a third metal layer and above the second metal layer; and patterning the third metal layer to form a third auxiliary cathode; wherein an interlayer insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode and between the second auxiliary electrode and the third auxiliary electrode, and the third auxiliary electrode is simultaneously connected to the first auxiliary electrode and the second auxiliary electrode; forming a protective layer on the third auxiliary electrode and extending to the array substrate; performing a hole-digging process on the protective layer so that the protective layer forms an undercut opening, which is used to expose a portion of the third auxiliary electrode; forming an anode on the protective layer; forming a light-emitting functional layer on the anode; and forming a cathode on the light-emitting functional layer, the cathode extending to the undercut opening and connected to the third auxiliary electrode.

[0014] Furthermore, the step of forming the protective layer includes: forming a passivation layer on the third auxiliary electrode; and forming a flat layer on the passivation layer; the step of performing a hole-digging process on the protective layer includes: performing a hole-digging process on the flat layer and the passivation layer, so that a first through hole is formed in the passivation layer, a second through hole is formed in the flat layer, and the second through hole is connected to the first through hole; and

[0015] The passivation layer is etched by wet etching so that the orthographic projection of the second through hole on the array substrate completely falls within the orthographic projection of the first through hole on the array substrate, and the undercut opening is formed between the flat layer and the passivation layer.

[0016] Furthermore, in the step of forming the first auxiliary electrode, the first metal layer is patterned to form a light-shielding layer, and the light-shielding layer is arranged on the same layer as the first auxiliary electrode; in the step of forming the second auxiliary electrode, the second metal layer is patterned to form a gate, and the gate is arranged on the same layer as the second auxiliary electrode; and in the step of forming the third auxiliary cathode, the third metal layer is patterned to form a source and drain, and the source and drain are arranged on the same layer as the third auxiliary electrode.

[0017] To achieve the above object, the present invention further provides a display terminal, comprising a terminal body and the OLED display panel described in any one of the above embodiments, wherein the terminal body is connected to the display panel.

[0018] The technical effect of the present invention is to provide an OLED display panel and a manufacturing method thereof, and a display terminal, wherein a first auxiliary electrode, a second auxiliary electrode, and a third auxiliary electrode are formed on an array substrate in an insulated manner, and the third auxiliary electrode is simultaneously connected to the first auxiliary electrode and the second auxiliary electrode to form a cathode overlapping structure, and an undercut opening is opened in the protective layer, and the undercut opening is used to expose a portion of the third auxiliary electrode, so that the cathode is connected to the cathode overlapping structure to form a cathode overlapping area, thereby reducing the impedance of the cathode and reducing the voltage drop (IR Drop), so that the display brightness of each area of the OLED display panel is consistent, thereby further improving the display uniformity of the OLED display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0020] Figure 1 This is a schematic structural diagram of the OLED display panel provided in Example 1 of the present application.

[0021] Figure 2 This is a schematic structural diagram of the light-emitting functional layer provided in Example 1 of the present application.

[0022] Figure 3 This is a flow chart of the method for preparing an OLED display panel provided in Example 1 of the present application.

[0023] Figure 4 A flow chart of the steps for forming an array substrate provided in Example 1 of the present application.

[0024] Figure 5 This is a structural diagram of the array substrate provided in Example 1 of the present application.

[0025] Figure 6 This is a schematic diagram of the structure formed by the protective layer provided in Example 1 of the present application.

[0026] Figure 7 Flowchart for forming a protective layer provided in Example 1 of the present application.

[0027] Figure 8 This is a schematic structural diagram of the bottom cut opening provided in Example 1 of the present application.

[0028] Figure 9 Flow chart of the undercut opening provided in Example 1 of the present application.

[0029] Figure 10 This is a schematic diagram of the structure formed by the pixel definition layer provided in Example 1 of the present application.

[0030] Figure 11 This is a schematic structural diagram of the OLED display panel provided in Example 2 of the present application.

[0031] The components of the accompanying drawings are identified as follows:

[0032] 1. Array substrate; 2. Protective layer; 3. Anode; 4. Light-emitting functional layer; 5. Pixel definition layer; 6. Cathode; 11. Substrate layer; 12. First metal layer; 13. Buffer layer; 14. Active layer; 15. Gate insulating layer; 16. Second metal layer; 17. Dielectric layer; 18. Third metal layer; 121. First auxiliary electrode; 122. Light shielding layer; 141. Channel region; 142. Source contact region; 143. Drain contact region; 144. First storage capacitor electrode; 151. First gate insulating layer; 152. Second gate insulating layer; 161. Gate; 16 2. Second auxiliary electrode; 181. Source electrode; 182. Drain electrode; 183. Third auxiliary electrode; 184. Second storage capacitor electrode; 21. Passivation layer; 22. Flat layer; 41. Hole injection layer; 42. Hole transport layer; 43. Light-emitting layer; 44. Electron transport layer; 45. Electron injection layer; 71. First conductive hole; 72. Second conductive hole; 73. Third conductive hole; 74. Fourth conductive hole; 91. First through hole; 92. Second through hole; 93. Third through hole; 94. Fourth through hole; 95. Fifth through hole; 96. Pixel opening; 10. Undercut opening. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0034] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0035] Example 1

[0036] like Figure 1 As shown, this embodiment provides an OLED display panel, which includes an array substrate 1, a protective layer 2, an anode 3, a pixel definition layer 5, a light-emitting functional layer 4 and a cathode 6.

[0037] The array substrate 1 includes a substrate layer 11 , a first metal layer 12 , a buffer layer 13 , an active layer 14 , a gate insulating layer 15 , a second metal layer 16 , a dielectric layer 17 and a third metal layer 18 .

[0038] The substrate layer 11 may be a flexible substrate, and the material used may be polyimide (PI) or polydimethylsiloxane (PDMS), which is not particularly limited herein.

[0039] The first metal layer 12 is disposed on the upper surface of the substrate layer 11 . The first metal layer 12 includes a patterned light shielding layer 122 and a first auxiliary electrode 121 . The light shielding layer 122 and the first auxiliary electrode 121 are disposed in the same layer.

[0040] The buffer layer 13 covers the first auxiliary electrode 121 and the light shielding layer 122 and extends to the upper surface of the substrate layer 11 .

[0041] The semiconductor layer includes an active layer 14 and a first storage capacitor electrode 144. Both the active layer 14 and the first storage capacitor electrode 144 are disposed on the upper surface of the buffer layer 13. The orthographic projection of the active layer 14 on the substrate layer 11 falls within the orthographic projection of the light shielding layer 122 on the substrate layer 11. The active layer 14 includes a channel region 141 and a source 181 contact region 142 and a drain 182 contact region 143 disposed on either side of the channel region 141. The active layer 14 and the first storage capacitor electrode 144 are spaced apart, and the light shielding layer 122 and the first storage capacitor electrode 144 are disposed correspondingly to form a first storage capacitor.

[0042] In this embodiment, the source 181 contact region 142, the drain 182 contact region 143, and the first storage capacitor electrode 144 of the active layer 14 are all ion-doped regions with conductive properties; the channel region 141 is an undoped region with semiconductor properties. In one embodiment, the material of the active layer 14 may be an oxide semiconductor material, such as indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO). In another embodiment, the material of the active layer 14 may also be amorphous silicon, single crystal silicon, low-temperature polysilicon, or the like.

[0043] The gate insulating layer 15 includes a first gate insulating layer 151 and a second gate insulating layer 152 provided in different layers. The first gate insulating layer 151 is correspondingly provided on the upper surface of the active layer 14 , and the second gate insulating layer 152 is correspondingly provided on the upper surface of the buffer layer 13 .

[0044] The second metal layer 16 is disposed on the upper surface of the gate insulating layer 15 and includes a patterned gate 161 and a second auxiliary electrode 162. The gate 161 and the second auxiliary electrode 162 are formed in the same process step, that is, the gate 161 and the second auxiliary electrode 162 are disposed on the same layer. Specifically, the gate 161 is disposed on the upper surface of the first gate insulating layer 151, and the second auxiliary electrode 162 is disposed on the upper surface of the second gate insulating layer 152. The orthographic projection of the second auxiliary electrode 162 on the substrate layer 11 at least partially overlaps with the orthographic projection of the first auxiliary electrode 121 on the substrate.

[0045] The dielectric layer 17 is disposed on the second metal layer 16 . The dielectric layer 17 covers the gate 161 and the second auxiliary electrode 162 , and extends to the upper surface of the buffer layer 13 .

[0046] The third metal layer 18 is disposed on the upper surface of the dielectric layer 17 and includes a patterned source and drain electrode 182, a third auxiliary electrode 183, and a second storage capacitor electrode 184. The source and drain electrode 182 is disposed on the same layer as the third auxiliary electrode 183 and the second storage capacitor electrode 184. Specifically, the source and drain electrode 182 is disposed on the dielectric layer 17 and connected to the active layer 14. The third auxiliary electrode 183 is disposed on the dielectric layer 17 and is simultaneously connected to the first auxiliary electrode 121 and the second auxiliary electrode 162. The orthographic projection of the third auxiliary electrode 183 on the substrate layer 11 at least partially overlaps with the orthographic projection of the first auxiliary electrode 121 on the substrate. In this embodiment, the source and drain electrode 182 includes a source electrode 181 and a drain electrode 182. The source electrode 181 is connected to one side of the active layer 14, and the drain electrode 182 is connected to the other side of the active layer 14. The source electrode 181 is connected to the active layer 14 through a third conductive via 73. The drain electrode 182 is connected to the active layer 14 through the third conductive via 73 and to the light shielding layer 122 through the fourth conductive via 74, thereby improving the electrical performance of the TFT and making the channel current more stable. The light shielding layer 122 is arranged corresponding to the first storage capacitor electrode 144, and the first storage capacitor electrode 144 is arranged corresponding to the second storage capacitor electrode 184 to form a second storage capacitor.

[0047] In this embodiment, the materials of the first metal layer 12, the second metal layer 16, and the third metal layer 18 can be independently selected from one or more metals, alloys, and metal nitrides, such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd), or alloys or nitrides of the above metals. These materials can be used alone or in combination.

[0048] The protective layer 2 is disposed on the third metal layer 18, covering the source / drain 182 and the third auxiliary electrode 183, and extending to the upper surface of the dielectric layer 17. Specifically, the protective layer 2 includes a passivation layer 21 and a planarization layer 22. The passivation layer 21 is disposed on the third auxiliary electrode 183 and defines a first through-hole 91. The planarization layer 22 is disposed on the passivation layer 21 and defines a second through-hole 92. The second through-hole 92 communicates with the first through-hole 91, and a portion of the planarization layer 22 extends into the first through-hole 91, thereby forming an undercut opening 10 between the planarization layer 22 and the passivation layer 21. The undercut opening 10 is used to expose a portion of the third auxiliary electrode 183. In this embodiment, the bottom diameter of the second through hole 92 is smaller than the top diameter of the first through hole 91. This arrangement ensures that the orthographic projection of the second through hole 92 on the array substrate 1 completely falls within the orthographic projection of the first through hole 91 on the array substrate 1, thereby forming an undercut opening 10 between the planar layer 22 and the passivation layer 21. Preferably, the orthographic projection of the second through hole 92 on the substrate layer 11 is smaller than the orthographic projection of the first through hole 91 on the substrate layer 11. This arrangement further ensures that at least a portion of the planar layer 22 can extend into the first through hole 91, thereby forming an undercut opening 10 between the planar layer 22 and the passivation layer 21.

[0049] In this embodiment, the buffer layer 13, the gate insulating layer 15, the dielectric layer 17, and the protective layer 2 can be made of one or more materials selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy). It should be noted that the buffer layer 13, the dielectric layer 17, and the protective layer 2 collectively constitute interlayer insulating layers between the first auxiliary electrode 121 and the second auxiliary electrode 162, and between the second auxiliary electrode 162 and the third auxiliary electrode 183.

[0050] The anode 3 is disposed on the protection layer 2 and connected to the source and drain electrodes 182. The material of the anode 3 can be a transparent conductive metal oxide, such as indium tin oxide (ITO).

[0051] The pixel definition layer 5 is disposed on the protective layer 2 . Specifically, the pixel definition layer 5 is provided with a third through hole 93 and a pixel opening 96 . The third through hole 93 is connected to the second through hole 92 . The pixel opening 96 is used to expose the anode 3 .

[0052] The light-emitting functional layer 4 is disposed on the anode 3 and the pixel definition layer 5 and is discontinuously disposed at the undercut opening 10, i.e., part of the light-emitting functional layer 4 can be connected to the third auxiliary electrode 183 located at the undercut opening 10, while other parts of the light-emitting functional layer 4 cannot be connected to the third auxiliary electrode 183 located at the undercut opening 10. In other words, the undercut opening 10 can discontinuing some of the film layers located above it. In this embodiment, Figure 2As shown, the light-emitting functional layer 4 includes, from bottom to top, a hole injection layer 41, a hole transport layer 42, a light-emitting layer 43, an electron transport layer 44, and an electron injection layer 45. The structure of the light-emitting functional layer 4 can refer to the structure of existing OLED light-emitting devices and will not be described in detail here.

[0053] Combine Figure 1 As shown, the cathode 6 is arranged on the light-emitting functional layer 4, and the cathode 6 extends to the bottom cut opening 10 and is connected to the third auxiliary electrode 183. The pattern of the cathode 6 is the same as the pattern of the light-emitting functional layer 4. The material of the cathode 6 can be a metal or an alloy, such as silver or a magnesium-silver alloy. It can be understood that the cathode 6 has a light-transmitting property so that the light emitted by the light-emitting layer 43 can be emitted through the cathode 6, that is, the OLED display panel provided in this embodiment is a top-emitting OLED display panel. Exemplarily, the transmittance of the cathode 6 is greater than 30%, for example, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 95%, 99%, etc.

[0054] In this embodiment, the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through at least one first conductive via 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through at least one second conductive via 72. Each first conductive via 71 penetrates from the dielectric layer 17 to the buffer layer 13 and is connected to the first auxiliary electrode 121. Each second conductive via 72 penetrates the dielectric layer 17 and is connected to the second auxiliary electrode 162.

[0055] The third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through a first conductive via 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through a second conductive via 72. In this arrangement, the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode 6 overlap structure, which can reduce the impedance of the cathode 6 and improve the display uniformity of the OLED display panel.

[0056] like Figure 3 As shown, this embodiment also provides a method for preparing an OLED display panel, including the following steps S1) to S7).

[0057] S1) forms an array substrate 1, and the steps of forming the array substrate 1 include: forming a first metal layer 12; patterning the first metal layer 12 to form a first auxiliary electrode 121; forming a second metal layer 16 above the first metal layer 12; patterning the second metal layer 16 to form a second auxiliary electrode 162; forming a third metal layer 18 above the second metal layer 16; patterning the third metal layer 18 to form a third auxiliary cathode 6; wherein an interlayer insulating layer is formed between the first auxiliary electrode 121 and the second auxiliary electrode 162, and between the second auxiliary electrode 162 and the third auxiliary electrode 183, and the third auxiliary electrode 183 is simultaneously connected to the first auxiliary electrode 121 and the second auxiliary electrode 162.

[0058] During the step of forming the first auxiliary electrode 121, the first metal layer 12 is patterned to form a light shielding layer 122, and the light shielding layer 122 is provided on the same layer as the first auxiliary electrode 121. During the step of forming the second auxiliary electrode 162, the second metal layer 16 is patterned to form a gate electrode 161, and the gate electrode 161 is provided on the same layer as the second auxiliary electrode 162. During the step of forming the third auxiliary cathode 6, the third metal layer 18 is patterned to form a source and drain electrode 182, and the source and drain electrode 182 is provided on the same layer as the third auxiliary electrode 183.

[0059] Specifically, such as Figure 4 As shown, the steps of forming the array substrate 1 specifically include S11)-S111).

[0060] S11) forming a first metal layer 12 disposed on the upper surface of the substrate layer 11, referring to Figure 5 Specifically, a metal material is deposited on the upper surface of the substrate layer 11 to form the first metal layer 12. The metal material may be aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), or other metals, or alloys or nitrides thereof. These materials may be used alone or in combination.

[0061] S12) Patterning the first metal layer 12 to form a light shielding layer 122 and a first auxiliary electrode 121 disposed on the same layer. Figure 5 .

[0062] S13) forming a buffer layer 13 on the first auxiliary electrode 121 and the light shielding layer 122, and extending to the upper surface of the substrate layer 11, referring to Figure 5Specifically, an inorganic material is deposited on the upper surface of the first auxiliary electrode 121 and the light shielding layer 122 to form a buffer layer 13. The buffer layer 13 covers the first auxiliary electrode 121 and the light shielding layer 122 and extends to the upper surface of the substrate layer 11. The inorganic material can be selected from one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0063] S14) forming an active layer 14 and a first storage capacitor electrode 144 on the buffer layer 13, referring to Figure 5 Specifically, an active layer 14 and a first storage capacitor electrode 144 are formed on the upper surface of the buffer layer 13. The orthographic projection of the active layer 14 on the substrate layer 11 falls within the orthographic projection of the light shielding layer 122 on the substrate layer 11, wherein the active layer 14 includes a channel region 141 and a source contact region 142 and a drain contact region 143 provided on both sides of the channel region 141. The active layer 14 and the first storage capacitor electrode 144 are spaced apart, and the light shielding layer 122 and the first storage capacitor electrode 144 are provided correspondingly, and form a first storage capacitor.

[0064] In this embodiment, the source contact region 142, drain contact region 143, and first storage capacitor electrode 144 of the active layer 14 are all ion-doped regions with conductive properties; the channel region 141 is an undoped region with semiconductor properties. In one embodiment, the material of the active layer 14 may be an oxide semiconductor material, such as indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO). In another embodiment, the material of the active layer 14 may also be amorphous silicon, single crystal silicon, low-temperature polysilicon, or the like.

[0065] S15) forming a gate insulating layer 15 on the active layer 14 and the buffer layer 13, referring to Figure 5 Specifically, in the same process step, a first gate insulating layer 151 is formed on the upper surface of the active layer 14, and a second gate insulating layer 152 is formed on the upper surface of the buffer layer 13. The material of the gate insulating layer 15 can be selected from one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0066] S16) forming a second metal layer 16 on the gate insulating layer 15, referring to Figure 5 Specifically, a metal material is deposited on the upper surface of the gate insulating layer 15 to form the second metal layer 16. The metal material can be aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), or other metals, or alloys or nitrides of the above metals. These materials can be used alone or in combination.

[0067] S17) Patterning the second metal layer 16 to form a gate electrode 161 and a second auxiliary electrode 162 disposed on the same layer. Figure 5 Specifically, the gate 161 is correspondingly arranged on the upper surface of the first gate insulating layer 151, and the second auxiliary electrode 162 is correspondingly arranged on the upper surface of the second gate insulating layer 152, and the orthographic projection of the second auxiliary electrode 162 on the substrate layer 11 at least partially overlaps with the orthographic projection of the first auxiliary electrode 121 on the substrate.

[0068] S18) Form a dielectric layer 17 on the gate electrode 161 and the second auxiliary electrode 162, referring to Figure 5 Specifically, in the same process step, a dielectric layer 17 is formed on the upper surface of the gate electrode 161 and the second auxiliary electrode 162. The dielectric layer 17 covers the gate electrode 161 and the second auxiliary electrode 162 and extends to the upper surface of the buffer layer 13. The material of the dielectric layer 17 can be selected from one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0069] S19) The dielectric layer 17 is subjected to two hole-digging processes to form a first conductive hole 71, a second conductive hole 72, a third conductive hole 73 and a fourth conductive hole 74. Figure 5 Specifically, during the first hole-digging process, a first conductive hole 71 and a fourth conductive hole 74 are formed. The first conductive hole 71 penetrates the dielectric layer 17 and the buffer layer 13 and exposes a portion of the surface of the first auxiliary electrode 121. The fourth conductive hole 74 penetrates the dielectric layer 17 and the buffer layer 13 and exposes a portion of the surface of the light-shielding layer 122. During the second hole-digging process, a second conductive hole 72 and a third conductive hole 73 are formed. The second conductive hole 72 penetrates the dielectric layer 17 and exposes a portion of the surface of the second auxiliary electrode 162. The third conductive hole 73 penetrates the dielectric layer 17 and exposes a portion of the surface of the active layer 14. That is, when the dielectric layer 17 is subjected to two hole-digging processes, deep holes, namely the first conductive hole 71 and the fourth conductive hole 74, are formed first, and then shallow holes, namely the second conductive hole 72 and the third conductive hole 73, are formed.

[0070] S110) Form a third metal layer 18 on the dielectric layer 17. Specifically, a metal material is deposited on the upper surface of the dielectric layer 17 to form the third metal layer 18, wherein the metal material fills the first conductive hole 71, the second conductive hole 72, the third conductive hole 73 and the fourth conductive hole 74 respectively. Figure 6 The metal material may be aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), neodymium (Nd), or other metals, or alloys or nitrides thereof, and these materials may be used alone or in combination.

[0071] S111) The third metal layer 18 is patterned to form a source / drain 182, a third auxiliary electrode 183 and a second storage capacitor electrode 184 arranged on the same layer. Figure 6 . Specifically, the source and drain electrodes 182 are arranged on the dielectric layer 17 and connected to the active layer 14, and the third auxiliary electrode 183 is arranged on the dielectric layer 17 and is simultaneously connected to the first auxiliary electrode 121 and the second auxiliary electrode 162, wherein the orthographic projection of the third auxiliary electrode 183 on the substrate layer 11 at least partially overlaps with the orthographic projection of the first auxiliary electrode 121 on the substrate. In this embodiment, the source and drain electrodes 182 include a source electrode 181 and a drain electrode 182, the source electrode 181 is connected to one side of the active layer 14, and the drain electrode 182 is connected to the other side of the active layer 14, wherein the source electrode 181 and the drain electrode 182 are connected to the active layer 14 through the third conductive hole 73. The source electrode 181 is connected to the active layer 14 through the third conductive hole 73 and is connected to the light shielding layer 122 through the fourth conductive hole 84, which can improve the electrical performance of the TFT and make the channel current more stable. The light shielding layer 122 is disposed corresponding to the first storage capacitor electrode 144 , and the first storage capacitor electrode 144 is disposed corresponding to the second storage capacitor electrode 184 to form a second storage capacitor.

[0072] S2) forming a protective layer 2 on the third auxiliary electrode 183 and extending to the array substrate 1, referring to Figure 6 .

[0073] like Figure 7 As shown, the steps of forming the protective layer 2 include S21)-S22.

[0074] S21) forming a passivation layer 21 on the third auxiliary electrode 183, referring to Figure 6 Specifically, a passivation layer 21 is formed on the third auxiliary electrode 183 , and the material of the passivation layer 21 can be selected from one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0075] S22) forming a flat layer 22 on the passivation layer 21, referring to Figure 6 Specifically, a planar layer 22 is formed on the passivation layer 21 , and a material of the planar layer 22 may be selected from one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0076] S3) The protective layer 2 is subjected to a hole-digging process so that an undercut opening 10 is formed in the protective layer 2. The undercut opening 10 is used to expose a portion of the third auxiliary electrode 183. Figure 8 .

[0077] like Figure 9 As shown, the step of performing hole-digging processing on the protective layer 2 includes S31)-S32).

[0078] S31) The flat layer 22 and the passivation layer 21 are subjected to a hole-digging process, so that the passivation layer 21 is formed with a first through hole 91, and the flat layer 22 is formed with a second through hole 92, and the second through hole 92 is connected to the first through hole 91. Figure 8 Specifically, when the planar layer 22 and the passivation layer 21 are drilled, a fourth through hole 94 is formed in the passivation layer 21 , and a fifth through hole 95 is formed in the planar layer 22 . The fifth through hole 95 is connected to the fourth through hole 94 and exposes the surface of the active layer 14 .

[0079] S32) Wet etching is performed on the passivation layer 21 so that the orthographic projection of the second through hole 92 on the array substrate 1 completely falls within the orthographic projection of the first through hole 91 on the array substrate 1, and the undercut opening 10 is formed between the flat layer 22 and the passivation layer 21. Figure 8 . Specifically, the area where the undercut opening 10 is located is defined by a yellow light process, and then the passivation layer 21 is etched by wet etching, so that the undercut opening 10 is formed between the flat layer 22 and the passivation layer 21. It should be noted that, except for the area where the undercut opening 10 is located, other areas are protected by photoresist and will not be affected by the etching solution. The undercut opening 10 is used to expose part of the third auxiliary electrode 183. In this embodiment, the bottom aperture of the second through hole 92 is smaller than the top aperture of the first through hole 91. Such an arrangement can form an undercut opening 10 between the flat layer 22 and the passivation layer 21. Preferably, the orthographic projection aperture of the second through hole 92 on the substrate layer 11 is smaller than the orthographic projection aperture of the first through hole 91 on the substrate layer 11. Such an arrangement can further ensure that at least part of the flat layer 22 can extend into the first through hole 91, so that an undercut opening 10 is formed between the flat layer 22 and the passivation layer 21.

[0080] S4) forming an anode 3 on the protective layer 2, referring to Figure 8 Specifically, a transparent conductive metal oxide is deposited on the protective layer 2 through a yellow light process to form the anode 3. The transparent conductive metal oxide completely fills the fourth through hole 94 and the fifth through hole 95, so that the anode 3 is connected to the source electrode 181 after formation. The transparent conductive metal oxide can be indium tin oxide (ITO).

[0081] In other embodiments, steps S4) and S32) can be interchanged, as long as the undercut opening 10 can be formed between the planar layer 22 and the passivation layer 21 and the anode 3 is formed on the protective layer 2 .

[0082] S5) A pixel definition layer 5 is formed on the protective layer 2. The pixel definition layer 5 is provided with a third through hole 93 and a pixel opening 96. The third through hole 93 is connected to the second through hole 92. The pixel opening 96 is used to expose the anode 3. Figure 10 .

[0083] S6) forming a light-emitting functional layer 4 on the anode 3, referring to Figure 1 Specifically, a light-emitting functional layer 4 is formed on the anode 3 and the pixel definition layer 5, and is intermittently provided at the undercut opening 10, that is, part of the light-emitting functional layer 4 can be connected to the third auxiliary electrode 183 located at the undercut opening 10, and other parts of the light-emitting functional layer 4 cannot be connected to the third auxiliary electrode 183 located at the undercut opening 10, that is, the undercut opening 10 can interrupt some of the film layers located above it. In this embodiment, the light-emitting functional layer 4 includes, from bottom to top, a hole injection layer 41, a hole transport layer 42, a light-emitting layer 43, an electron transport layer 44, and an electron injection layer 45, see Figure 2 .

[0084] S7) forming a cathode 6 on the light-emitting functional layer 4, wherein the cathode 6 extends to the undercut opening 10 and is connected to the third auxiliary electrode 183, Figure 1 . Specifically, a cathode 6 is formed on the light-emitting functional layer 4, and the cathode 6 extends to the bottom cut opening 10 and is connected to the third auxiliary electrode 183. The pattern of the cathode 6 is the same as the pattern of the light-emitting functional layer 4. The material of the cathode 6 can be a metal or an alloy, such as silver or a magnesium-silver alloy. It can be understood that the cathode 6 has a light-transmitting property so that the light emitted by the light-emitting layer 43 can be emitted through the cathode 6, that is, the OLED display panel provided in this embodiment is a top-emitting OLED display panel. Exemplarily, the transmittance of the cathode 6 is greater than 30%, such as 30%, 40%, 50%, 60%, 70%, 80%, 90%, 95%, 99%, etc.

[0085] Combine Figure 2 As shown, the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through a first conductive via 81, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through a second conductive via 82. In this arrangement, the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode 6 overlap structure, which can reduce the impedance of the cathode 6 and improve the display uniformity of the OLED display panel.

[0086] This embodiment further provides a display terminal, which includes a terminal body and the OLED display panel mentioned above, wherein the terminal body is connected to the display panel.

[0087] Example 2

[0088] This embodiment provides an OLED display panel, a method for manufacturing the same, and a display terminal, which include all the technical solutions of Example 1, except that the second auxiliary electrode 162 is located between the two first conductive holes 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through the two second conductive holes 72 at the same time.

[0089] like Figure 11 As shown, the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through two first conductive vias 71. One of the two first conductive vias 71 is connected to one side of the first auxiliary electrode 121, and the other first conductive via 71 is connected to the other side of the first auxiliary electrode 121. The second auxiliary electrode 162 is located between the two first conductive vias 71, and the third auxiliary electrode 183 is simultaneously connected to the second auxiliary electrode 162 through two second conductive vias 72. In this arrangement, the third auxiliary electrode 183 is connected in parallel with the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode 6 overlap structure, which can further reduce the impedance of the cathode 6, thereby reducing the voltage drop (IR Drop) and improving the display uniformity of the OLED display panel. In this embodiment, the second auxiliary electrode 162 is located between the two first conductive vias 71. This arrangement can save the space occupied by the conductive vias within the array substrate 1 and improve the PPI. In other embodiments, the two second conductive vias 72 may be disposed on the left or right side of the gate insulating layer 15 , as long as the third auxiliary electrode 183 , the second auxiliary electrode 162 , and the first auxiliary electrode 121 form a parallel circuit.

[0090] Combine Figure 1 and Figure 11 As shown, Figure 11 The cathode 6 lap structure and Figure 1 Compared with the cathode 6 lap structure, Figure 11 The third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through two first conductive holes 71, and is connected to the second auxiliary electrode 162 through two second conductive holes 72. Figure 1 The third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through a first conductive hole 71 and is connected to the second auxiliary electrode 162 through a second conductive hole 72. Figure 11 The impedance ratio of the cathode 6 lap structure is Figure 1 The impedance of the cathode 6 overlap structure is smaller and the voltage drop is smaller. In other words, Figure 11The cathode 6 overlap structure in the embodiment has a better effect of reducing the cathode 6 impedance, thereby helping to further improve the problem of uneven screen display.

[0091] Therefore, the OLED display panel provided in this embodiment forms an insulated first auxiliary electrode 121, a second auxiliary electrode 162, and a third auxiliary electrode 183 on the array substrate 1, and the third auxiliary electrode 183 is simultaneously connected to the first auxiliary electrode 121 and the second auxiliary electrode 162 to form a parallel-connected cathode 6 overlapping structure, and an undercut opening 10 is opened in the protective layer 2. The undercut opening 10 is used to expose a portion of the third auxiliary electrode 183, so that the cathode 6 is connected to the cathode overlapping structure to form a cathode overlapping area, thereby further reducing the impedance of the cathode 6, reducing the voltage drop (IR Drop), and further improving the display uniformity of the OLED display panel.

[0092] This embodiment also provides a method for manufacturing an OLED display panel, which includes all the technical solutions of the method for manufacturing an OLED display panel of Example 1. The difference is that when the dielectric layer 17 is drilled, two first conductive vias 71 and two second conductive vias 72 are formed, so that the third auxiliary electrode 183 is connected to the first auxiliary electrode 121 through the two first conductive vias 71, and the third auxiliary electrode 183 is connected to the second auxiliary electrode 162 through the two second conductive vias 72. One of the two first conductive vias 71 is connected to one side of the first auxiliary electrode 121, and the other first conductive via 71 is connected to the other side of the first auxiliary electrode 121. The second auxiliary electrode 162 is located between the two first conductive vias 71, and each second conductive via 72 is connected to the second auxiliary electrode 162. In this arrangement, the third auxiliary electrode 183 is connected in parallel with the second auxiliary electrode 162 and the first auxiliary electrode 121 to form a cathode 6 overlap structure, which can further reduce the impedance of the cathode 6, thereby reducing the voltage drop (IR drop) and improving the display uniformity of the OLED display panel. In this embodiment, the second auxiliary electrode 162 is located between the two first conductive vias 71. This arrangement can save space occupied by the conductive vias within the array substrate 1. In other embodiments, the two second conductive vias 72 can be located on either the left or right side of the gate insulating layer 15, as long as the third auxiliary electrode 183 forms a parallel circuit with the second auxiliary electrode 162 and the first auxiliary electrode 121.

[0093] The above is a detailed introduction to an OLED display panel, a preparation method thereof, and a display terminal provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An OLED display panel, characterized in that: include: An array substrate comprising a first auxiliary electrode, a second auxiliary electrode, a third auxiliary electrode, and an interlayer insulating layer, wherein the interlayer insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode, and between the second auxiliary electrode and the third auxiliary electrode, and the second auxiliary electrode is disposed on the first auxiliary electrode; and the third auxiliary electrode is disposed on the second auxiliary electrode. a protective layer disposed on the third auxiliary electrode, wherein the protective layer is provided with an undercut opening, wherein the undercut opening is used to expose a portion of the third auxiliary electrode; an anode disposed on the protective layer; a light-emitting functional layer, which is disposed on the anode; as well as a cathode disposed on the light-emitting functional layer, the cathode extending to the undercut opening and connected to the third auxiliary electrode; The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode at the same time. The third auxiliary electrode is connected to the first auxiliary electrode through at least one first conductive hole, and is connected to the second auxiliary electrode through at least one second conductive hole.

2. The OLED display panel according to claim 1, wherein: The third auxiliary electrode is connected to the first auxiliary electrode through two first conductive vias, one of the two first conductive vias is connected to one side of the first auxiliary electrode, and the other first conductive via is connected to the other side of the first auxiliary electrode; Wherein, the second auxiliary electrode is located between two of the first conductive holes.

3. The OLED display panel according to claim 1, wherein: The third auxiliary electrode is connected to the second auxiliary electrode through two of the second conductive vias.

4. The OLED display panel according to any one of claims 1 to 3, wherein: The array substrate further includes: a light shielding layer, which is provided on the same layer as the first auxiliary electrode; a gate electrode, which is provided in the same layer as the second auxiliary electrode; and The source and drain electrodes are arranged in the same layer as the third auxiliary electrode.

5. The OLED display panel according to claim 4, wherein: Also includes: a substrate layer, on which the light shielding layer and the first auxiliary electrode are disposed; a buffer layer, disposed on the substrate layer and covering the light shielding layer and the first auxiliary electrode; an active layer disposed on the buffer layer, wherein an orthographic projection of the active layer on the substrate layer falls within an orthographic projection of the light shielding layer on the substrate layer; a first gate insulating layer, which is correspondingly disposed on the active layer; a second gate insulating layer, which is correspondingly disposed on the buffer layer; The gate is correspondingly disposed on the first gate insulating layer, the second auxiliary electrode is correspondingly disposed on the second gate insulating layer, and an orthographic projection of the second auxiliary electrode on the substrate layer at least partially overlaps with an orthographic projection of the first auxiliary electrode on the substrate; a dielectric layer covering the gate and the second auxiliary electrode and extending onto the buffer layer; as well as The source and drain electrodes are disposed on the dielectric layer and connected to the active layer, and the third auxiliary electrode is disposed on the dielectric layer and connected to both the first auxiliary electrode and the second auxiliary electrode, wherein an orthographic projection of the third auxiliary electrode on the substrate layer at least partially overlaps with an orthographic projection of the first auxiliary electrode on the substrate; The interlayer insulating layer includes the buffer layer, the dielectric layer and the protective layer.

6. The OLED display panel according to any one of claims 1 to 3, wherein: The protective layer comprises: a passivation layer, which is disposed on the third auxiliary electrode, and the passivation layer is provided with a first through hole; and A flat layer is disposed on the passivation layer, wherein a second through hole is opened in the flat layer, the second through hole is connected to the first through hole, and the orthographic projection of the second through hole on the array substrate completely falls within the orthographic projection of the first through hole on the array substrate, so that the undercut opening is formed between the flat layer and the passivation layer.

7. The OLED display panel according to claim 6, wherein: Also includes: a pixel definition layer disposed on the protective layer, the pixel definition layer being provided with a third through hole and a pixel opening, the third through hole being connected to the second through hole, and the pixel opening being used to expose the anode; The light-emitting functional layer is disposed on the anode and the pixel definition layer; the cathode is disposed on the light-emitting functional layer, extends to the third through hole and the undercut opening, and is connected to the third auxiliary electrode.

8. A method for preparing an OLED display panel, characterized in that: include: An array substrate is formed, the steps of forming the array substrate comprising: forming a first metal layer; patterning the first metal layer to form a first auxiliary electrode; forming a second metal layer above the first metal layer; patterning the second metal layer to form a second auxiliary electrode; forming a third metal layer above the second metal layer; and patterning the third metal layer to form a third auxiliary cathode; wherein an interlayer insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode and between the second auxiliary electrode and the third auxiliary electrode, and the third auxiliary electrode is connected to both the first auxiliary electrode and the second auxiliary electrode; forming a protective layer on the third auxiliary electrode and extending onto the array substrate; Performing a hole-digging process on the protective layer so that an undercut opening is formed in the protective layer, wherein the undercut opening is used to expose a portion of the third auxiliary electrode; forming an anode on the protective layer; forming a light-emitting functional layer on the anode; and A cathode is formed on the light-emitting functional layer, wherein the cathode extends to the undercut opening and is connected to the third auxiliary electrode.

9. The method for preparing an OLED display panel according to claim 8, wherein: The step of forming the protective layer comprises: forming a passivation layer on the third auxiliary electrode; and forming a planar layer on the passivation layer; The step of performing a hole-digging process on the protective layer includes: Performing a hole-digging process on the planar layer and the passivation layer, so that a first through hole is formed in the passivation layer and a second through hole is formed in the planar layer, and the second through hole is connected to the first through hole; and The passivation layer is etched by wet etching so that the orthographic projection of the second through hole on the array substrate completely falls within the orthographic projection of the first through hole on the array substrate, and the undercut opening is formed between the flat layer and the passivation layer.

10. The method for preparing an OLED display panel according to claim 8, wherein: In the step of forming the first auxiliary electrode, the first metal layer is patterned to form a light shielding layer, and the light shielding layer is provided on the same layer as the first auxiliary electrode; In the step of forming the second auxiliary electrode, the second metal layer is patterned to form a gate, and the gate is provided in the same layer as the second auxiliary electrode; and In the step of forming the third auxiliary cathode, the third metal layer is patterned to form source and drain electrodes, and the source and drain electrodes are provided in the same layer as the third auxiliary electrode.

11. A display terminal, characterized in that: The display terminal includes a terminal body and the OLED display panel according to any one of claims 1 to 7, wherein the terminal body is connected to the display panel.

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