A vertical OECT based on porous semiconductor channel and its preparation method

Abstract

The present invention discloses an OECT based on a porous semiconductor channel and a preparation method thereof, which mainly includes a substrate, a source electrode, a porous semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode. During the preparation process, a substrate is first prepared in a vertical structure, and the substrate is cleaned and dried. Then, a source electrode is prepared on the substrate, a porous semiconductor layer is prepared on the source electrode, a drain electrode is prepared on the porous semiconductor layer, an encapsulation layer is prepared on the substrate, and the overlapping portion between the drain electrode and the source electrode is exposed. An electrolyte layer is prepared above the drain electrode, and finally a gate electrode connected to the electrolyte layer is prepared.

Description

Technical Field

[0001] The present invention belongs to the technical field of organic electrochemical transistors, and more specifically, relates to a vertical OECT based on a porous semiconductor channel and a preparation method thereof. Background Art

[0002] Organic electrochemical transistors (OECTs) can be used in bioelectronics, wearable electronics, and artificial neural electronics due to their low driving voltage (<1V), low power consumption (<μW), high transconductance (>10mS), and excellent mechanical flexibility and stretchability. In OECTs, the biggest difference from traditional field-effect transistors is that the semiconductor that constitutes the channel has the ability to conduct both ions and electrons / holes. Therefore, when an electrolyte is used as the dielectric layer, the ions in the electrolyte can be injected / precipitated into the body of the semiconductor under the action of the gate bias, forming a high-voltage gate current of up to μF / cm 2 Therefore, it is possible to achieve extremely high transconductance (>10mS) at an extremely low driving voltage (<1V).

[0003] In addition, compared with traditional transistors, OECTs have the advantages of high sensitivity, miniaturization, high-throughput sensing, flexibility, and biocompatibility. In addition, organic materials themselves have the advantages of light weight, low cost, flexibility, simple preparation methods, and a wide variety of types. Compared with traditional silicon-based metal oxide semiconductor field-effect transistors, the preparation process uses simple processes such as low-temperature deposition or solution (inkjet printing, spin coating, drop coating, etc.) instead of the traditional high-temperature vacuum deposition method to make devices. Therefore, it has great application potential in weak signal amplification, biological signal detection / monitoring, and brain-like neural systems. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a vertical OECT based on a porous semiconductor channel and its preparation method, which on the one hand further promotes the effective doping of ions in the semiconductor, and on the other hand ensures that the device has a short channel of microns or less. By constructing a porous semiconductor channel prepared by a solution method, not only is the low-cost large-area preparation of the vertical OECT achieved, but the porous structure also introduces an effective ion transmission path, avoiding the obstruction of the electrode (drain electrode) on the vertical structure to ion transmission. In addition, this vertical structure will effectively avoid the morphological degradation of the semiconductor in repeated doping cycles, and can achieve OECTs with high cycle stability.

[0005] To achieve the above-mentioned object of the invention, the present invention provides an OECT based on a porous semiconductor channel, characterized by comprising: a substrate, a source electrode, a porous semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode;

[0006] A rectangular strip source electrode is arranged in the center of the substrate, and a square porous semiconductor layer is arranged at the center of the source electrode, and the width of the porous semiconductor layer is greater than that of the source electrode; the porous structure in the semiconductor layer is a vertical through-hole structure, and the opening of the porous electrode near the drain electrode is smaller than the opening of the porous electrode near the source electrode; a rectangular strip drain electrode is arranged at the center of the porous semiconductor layer, and the width of the drain electrode is smaller than the width of the porous semiconductor layer; an encapsulation layer is arranged at the center of the drain electrode, and a square hole is opened in the center of the encapsulation layer. At this time, the size of the hole, as viewed from a top view, must meet the requirement that the drain electrode exposes all or part of the overlapping area with the source electrode; the encapsulation layer is covered with an electrolyte layer, and the size of the electrolyte layer must completely cover the square hole of the encapsulation layer; a gate is arranged above the electrolyte layer, and the gate is in full contact with the electrolyte layer, or a gate is arranged on the side of the porous semiconductor layer, and the gate and the source electrode are located in the same plane;

[0007] A control signal is applied to the gate. Under the action of the source-drain voltage between the drain and source, the ions in the electrolyte layer can penetrate into or out of the semiconductor layer through the porous structure, thereby regulating the conductive properties of the semiconductor layer.

[0008] The object of the invention of the present invention is achieved like this:

[0009] The present invention discloses an OECT based on a porous semiconductor channel and a preparation method thereof, which mainly includes a substrate, a source electrode, a porous semiconductor layer, a drain electrode, an encapsulation layer, an electrolyte layer and a gate electrode. During the preparation process, a substrate is first prepared in a vertical structure, and the substrate is cleaned and dried. Then, a source electrode is prepared on the substrate, a porous semiconductor layer is prepared on the source electrode, a drain electrode is prepared on the porous semiconductor layer, an encapsulation layer is prepared on the substrate, and the overlapping portion between the drain electrode and the source electrode is exposed. An electrolyte layer is prepared above the drain electrode, and finally a gate electrode connected to the electrolyte layer is prepared.

[0010] At the same time, the OECT based on the porous semiconductor channel and the preparation method thereof of the present invention also have the following beneficial effects:

[0011] (1) Using vertical structure devices, the channel length can be controlled and adjusted in the range of 100nm to 10μm, and then the various indicators of the transistor, such as current density, switching rate, capacitance, etc., can be adjusted according to the channel length;

[0012] (2) Using a porous semiconductor layer, under the action of the gate voltage, the ions in the electrolyte dielectric layer are doped into or precipitated into the semiconductor through the porous layer, avoiding the need for ions to dope the semiconductor from the edge of the electrolyte under the vertical structure, greatly shortening the ion transmission path, and thus effectively controlling the carrier concentration in the semiconductor and changing the conductivity of the semiconductor;

[0013] (3) The porous structure of the present invention is such that the diameter of the upper opening is smaller than that of the lower opening. When preparing the drain electrode at the top, the contact between the drain electrode and the source electrode can be effectively avoided, thereby preventing the device from short-circuiting. At the same time, the structure is applicable to a variety of electrode preparation methods, including evaporation, sputtering, etc.

[0014] (4) The current density and transconductance per unit area of ​​the vertical OECT device based on the porous structure provided by the present invention are not affected by changes in the size of the source and drain electrodes. Therefore, the output current and transconductance can be linearly adjusted by the size of the source and drain electrodes, making it suitable for applications with different requirements for current density and transconductance.

[0015] (5) The porous structure-based vertical OECT device preparation method provided by the present invention is compatible with large-scale solution preparation methods, which can effectively reduce preparation energy consumption and preparation costs; at the same time, the device structure is compatible with flexible stretchable substrates, which can achieve stable device performance maintenance and output under extreme stress conditions;

[0016] (6) Package opening: The device of the present invention can change the shape of the package layer opening to control the efficiency of ion incorporation / exfiltration. As described in effect (2), ions enter and exit the semiconductor channel through porous doping. Changing the size and method of the opening can change the efficiency of ion penetration: for example, when the entire channel layer is exposed to the outside and a gate voltage is applied to turn on the device, ions simultaneously penetrate into the channel from all porous layers, and when the voltage is removed, ions penetrate from the porous layers. If only part of the porous layers are exposed to the outside, the efficiency of ion incorporation / exfiltration will be reduced, thereby controlling the distance of ion movement, changing the time characteristic curve of the device, and introducing a storage function at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a layered structure diagram of a vertical OECT based on a porous semiconductor layer of the present invention;

[0018] Figure 2 is the transfer characteristic curve of the output current;

[0019] Figure 3 The following are structural diagrams of vertical OECTs based on porous semiconductor layers using top full-coverage gates and side gates respectively; DETAILED DESCRIPTION

[0020] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0021] Example

[0022] Figure 1This is a layered structure diagram of the vertical OECT based on the porous semiconductor layer of the present invention.

[0023] In this embodiment, a vertical OECT based on a porous semiconductor layer, such as Figure 1 (a) shows a cross-sectional view of an OECT, comprising a substrate 1, a source electrode 2, a porous semiconductor layer 3, a drain electrode 4, an encapsulation layer 5, an electrolyte layer 6, and a gate electrode 7;

[0024] exist Figure 1 (b) The source electrode 2 in the form of a rectangular strip is set in the center of the substrate 1. Figure 1 (c) as shown; Figure 1 As shown in (d), a square porous semiconductor layer 3 is provided on the source electrode 2, and the width of the porous semiconductor layer 3 is greater than the width of the source electrode 2; Figure 1 As shown in (e), a rectangular strip-shaped drain electrode 4 is provided at the center of the porous semiconductor layer 3. The width of the drain electrode 4 is smaller than the width of the semiconductor layer 3, and the drain electrode 4 does not cover or block the porous part of the semiconductor. Figure 1 As shown in (f), an encapsulation layer 5 is provided at the center of the drain electrode 4, and a square hole is opened in the center of the encapsulation layer 5. At this time, the size of the hole, as viewed from the top view, is sufficient to expose the overlapping area of ​​the drain electrode 4 and the source electrode 2; Figure 1 As shown in (g), the encapsulation layer 5 is covered with an electrolyte layer 6, and the size of the electrolyte layer 6 is sufficient to completely cover the square hole of the encapsulation layer 5; a gate 7 is provided on the electrolyte layer 6, and the gate 7 is in full contact with the electrolyte layer 6;

[0025] like Figure 3 In (a), the gate 7 can be an electrode sheet directly above the electrolyte layer 6; Figure 3 In (b), the gate electrode 7 may be on the side of the porous semiconductor layer 3 and located in the same plane as the source electrode 2;

[0026] A control signal is applied to the gate 7. Under the action of the source-drain voltage between the drain electrode 4 and the source electrode 2, the ions in the electrolyte layer 6 can penetrate into or out of the semiconductor layer 3 through the porous structure, thereby controlling the conductivity of the semiconductor layer. The characteristics of this signal are affected by various factors including the porous diameter, porous density, porous semiconductor thickness, and the size of the opening of the packaging layer. Therefore, the above conditions can be controlled according to actual conditions, thereby effectively regulating the migration time of electrons and ions, and realizing effective regulation of the OECT performance (including current size, transconductance size, and response time).

[0027] In this embodiment, the substrate is selected from one of glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), or polyurethane (PU).

[0028] In this embodiment, the electrode width of the source and drain electrodes ranges from 1 to 500 μm, and they are specifically composed of an electrochemically stable conductive material, specifically one of gold, platinum, carbon nanotubes or graphene; the gate is selected from a conductive material with or without electrochemical activity, specifically one of gold, silver, poly (3,4-ethylenedioxythiophene): polystyrene sulfonate, carbon nanotubes, graphene, and graphyne.

[0029] In this embodiment, the thickness of the semiconductor layer is 100 nm to 1 μm, and is specifically made of a composite semiconductor material that is both ion-conducting and electron-conducting.

[0030] In this embodiment, the encapsulation layer is made of an electrochemically stable insulating material, specifically one of parylene-C, cellulose, photoresist SU-8, polystyrene, polydimethylsiloxane PDMS, and polystyrene-ethylene-butylene SEBS.

[0031] In this embodiment, the electrolyte layer is a solid or liquid electrolyte that does not have electron-conducting properties but has ion-conducting properties.

[0032] In combination with the above materials, the preparation method of a vertical OECT based on a porous semiconductor layer of the present invention is described in detail below, which specifically includes the following steps:

[0033] (1) Ultrasonic cleaning with isopropyl alcohol Figure 1 (b) The glass substrate shown was dried for 15 minutes and then dried in an oven at 80°C for 2 hours.

[0034] (2) On the cleaned glass substrate, 3nm chromium and 120nm gold are sequentially deposited as source electrodes with a width of 30 to 120μm. Figure 1 (c)

[0035] (3) The glass substrate with a layer of electrode deposited thereon is subjected to UV ozone cleaning for about 10 minutes;

[0036] (4) Prepare a semiconductor layer with cross-linking function by spin coating: control the humidity to above 85%, spin coating speed to 5000 rpm, and spin coating for 30 seconds (because spin coating under high humidity conditions causes water vapor condensation to form a breathing pattern, forming a porous semiconductor); photolithography: use 365nm ultraviolet light for exposure treatment, cross-link the semiconductor film at the channel to form a semiconductor layer in the channel area, such as Figure 1 (d)

[0037] (5) Prepare 120nm gold as drain electrode on the semiconductor layer, with an electrode width of 30 to 120μm, such as Figure 1 (e)

[0038] (6) Prepare a spin-coated encapsulation layer with photocrosslinking function, and use 365nm ultraviolet light for exposure to expose the patterned channel, such as Figure 1 (f)

[0039] (7) Add about 1 μL of PBS buffer solution on the exposed channel as a dielectric layer, and connect the gate through the dielectric layer, as shown in Figure 1 (g) shown.

[0040] Thus, a vertical OECT device with a porous semiconductor layer was successfully fabricated. In this embodiment, the source, drain, and gate electrodes were fabricated using one of the following methods: evaporation, magnetron sputtering, spray coating, inkjet printing, aerosol printing, or screen printing. The semiconductor layer, encapsulation layer, and electrolyte layer were fabricated using one of the following methods: spin coating, screen printing, inkjet printing, 3D printing, aerosol printing, electrohydrodynamic printing, or doctor blade coating.

[0041] Next, we use the prepared vertical OECT for testing. The test conditions are as follows:

[0042] Constant drain voltage V D =0.1V, set the gate-source voltage to sweep forward between 0.3V and -0.5V, capture the output current to obtain the transfer characteristics and draw a graph, such as Figure 2 As shown, it can be seen that under this test condition, the device has a great current regulation effect, achieving a current regulation effect from 10 -8 A to 10 -2 The source current (solid line) is controlled at the order of A; the gate current is always kept at a low level (<10 -7 A) Devices with different channel shapes have different hysteresis responses. The rule is: as the top electrode width decreases, the ion permeation path becomes shorter and the output current hysteresis decreases; conversely, the hysteresis becomes more pronounced.

[0043] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. An OECT based on a porous semiconductor channel, characterized in that: include: substrate, source electrode, porous semiconductor layer, drain electrode, encapsulation layer, electrolyte layer and gate electrode; A rectangular strip source electrode is provided in the center of the substrate, and a square porous semiconductor layer is provided at the center of the source electrode. The width of the porous semiconductor layer is greater than that of the source electrode. The porous semiconductor layer is vertically connected in the semiconductor layer, and the opening of the porous layer near the drain electrode is smaller than the opening of the porous layer near the source electrode. A rectangular strip-shaped drain electrode is provided at the center of the porous semiconductor layer, wherein the width of the drain electrode is smaller than the width of the porous semiconductor layer; An encapsulation layer is provided at the center of the drain electrode, and a square hole is opened in the center of the encapsulation layer. When viewed from a top view, the size of the hole is sufficient to expose all or part of the area of ​​the drain electrode that overlaps with the source electrode. An electrolyte layer is provided above the encapsulation layer, and the size of the electrolyte layer is sufficient to completely cover the square hole of the encapsulation layer. A gate is provided above the electrolyte layer, and the gate is in full contact with the electrolyte layer, or a gate is provided on the side of the porous semiconductor layer, and the gate and the source electrode are located in the same plane. A control signal is applied to the gate. Under the action of the source-drain voltage between the drain and source electrodes, the ions in the electrolyte layer can penetrate into or out of the semiconductor layer through the porous structure, thereby realizing the current regulation of the OECT.

2. The OECT based on porous semiconductor channel according to claim 1, characterized in that The substrate is one of glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS) or polyurethane (PU).

3. The OECT based on porous semiconductor channel according to claim 1, characterized in that The electrode width of the source and drain electrodes ranges from 1 to 500 μm, and they are specifically composed of electrochemically stable conductive materials, specifically one of gold, platinum, carbon nanotubes or graphene; the gate is made of a conductive material with or without electrochemical activity, specifically one of gold, silver, poly (3,4-ethylenedioxythiophene): polystyrene sulfonate, carbon nanotubes, graphene, and graphyne.

4. The OECT based on porous semiconductor channel according to claim 1, characterized in that The thickness of the semiconductor layer is 100nm to 5μm, and is specifically composed of a composite semiconductor material that is both ion-conducting and electron-conducting. The upper opening diameter of the porous structure that runs through the top and bottom is 100nm to 4μm, and the lower opening diameter is 150nm to 3.5μm.

5. The OECT based on porous semiconductor channel according to claim 1, characterized in that The encapsulation layer is made of an electrochemically stable insulating material, specifically one of parylene-C, cellulose, photoresist SU-8, polystyrene, polydimethylsiloxane PDMS, and polystyrene-ethylene-butylene SEBS.

6. The OECT based on porous semiconductor channel according to claim 1, characterized in that The electrolyte layer is a solid or liquid electrolyte that does not have electronic conductivity but has ion conductivity.

7. The method for preparing an OECT based on a porous semiconductor channel according to claim 1, wherein: The preparation process includes the following steps: Step 1: Prepare the substrate, clean it and dry it; Using a glass substrate as the substrate, the glass substrate was ultrasonically cleaned with isopropyl alcohol for 15 minutes and then dried in an oven at 80°C for 2 hours. Step 2: Prepare a source electrode on the substrate; 3nm chromium and 120nm gold were sequentially evaporated on the cleaned glass substrate as source electrodes with a width of 30 to 120μm. Step 3: preparing a porous semiconductor layer on the source electrode; A glass substrate with an electrode layer deposited thereon was cleaned with UV ozone for 10 minutes, and then a cross-linked semiconductor layer was spin-coated. The humidity was controlled above 85%, and the spin coating speed was 5000 rpm for 30 seconds to form a porous semiconductor. Photolithography was then performed using 365 nm UV light exposure to cross-link the semiconductor film in the channel region, forming a semiconductor layer in the channel region. Step 4: preparing a drain electrode on the semiconductor layer; A 120nm gold drain electrode is prepared on the semiconductor layer, with an electrode width of 30 to 120μm; Step 5: preparing an encapsulation layer on the substrate and exposing the semiconductor layer between the source and drain electrodes; Prepare a spin-coated encapsulation layer with photocrosslinking function and expose it with 365nm ultraviolet light to expose the patterned channels; Step 6: preparing an electrolyte layer on top of the semiconductor layer; 1 μL of PBS buffer was added dropwise on the exposed channels to serve as the electrolyte layer; Step 7: Prepare the gate electrode connected to the electrolyte layer.

8. The method for preparing an artificial neural synapse based on OECT according to claim 7, characterized in that: The source electrode, drain electrode and gate electrode are prepared by a method selected from evaporation, magnetron sputtering, spraying, inkjet printing, aerosol printing and screen printing.

9. The method for preparing an artificial neural synapse based on OECT according to claim 7, characterized in that: The semiconductor layer, encapsulation layer, and electrolyte layer are prepared by spin coating, spray coating, screen printing, inkjet printing, 3D printing, aerosol printing, electrofluid printing, or scraping.

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