Capacitive structures and porous semiconductors in engineered substrates

Abstract

An article includes a crystalline semiconductor substrate, a structured dielectric region disposed on the crystalline semiconductor substrate, the structured dielectric region including a plurality of pillars extending from the crystalline semiconductor substrate, and a filler material including a porous dielectric material, a nonporous dielectric material, vacuum, a gas, or a combination of two or more thereof disposed in regions separating the plurality of pillars; an insulating oxide layer disposed on the structured dielectric region; and a device layer comprising a crystalline semiconductor or piezoelectric material; where: each of the plurality of pillars has a width of about 100 nm to about 40 μm; the plurality of pillars are formed of the crystalline semiconductor substrate; and the structured dielectric region exhibits an effective resistivity higher than a resistivity of the crystalline semiconductor substrate, or the filler material exhibits an effective permittivity lower than a permittivity of the crystalline semiconductor substrate.

Description

Atty. Dkt. No. 132447-0111CAPACITIVE STRUCTURES AND POROUS SEMICONDUCTORS IN ENGINEERED SUBSTRATESCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Provisional PatentApplication No. 63 / 682,198 filed August 12, 2024, which is hereby incorporated by reference, in its entirety for any and all purposes.GOVERNMENT RIGHTS

[0002] This invention was made with government support under DE-SC0022480 and DE-SC0024779 awarded by the U.S. Department of Energy. The government has certain rights in the invention.FIELD

[0003] The present technology is generally related to engineered substrate architectures for silicon-on-insulator (SOI) and piezo on insulator (POI) platforms, wherein the handle wafer is modified to reduce substrate conduction and dielectric coupling. These modifications include structured dielectric regions such as pillar arrays and capacitive trench configurations formed within a crystalline semiconductor substrate. These regions interrupt conduction paths and promote displacement current flow, thereby improving RF performance.BACKGROUND

[0004] Silicon-on-insulator (SOI) articles are widely used in modem electronics, particularly in high-frequency applications due to their advantages in noise isolation and device speed for improved performance and reliability. Piezoelectric-on-insulator (POI) articles are widely used in acoustic and high-frequency devices to combine the electromechanical benefits of piezoelectric materials with insulating substrates. In radiofrequency (RF) applications, however, substrate losses and parasitic coupling can significantly degrade signal integrity and linearity. These issues may be caused by-1-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 conduction in the substrate (also referred to herein as “handle wafer” and “handle layer”) of the SOI and POI, which acts as a lossy ground plane at high frequencies. Even when high-resistivity silicon (e.g., greater than 1000 Ohm cm or 1000 Ohm cm to 10000 Ohm cm) is used for the handle wafer, a parasitic conduction layer often forms at the interface between the substrate and the buried oxide (BOX, also referred to herein as an “insulating oxide layer”). This interfacial conduction layer undermines the benefits of the high-resistivity substrate by permitting unwanted coupling between the active device layer and the substrate, thereby limiting RF performance.SUMMARY

[0005] In one aspect, an article is disclosed. The article includes a crystalline semiconductor substrate, a structured dielectric region disposed on the crystalline semiconductor substrate, an insulating oxide layer disposed on the structured dielectric region, and a device layer comprising a crystalline semiconductor or piezoelectric material. The structured dielectric region includes a plurality of pillars extending from the crystalline semiconductor substrate, and a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor material, vacuum, a gas, or a combination of any two or more thereof disposed in regions separating the plurality of pillars. Each pillar of the plurality of pillars has a width of about 100 nm to about 40 pm. The plurality of pillars are formed of the crystalline semiconductor substrate. The structured dielectric region exhibits an effective resistivity higher than a resistivity of the crystalline semiconductor substrate, or the filler material exhibits an effective permittivity lower than a permittivity of the crystalline semiconductor substrate.

[0006] In any embodiment, the insulating layer may be furthered disposed on portions of the crystalline semiconductor substrate free of the structured dielectric region.

[0007] In another aspect, an article is disclosed. The article includes a crystalline semiconductor substrate comprising a surface having a plurality of pillars extending therefrom, and a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor material, vacuum, a gas, or a combination thereof disposed in regions separating the plurality of-2-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 pillars. Each pillar of the plurality of pillars has a width of about 100 nm to about 40 pm. The plurality of pillars are formed of the crystalline semiconductor substrate. A combination of the plurality of pillars and the filler material exhibits an effective resistivity higher than a resistivity of the crystalline semiconductor substrate, or the filler material exhibits an effective permittivity lower than a permittivity of the crystalline semiconductor substrate.

[0008] In any embodiment, the crystalline semiconductor substrate may further include planar regions free of the plurality of pillars. Each pillar of the plurality of pillars may be spaced apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 100 pm. Each pillar of the plurality of pillars may be spaced apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 2 pm. Each pillar of the plurality of pillars may be uniformly spaced apart from each other pillar of the plurality of pillars. The filler material may include the porous dielectric material, and the porous dielectric material may include a dielectric material having a plurality of pores dispersed throughout the dielectric material. The plurality of pores may comprise a lamellar porosity, a columnar porosity, or a combination thereof. The filler material may include the nonporous dielectric material or the nonporous semiconductor material. The nonporous dielectric material may include a ceramic or a polymer. The filler material may include the porous semiconductor material or nonporous semiconductor material and the porous semiconductor material or nonporous semiconductor material may include an amorphous semiconductor material or a poly crystalline semiconductor material. The article may include a planar surface oxide disposed on the plurality of pillars. The crystalline semiconductor substrate may include silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, or germanium. Each pillar of the plurality of pillars may have a triangular, rectangular, square, ovular, circular, cruciform, or hexagonal cross- sectional shape.

[0009] In another aspect, a monolithic active pixel sensor is disclosed. The monolithic active pixel sensor includes an article as described herein.

[0010] In another aspect, an article is disclosed. The article includes a plurality of pillars disposed on a crystalline semiconductor substrate, the plurality of pillars comprising a crystalline semiconductor, each pillar of the plurality of pillars having a-3-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 width of about 100 nm to about 40 pm; and a porous dielectric material or porous semiconductor material disposed around the plurality of pillars. The porous dielectric material or porous semiconductor material may have a plurality of pores dispersed throughout the porous dielectric material or porous semiconductor material.

[0011] In another aspect, a method of making an article is disclosed. The method includes etching a crystalline semiconductor substrate to form a plurality of pillars on a surface of the crystalline semiconductor substrate, each pillar of the plurality of pillars having a width of about 100 nm to about 40 pm; and disposing a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor material, or a combination thereof in regions separating the plurality of pillars.

[0012] In any embodiment, the porous dielectric material or porous semiconductor material may include a lamellar porosity, a columnar porosity, or a combination thereof. The method of making may include the filler material including the porous dielectric material or the porous semiconductor material, and the porous dielectric material or the porous semiconductor material may include a plurality of pores dispersed throughout the porous dielectric material or the porous semiconductor material. The plurality of pores may include a lamellar porosity, , a columnar porosity, or a combination thereof. The filler material may include the nonporous dielectric material or the nonporous semiconductor material. The etching may include spacing each pillar of the plurality of pillars apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 100 pm. The etching may include spacing each pillar of the plurality of pillars uniformly apart from each other pillar of the plurality of pillars.

[0013] In another aspect, an article is disclosed including a substrate comprising a crystalline semiconductor and a discrete region within the crystalline semiconductor, the discrete region comprising a porous dielectric material or porous semiconductor; an insulating oxide layer disposed on the substrate; and a device layer disposed on the insulating oxide layer, the device layer comprising a crystalline semiconductor or piezoelectric material. The porous dielectric material or porous semiconductor material may include a lamellar porosity.-4-4833-5236-891 1.1Atty. Dkt. No. 132447-0111BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a cross-sectional schematic of a silicon-on-insulator (SOI) or piezoelectric on insulator (POI) article with a structured dielectric region.

[0015] FIG. 2A is a cross-sectional schematic showing a detailed illustration of an SOI or POI article with a structured dielectric region comprises of pillars and filler. FIG. 2B is an illustration of different structured dielectric regions.

[0016] FIG. 3 is a cross-sectional schematic showing electric field lines and / or conduction paths in a multilayer substrate with coplanar waveguides.

[0017] FIG. 4 is a flow diagram of formation of an SOI with a handle wafer including a structured dielectric region with discrete cavities filled with porous semiconductor.

[0018] FIG. 5 is a flow diagram of the formation of a structured dielectric region with discrete cavities filled with porous semiconductor.

[0019] FIGs. 6 A and 6B are graphs comparing the effective permittivity of homogenous porosity (FIG. 6 A) and layered porosity (FIG. 6B).

[0020] FIGs. 7A and 7B provide graphs of effective permittivity and dielectric constant for porous materials. FIGs. 7A and 7B are graphs comparing the effective permittivity of columnar porosity (FIG. 7A) and layered porosity (FIG. 7B).

[0021] FIG. 8 A is a cross-sectional image of an engineered substrate including porous silicon formed by deposition of silicon flake powder. FIG. 8B is a photograph of an etched wafer with porous silicon deposited in cavities. FIG. 8C is an optical microscopy image of individual cavities with a length of 1,000 pm and width from 10 to 40 pm.

[0022] FIGs. 9A describes a test setup used for RF testing. FIG. 9A is an illustration of a test setup used for RF testing of engineered substrates showing a cross- sectional view of the coplanar waveguide (CPW) structures on an engineered substrate with an oxide. FIG. 9B is an image of an RF test structure fabricated on an engineered substrate formed with a silicon wafer with porous silicon layer disposed therein and hydrogen silsesquioxane (HSQ) insulating oxide layer.-5-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0023] FIGs. 10A-10D compare harmonic distortions, impedance, and effective permittivity of materials. FIGs. 10A and 10B present data from the experimental testing of an engineered substrate incorporating porosity formed by deposition of silicon flake powder, showing a reduction in second and third harmonic distortion. FIGs. 10C and 10D present data comparing characteristic impedance (FIG. 10C) and effective permittivity (FIG. 10D) vs. frequency; SI: Si wafer (1-10 Q cm) with PECVD oxide; S2: Si wafer (1- 10 Q cm) with HSQ oxide; S4: Si wafer (1-10 Q cm) with porous Si layer and HSQ oxide.

[0024] FIG. 11 presents data from the experimental testing of an engineered substrate incorporating porosity formed by deposition of silicon flake powder, showing a reduction in cross-talk between adjacent transmission lines.

[0025] FIGs. 12A-12B are scanning electron microscopy (SEM) images of wafer cavities including silicon hexagonal pillar supports of two sizes and spacings; FIG. 12 A: 7.5 pm pillars with 35 pm spacing; FIG. 12B: 15 micron pillars with 1 pm spacing.

[0026] FIGs. 13A-13B SEM of porous silicon deposited within the etched cavities with support pillars.

[0027] FIGs. 14A-14D are SEM images of an engineered substrate with hexagonal trench structures implemented in a crystalline semiconductor substrate.

[0028] FIG. 15 is a cross-sectional image produced by focused ion beam milling to show the annealed porosity of porous silicon.

[0029] FIG. 16 presents data from an engineered substrate with hexagonal trench structures, showing reduction in second and third harmonic distortion.

[0030] FIG. 17 is a graph of data from an engineered substrate with hexagonal pillar structures, indicating a reduction in cross-talk.DETAILED DESCRIPTION

[0031] Various embodiments are described hereinafter. It should be noted that the specific embodiments are not intended as an exhaustive description or as a limitation to the broader aspects discussed herein. One aspect described in conjunction with a particular-6-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 embodiment is not necessarily limited to that embodiment and can be practiced with any other embodiment s).

[0032] As utilized herein with respect to numerical ranges, the terms “approximately,” “about,” “substantially,” and similar terms will be understood by persons of ordinary skill in the art and will vary to some extent depending upon the context in which it is used. If there are uses of the terms that are not clear to persons of ordinary skill in the art, given the context in which it is used, the terms will be plus or minus 10% of the disclosed values. When “approximately,” “about,” “substantially,” and similar terms are applied to a structural feature (e.g., to describe its shape, size, orientation, direction, etc.), these terms are meant to cover minor variations in structure that may result from, for example, the manufacturing or assembly process and are intended to have a broad meaning in harmony with the common and accepted usage by those of ordinary skill in the art to which the subject matter of this disclosure pertains. Accordingly, these terms should be interpreted as indicating that insubstantial or inconsequential modifications or alterations of the subject matter described and claimed are considered to be within the scope of the disclosure as recited in the appended claims.

[0033] The use of the terms “a” and “an” and “the” and similar referents in the context of describing the elements (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the embodiments and does not pose a limitation on the scope of the claims unless otherwise stated. No language in the specification should be construed as indicating any non-claimed element as essential.

[0034] In RF systems, achieving quasi-transverse electromagnetic (quasi-TEM) mode propagation is desirable to reduce signal distortion and substrate losses. This can be-7-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 done by lowering the dielectric relaxation frequency of the substrate below the operating frequency range, which can be accomplished by increasing substrate resistivity or reducing permittivity. In such regimes, the substrate behaves as a lossy dielectric.

[0035] To mitigate detrimental effects of substrate losses and parasitic coupling, high-resistivity trap-rich (HR-TR) SOI articles have been developed. These articles incorporate polycrystalline silicon layers beneath the BOX to suppress parasitic conduction and improve RF isolation. While effective in reducing substrate losses, HR-TR SOI substrates present several limitations. Their fabrication is costly, in part due to the significantly higher price of high-resistivity silicon compared to standard or low-resistivity wafers. Additionally, the trap-rich layer itself can undergo crystallization at elevated temperatures, which reduces the density of electronic traps and compromises its effectiveness. This thermal instability, combined with the complexity of HR-TR processing, limits compatibility with high-temperature CMOS flows and contributes to persistent parasitic conduction at the BOX / handle interface.

[0036] An alternative approach that has been explored in research involves the use of electrochemically etched porous silicon layers beneath the BOX. These porous layers can reduce the effective dielectric constant and improve RF linearity. However, electrochemically etched porous silicon introduces its own challenges. The pore dimensions in these layers are typically on the nanometer scale, resulting in a fine porous network that is mechanically fragile and thermally unstable. At elevated temperatures, this fine porosity tends to sinter or consolidate into larger pores, altering the morphology of the silicon. These changes induce mechanical stresses within the substrate, often leading to wafer bowing or warping. The process also typically uses doped substrates to facilitate etching, which limits compatibility with high-resistivity silicon. Furthermore, the fabrication process is complex, often using etch-stop layers and post-etch patterning, and the resulting structures lack the thermal robustness for integration with standard CMOS flows.

[0037] The effectiveness of substrate modifications in mitigating conduction- related losses is influenced by the electrical properties of the wafer. In high-resistivity substrates, conduction is typically confined to a thin parasitic layer near the BOX interface. In lower-resistivity substrates, conduction behavior is governed by the skin-8-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 depth at RF frequencies, which concentrates current near the surface. These differences in conduction behavior present challenges for achieving consistent RF isolation across substrate types.

[0038] Similar substrate engineering challenges are encountered in piezoelectric on insulator (POI) platforms, which integrate piezoelectric materials such as lithium niobate or aluminum nitride onto insulating layers for RF filtering and acoustic wave devices. POI substrates are increasingly used in mobile and wireless applications due to their ability to support high-performance acoustic resonators. However, like SOI, POI substrates suffer from parasitic coupling and substrate losses that degrade RF performance. The handle wafer in POI structures plays a role in determining the overall dielectric environment and mechanical stability of the device. Improvements to the substrate — particularly those that reduce dielectric constant or increase effective resistivity while maintaining mechanical integrity — are useful for advancing POI technologies.

[0039] There remains a need for an engineered substrate architecture that provides low dielectric constant and high effective resistivity for RF isolation, while maintaining mechanical integrity and thermal stability. There remains a need for a substrate that is compatible with low, standard, and high-resistivity silicon and is applicable to both SOI and POI platforms, and that avoids the limitations associated with trap-rich layers and electrochemically etched porous silicon.

[0040] Provided herein are engineered porous structures, SOI substrates including engineered porous structures, POI substrates including engineered porous structures, and methods of making the same. The engineered porous structures may be disposed on the handle wafer of SOI and POI substrates. The engineered porous structures may be formed in or on the handle wafer of SOI and POI substrates. The engineered porous structures may include etched pillar arrays and capacitive configurations (e.g., cavities formed in the handle wafer). The engineered porous structures may reduce substrate coupling and dielectric losses in SOI and POI articles while preserving mechanical strength. The engineered porous structures may facilitate scalable, CMOS-compatible fabrication and offer a promising alternative to conventional RF-enhanced SOI and POI technologies.

[0041] In conventional SOI and POI articles, the handle wafer beneath the buried oxide (BOX) layer (also referred to herein as “insulting oxide layer”) may act as a-9-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 conductive path, especially at high frequencies. Even high-resistivity silicon substrates are prone to forming parasitic conduction layers at the BOX interface.Engineered Porous Substrates

[0042] Engineered porous structures may form a structured dielectric region. The structured dielectric region may be disposed on the handle wafer. For example, the structured dielectric region may be imposed in the handle wafer. The handle wafer may be modified by introducing one or more structured dielectric regions including engineered porous structures. The structured dielectric region may suppress substrate conduction, reduce effective dielectric constant, and / or promote displacement current flow over conduction current. The structured dielectric region may include materials (e.g. semiconductors) that may be classified outside of dielectrics, and is so named simply due to its effective dielectric constant and effective resistivity.

[0043] The structured dielectric region may support quasi-transverse electromagnetic (quasi-TEM) mode propagation by lowering the dielectric relaxation frequency below the operating frequency range of RF devices. This may permit the substrate to behave as a lossy dielectric, where displacement currents dominate and conduction currents are suppressed. This behavior is typically achieved using high-resistivity substrates, but the structured dielectric region may provide similar performance using standard or low-resistivity silicon, thereby expanding manufacturing flexibility.

[0044] Unlike conventional high-resistivity trap-rich (HR-TR) SOI and POI articles, which rely on expensive high-resistivity silicon and thermally unstable polycrystalline trap layers, the structured dielectric regions may achieve comparable or superior RF isolation using scalable fabrication techniques.

[0045] FIG. 1 is a cross-sectional schematic of a SOI or POI article 100 with a structured dielectric region 120. The structured dielectric region 120 is disposed on the handle wafer 110. The buried oxide (BOX) 130 is disposed on the structured dielectric region 120. The device layer 140 is disposed on the BOX 130. In some embodiments, regions of the handle wafer 110 may be free of the structured dielectric region 120, and the BOX 130 may be disposed directly on the handle wafer 110.-10-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0046] The handle wafer 110 may provide mechanical support to the SOI or POI article. The handle wafer 110 may be thicker than other regions of the article. For example, the handle wafer 110 may be about 1 pm to 10 mm (e.g., about 500 pm to about 1000 pm or about 725 pm to about 775 pm). The handle wafer 110 may be the thicker, bottom layer of the article. The handle wafer 110 may provide a thermal path to conduct heat away from the device layer 140. The handle wafer 110 may be formed of a crystalline semiconductor (e.g., silicon, gallium nitride, gallium arsenide, indium phosphide, or germanium). For example, the handle wafer 110 may be monocrystalline silicon with a (100) crystal orientation.

[0047] The BOX 130 may be a continuous layer of insulator that is disposed between the structured dielectric region 120 and the device layer 140. The BOX 130 may provide electrical isolation between the device layer 140 and the handle wafer 110. The BOX 130 may have a thickness of about 1 nm to about 500 pm (e.g., about 10 nm to about 3 pm, about 10 nm to about 500 nm, about 10 nm to about 100 nm, about 10 nm to about 50 nm, or about 20 nm to about 30 nm). The BOX 130 material may include silicon oxide, germanium oxide, gallium oxide, indium oxide, aluminum oxide (e.g., sapphire), or a combination of any two or more thereof.

[0048] The device layer 140 may be a thinner layer of crystalline semiconductor or piezoelectric. Active devices may be fabricated into or on top of the device layer 140. The device layer may have a thickness of about 1 nm to about 500 pm (e.g., about 5 nm to about 3 pm, about 5 nm to about 1 pm, about 5 nm to about 500 nm, or about 5 nm to about 200 nm). Where the article 100 is a SOI article, the device layer 140 may be formed of a crystalline semiconductor (e.g., silicon, gallium nitride, gallium arsenide, indium phosphide, or germanium). For example, the device layer 140 may be monocrystalline silicon with a 100 crystal orientation. Where the article 100 is a POI article, the device layer 140 may be formed of a piezoelectric material (e.g., lithium niobate, lithium tantalate, lead zirconate titanate, aluminum nitride, scandium-doped aluminum nitride).

[0049] The structured dielectric region 120 may be formed of engineered porous structures. Engineered porous structures may include pillar arrays (e.g., etched into the handle wafer), cavities formed in the handle wafer creating capacitive configurations, and combinations thereof. A filler material may be disposed in the cavities and discrete areas-11-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 around the pillar arrays. The filler material may include a gas, a porous material (e.g., a porous semiconductor or dielectric material), a solid nonporous material (e.g., nonporous semiconductor or dielectric material), a gas, or a combination of any two or more thereof. The polymer may include any suitable polymer, nonlimiting examples of which include an epoxy, polyimide, polyetherimide, fluorinated polymer, or a copolymer or polymer blend thereof. The ceramic may include any suitable ceramic, nonlimiting examples of which include silicon oxide, fluorphlogopite, barium titanate, and combinations thereof. The semiconductor material may be an amorphous semiconductor material, a polycrystalline semiconductor material, or a combination thereof.

[0050] A cross-sectional schematic of an SOI or POI article 200 with a structured dielectric region 220 is shown in FIG. 2A, and FIG. 3 illustrates electric field lines and conduction paths within that structure. The article 200 includes a structured dielectric region 220 disposed on the handle wafer 210. In some embodiments, the handle wafer may include regions free of the structured dielectric region 220, in which case the BOX 230 may be disposed directly on the handle wafer 210. For example, the structured dielectric region 220 may be formed by patterning the handle wafer 210, and the handle wafer 210 may include planar regions that were not patterned and therefore do not include the dielectric region 220.

[0051] The structured dielectric region 220 is disposed on the handle wafer 210. The buried oxide (BOX) 230 is disposed on the structured dielectric region 220. The device layer 240 is disposed on the BOX 230.

[0052] The handle wafer 210 may provide mechanical support to the SOI or POI article. The handle wafer 210 may be thicker than other regions of the article. For example, the handle wafer 110 may be about 1 pm to 10 mm (e.g., about 500 pm to about 1000 pm or about 725 pm to about 775 pm). The handle wafer 210 may be the thicker, bottom layer of the article. The handle wafer 210 may provide a thermal path to conduct heat away from the device layer 240. The handle wafer 210 may be formed of a crystalline semiconductor (e.g., silicon, gallium nitride, gallium arsenide, indium phosphide, or germanium). For example, the handle wafer 210 may be monocrystalline silicon with a (100) crystal orientation.-12-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0053] The BOX 230 may be a continuous layer of insulator that is disposed between the structured dielectric region 220 and the device layer 240. The BOX 240 may provide electrical isolation between the device layer 240 and the handle wafer 210. The BOX 230 may have a thickness of about 1 nm to about 500 pm (e.g., about 10 nm to about 3 pm, about 10 nm to about 500 nm, about 10 nm to about 100 nm, about 10 nm to about 50 nm, or about 20 nm to about 30 nm). The BOX 230 material may include silicon oxide, germanium oxide, gallium oxide, indium oxide, aluminum oxide (e.g., sapphire), or a combination of any two or more thereof.

[0054] The device layer 240 may be a thinner layer of crystalline semiconductor or piezoelectric. Active devices may be fabricated into or on top of the device layer 240. The device layer 240 may have a thickness of about 1 nm to about 500 pm (e.g., about 5 nm to about 3 pm, about 5 nm to about 1 pm, about 5 nm to about 500 nm, or about 5 nm to about 200 nm). Where the article 200 is a SOI article, the device layer 240 may be formed of a crystalline semiconductor (e.g., silicon, gallium nitride, gallium arsenide, indium phosphide, or germanium). For example, the device layer 240 may be monocrystalline silicon with a 200 crystal orientation. Where the article 200 is a POI article, the device layer 240 may be formed of a piezoelectric material (e.g., lithium niobate, lithium tantalate, lead zirconate titanate, aluminum nitride, scandium-doped aluminum nitride).

[0055] The structured dielectric region 220 may be formed of engineered porous structures. Engineered porous structures may include pillar arrays 222 (e.g., etched into the handle wafer), cavities 224 formed in the handle wafer creating capacitive configurations, and combinations thereof. Where the pillar arrays 222 are formed by etching the handle wafer 210, the pillar arrays 222 may be formed of the same material as the handle wafer 210. Engineered porous structures may include a handle layer 210 with discrete regions 224 (e.g., cavities) within the handle wafer 210, forming the structured dielectric region 220, such that pillars are formed, at least in part, of the same material as the handle wafer 210 (e.g., crystalline semiconductor). The pillars may further include an oxide disposed on one or more surfaces of the pillars. For example, the oxide may be an oxide formed of an oxide of the wafer material.

[0056] Pillar and cavities 224 (e.g., spacing between pillars) may be uniformly (evenly) spaced apart from each other pillar, arranged in a density gradient, or in a-13-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 disordered arrangement. As an example, the cavity size may be about 500 pm to about 1500 pm in depth and width or length of about 0.1 pm to 1000 pm. The cross-sectional cavity shape may include hexagonal shapes, triangular shapes, circular shapes, oval shapes, square shapes, square shapes with rounded corners, rectangular shapes, cruciform, or any combination of two or more thereof. The cavity shape may include an orientation, for example two orthogonal sets of cavities. The cavity structures may be formed through etching (e.g., photolithography and deep reactive ion etching (DRIE)). As an example, pillars may include hexagonal shapes, triangular shapes, or hexagonal shapes where the spacing between pillars is smaller (e.g., about 100 nm to about 1 pm, about 100 nm to about 500 nm, or about 100 nm to about 200 nm). As another example, pillars may be any suitable shape where the spacing between pillars is larger (e.g., about 1 pm to about 1 mm, about 1 pm to about 10 pm, or about 1 pm to about 2 pm).

[0057] The pillars and cavities 224 may have different morphologies. Nonlimiting examples of cross-sectional morphologies include hexagonal shapes, triangular shapes, circular shapes, oval shapes, square shapes, square shapes with rounded corners, rectangular shapes, cruciform, or any combination of two or more thereof. For example, cavities 224 may include trenches.

[0058] The pillars may have a width, length, diameter, and / or other dimension of about 100 nm to about 1 mm (e.g., about 100 nm to about 40 pm, about 100 nm to about 20 pm, about 100 nm to about 10 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween).

[0059] The cavities 224 may have a width, length, diameter, and / or other dimension of about 100 nm to about 10 mm (e.g., about 100 nm to about 1 mm, about 100 nm to about 10 pm, about 100 nm to about 2 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween). The dimension of cavities 224 may provide the spacing between pillars such that the spacing between pillars may be about 100 nm to about 10 mm (e.g., about 100 nm to about 1 mm, about 100 nm to about 10 pm, about 100 nm to about 2 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween).

[0060] The height of the pillars, and the corresponding depth of the cavities 224 may be determined based on the resistivity of the handle wafer in which the structured-14-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 dielectric region 220 is formed. For example, the handle wafer may have a high resistivity (e.g., 1000 Ohm cm to about 10000 Ohm cm) and the depth of the cavities 224 may be less than 0.5 pm (e.g., about 0.05 pm to about 0.5 pm, about 0.1 pm to about 0.5 pm, or any value or subrange therebetween). For example, the handle wafer may have a standard resistivity (e.g., about 1 Ohm cm to about 10 Ohm cm) and the depth of the cavities 224 may be greater than 5 pm (e.g., about 5 pm to about 2000 pm, about 5 pm to about 1500 pm, about 5 pm to about 1000 pm, about 5 pm to about 150 pm, or any value or subrange therebetween). For example, the handle wafer may have a low resistivity (e.g., less than 1 Ohm cm) and the depth of the cavities 224 may be greater than 0.5 pm (e.g., about 0.5 pm to about 1500 pm, about 0.5 pm to about 10 pm, about 0.5 pm to about 5 pm, about 0.5 pm to about 1 pm, or any value or subrange therebetween).

[0061] A filler material may be disposed in the cavities 224 and discrete areas around the pillar arrays 222. The filler material may include a gas, a porous material (e.g., a porous semiconductor, porous dielectric, or a combination thereof), a solid nonporous material (e.g., semiconductor, dielectric, or a combination thereof), a gas (e.g., air, argon, xenon, nitrogen, or a combination of any two or more thereof), or a combination of any two or more thereof.

[0062] FIG. 2B illustrates variations of the structured dielectric region disposed on the handle layer. The approach on the left, shown as 1 and 4 for cases without and with the top oxide present, respectively, include porous silicon embedded into the structure with silicon pillars. The middle illustrations (2 and 5) provide a variation without and with the top oxide present, respectively, which may be useful where the spacing between silicon supports is very small (e.g., about 100 nm to about 1 pm). With very small inter-support spacings, an oxide layer may be deposited or grown between the silicon supports. This structure may provide similar or less good isolation as compared to the porous silicon. A third approach is illustrated as 3 and 6, without and with a top oxide present, respectively. This third approach includes cavities in the handle wafer that remain unfilled (vacuum) or are filled with a gas.

[0063] Structured dielectric regions disposed on the handle wafer may provide quasi-TEM mode propagation by lowering the dielectric relaxation frequency of the substrate. The structured dielectric regions may behave as lossy dielectrics, where-15-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 displacement currents dominate over conduction currents. This is achieved through geometric and material engineering, without relying on trap-rich layers or electrochemically etched porous silicon.

[0064] The effectiveness of these structures may depend on both the depth of the etched regions and the resistivity of the substrate. In high-resistivity wafers (e.g., 1000 Ohm cm to about 10000 Ohm cm), the parasitic conduction layer is typically only a few hundred nanometers thick (e.g., 100 nm to about 600 nm). Trenches etched to a comparable depth may interrupt conduction within this layer, and the bulk of the handle wafer below the trenches remains effectively non-conductive. In contrast, standard (e.g., about 1 Ohm cm to about 10 Ohm cm) or low-resistivity (e.g., less than 1 Ohm cm) wafers exhibit conduction behavior governed by the skin depth at RF frequencies. In these cases, deeper trenches are used to interrupt conduction currents, but the current density is naturally concentrated near the surface, making the trenching approach particularly effective.

[0065] For example, vertical breaks may be etched into the crystalline semiconductor substrate to form capacitive structures opposed to the electric field lines of coplanar RF transmission lines. These breaks may be left open, capped, or filled with a filler material comprising porous dielectric material, nonporous dielectric material, porous semiconductor material, nonporous semiconductor material, vacuum, gas, or combinations thereof. The capacitance of each structure depends on its geometry and fill material.

[0066] The present technology supports a spectrum of porosity and dielectric behavior. The effective permittivity of the structured regions may be modeled using the Lichtenecker mixing rule or models for columnar or layered structures and porosity.

[0067] Their electrical behavior may be tuned by adjusting trench depth, spacing, shape, and fill composition. Hexagonal packing of pillars may be useful for close spacing and uniform field distribution. The remaining semiconductor material between etched regions may contribute to mechanical strength, surface uniformity, and thermal conduction.-16-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0068] The structured dielectric regions may be left open, capped, or filled with a filler material. The filler material may include a gas, a porous material (e.g., a porous semiconductor or dielectric material), a solid nonporous dielectric (e.g., a nonporous semiconductor or dielectric material), a gas (e.g., air, dry air, argon, xenon, nitrogen, or a combination of any two or more thereof), or a combination of any two or more thereof. For example, the structured dielectric regions may be left open, capped, or filled with porous silicon or oxide, forming capacitive elements that further enhance substrate performance. These capacitive structures may interrupt conduction paths and allow displacement currents to flow along field lines, for example in coplanar RF configurations. For example, the dielectric material may include silicon oxide, germanium oxide, gallium oxide, or a combination of any two or more thereof. For example, the semiconductor may include silicon, gallium nitride, gallium arsenide, indium phosphide, germanium, or a combination of any two or more thereof. For example, the metal oxide may include aluminum oxide, yttrium oxide, zirconium oxide, niobium oxide, zinc oxide, hafnium oxide, titanium oxide, or a combination of any two or more thereof.

[0069] The porous material may be formed of particles. The particles may be spheroid, anisotropic, or may be high aspect ratio particles with the major axis of the particles generally perpendicular to the applied electric field and the minor axis generally parallel to the applied electric field. Where the filler material has lamellar porosity, the particles may be platelets or flakes with aspect ratios of 2 to 100 (e.g., two or greater). Platelets and flakes may have irregular cross-sections in the plane that is generally perpendicular to the applied electric field, but the dimensions of the particles may be on the same order of magnitude to be considered a platelet or flake. Where the filler material has lamellar porosity, the porous material may include a ribbon-shaped particle in which one dimension of the particle in the plane perpendicular to the electric field, the length of the ribbon, is much larger than the other dimension of the particle in the plane perpendicular to the electric field, the width. The aspect ratio of the ribbon-shaped particles may be about 10 to 1000. The porous material may include one or a combination of platelets or flakes and ribbon-shaped particles. A variation of sizes and types of the particles may be predetermined to control the structure and porosity in ways that a single particle size or particle type could not achieve. A dimension of the particles may be about 1 nm to about 1 pm (e.g., about 1 nm to about 500 nm, about 1 nm to about 200 nm, about-17-4833-5236-891 1.1Atty. Dkt. No. 132447-01111 nm to about 100 nm, about 1 nm to about 50 nm, about 1 nm to about 20 nm, about 1 nm to about 10 nm, or any value or subrange therebetween).

[0070] For example, the porous material may be silicon. Porous silicon may improve RF properties of SOI articles as compared to conventional RF SOI including traprich polysilicon layers between the BOX and bulk substrate. The porous silicon may be highly trap-rich, which may prevent or reduce conduction in the inversion layer. The porous silicon may have a low dielectric constant, so the capacitive coupling between the front-end electronics and bulk substrate may be reduced. Further, the performance advantages of porous silicon may be observed at higher temperatures (e.g., 175 °C), as compared to conventional HR-TR SOI.

[0071] A material’s permittivity is a parameter describing the degree of polarization of the material when in an externally applied electric field. While permittivity is a complex number that is a function of frequency, temperature, and field strength, the common term “dielectric constant” is used to denote the ratio of the real component of the complex permittivity with respect to the free space permittivity (i.e., the permittivity of vacuum). Solids and liquids have a dielectric constant greater than 2. This is denoted as esin the various equations. Gases have a dielectric constant slightly greater than 1. This is denoted as sPin the various equations. Composite materials, comprising of two or more materials with different formulations and / or dielectric constants, have an effective permittivity and effective dielectric constant. This is denoted as £ in various equations. The effective dielectric constant is dependent on the dielectric constants of the materials in the composite, the volume percentage of each material, and the arrangement or structure of the materials. While the term dielectric constant invokes the concept of an electrical insulator due to the inclusion of the word “dielectric”, permittivity and thus the dielectric constant may be applied to other materials, including semiconductors.

[0072] Porous dielectrics have been developed to reduce the dielectric constant from that of the solid material forming the physical and mechanical structure. Prior art on low dielectric constant porous dielectrics require a larger volume percentage of porosity, leading to a dielectric that is more than 50% gas. However, a larger volume percentage of porosity often degrades the other beneficial properties of the solid material. The larger volume percentage of porosity may reduce the material’s mechanical integrity, thermal-18-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 conductivity, and other properties. These issues may become more challenging when aiming to achieve exceptionally low dielectric constant materials. A dielectric constant below 2 is technically challenging because almost all solid materials have a dielectric constant above 2. A porous composite conventionally includes a large volume percentage of porosity for an effective dielectric constant less than 2, resulting in a decrease of the mechanical integrity and thermal conductivity of the material. Porosity may be classified as either homogeneous or structured. While a porous composite is a heterogeneous mixture, it may be described with a homogeneous effective medium representation if the solid and pore shapes and orientations are randomly distributed. Examples of homogeneous porous composites include foams, xerogels, and aerogels. Porous coatings formed through the depositions of powders that do not form a composite structure due to the random or distributed shape and orientation of the pores may also be described to have homogenous porosity. The dielectric constant for homogenous porosity has been derived in the literature from Maxwell’s equations to show that it follows the Lichtenecker rule. The equation for Lichtenecker’ s rule is

[0073] If the shapes and orientation of the solid and / or pores are not randomly distributed, the composite may be structured. A common implementation of structured porosity may be described as columnar porosity. In columnar porosity, the pores extend through part or all of the material as pillars, trenches, or similar shapes. Examples of columnar porosity are anodic aluminum oxide and electrochemically etched silicon. The effective dielectric constant of structured porous materials is often dependent on the orientation of the applied electric field with respect to the porous structure. For columnar porosity, the applied electric field may be parallel to the long axis of the columnar pores. In this case, the effective dielectric constant of columnar porosity may follow a simple weighted average of dielectric constants. £eyy = VSES+ vpEp. Conventionally, high volume percentage of porosity in the prior art is a problem for mechanical integrity and thermal compatibility, leading to product failures. Electrochemical etching processes for columnar porosity are also time consuming and use hazardous chemicals. This may lead to an increase in concern for worker and environmental protection.-19-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0074] To address the shortcomings of the porous columnar structure with respect to mechanical strength, thermal conductivity, and thermomechanical stability, structured dielectric regions disclosed herein may provide improvements. Structured dielectric regions including lamellar porosity (also referred to herein as “layered porosity”) disposed within cavities in the handle wafer may provide a layer-like structure that may be compacted such that it may not be easily crushed or otherwise harmed during wafer bonding or other processing. Mechanical forces perpendicular to a layer of lamellar dielectric structures are distributed and supported. Second, similar values of the effective dielectric constant achieved through columnar porosity may be reached with lamellar porosity at much lower levels of porosity.

[0075] The structured dielectric region may exhibit an effective resistivity higher than a resistivity of the crystalline semiconductor substrate. For example, the effective resistivity of the structured dielectric region may be at least 1% higher (e.g., 1% to 500%, 1% to 100%, 1% to 50%).

[0076] The filler material may exhibit an effective permittivity lower than a permittivity of the crystalline semiconductor substrate. For example, the filler material may exhibit an effective permittivity at least 1% less (e.g., 1% to 100%, 1% to 50%, 1% to 10%).Fabrication of Engineered Porous Structures

[0077] The structured regions may include engineered porous structures formed using plasma etching. The methods of making the structured regions may be free of doped substrates, etch-stop layers, and / or post-etch patterning. The present technology may also avoids the limitations of electrochemically etched porous silicon, which is characterized by nanometer-scale porosity that is mechanically fragile and prone to sintering at elevated temperatures, leading to wafer warping and stress.

[0078] The structures may be fabricated using plasma etching or other scalable techniques compatible with CMOS processing. No doped substrates, etch-stop layers, or post-etch patterning may be required. In some embodiments, porous material may be deposited using slurry-based or thermal methods. Oxide fill may be achieved using spin- on-glass or other dielectric deposition techniques.-20-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0079] A fabrication process flow diagram showing representative steps including trench etching, filler material deposition, and oxide layer formation is provided in FIG. 4. The process includes forming cavities 412 in the handle wafer 410 and forming the top device layer 430 with the BOX layer 420 disposed on a surface thereof (e.g., by formation of an oxide of the top device layer 430).

[0080] Cavities 412 in the handle wafer 410 may be formed by selectively etching the handle wafer 410 (e.g., by photolithography and DRIE). The cavities 412 may form pillar arrays, trenches, or a combination thereof. Photolithography may be used to arrange the cavities and / or pillars (e.g., spacing between pillars). The cavity shapes may include hexagonal shapes, triangular shapes, circular shapes, oval shapes, square shapes, square shapes with rounded comers, rectangular shapes, cruciform, or any combination of two or more thereof. The cavity shape may include an orientation, for example two orthogonal sets of cavities. Photolithography may be used to determine one or more dimensions of the pillars and cavities. The pillars may have a width, length, diameter, and / or other dimension of about 100 nm to about 1 mm (e.g., about 100 nm to about 10 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween). The cavities may have a width, length, diameter, and / or other dimension of about 100 nm to about 10 mm (e.g., about 100 nm to about 1 mm, about 100 nm to about 10 pm, about 100 nm to about 2 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween).

[0081] The amount of etching may determine the depth of the cavities 412 and the corresponding height of the pillars. The height of the pillars, and the corresponding depth of the cavities may be determined based on the resistivity of the handle wafer in which the structured dielectric layer is formed. For example, the handle wafer 410 may have a high resistivity (e.g., 1000 Ohm cm to about 10000 Ohm cm) and the depth of the cavities 412 may be less than 0.5 pm (e.g., about 0.05 pm to about 0.5 pm, about 0.1 pm to about 0.5 pm, or any value or subrange therebetween). For example, the handle wafer 410 may have a standard resistivity (e.g., about 1 Ohm cm to about 10 Ohm cm) and the depth of the cavities 412 may be greater than 5 pm (e.g., about 5 pm to about 2000 pm, about 5 pm to about 1500 pm, about 5 pm to about 1000 pm, about 5 pm to about 150 pm, about 5 pm to about 50 pm, about 5 pm to about 20 pm, or any value or subrange therebetween). For -21-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 example, the handle wafer 410 may have a low resistivity (e.g., less than 1 Ohm cm) and the depth of the cavities 412 may be greater than 0.5 pm (e.g., about 0.5 pm to about 1500 pm, about 0.5 pm to about 10 pm, about 0.5 pm to about 5 pm, about 0.5 pm to about 1 pm, or any value or subrange therebetween).

[0082] The etching step may include patterning the handle wafer 410 so that one or more regions of the handle wafer 410 remain unmodified, planar regions free of pillar structures and cavities.

[0083] In step 401, a powder (e.g., a silicon powder) is deposited into cavities 412 of the handle wafer 410 to provide a material 414 with porosity and improved thermomechanical properties. The filler material may be deposited via wet processing (e.g., application of a powder slurry). To achieve planarity of the deposited porous silicon, polishing of the wafer may be conducted such that the material 414 is planar with the top surface of the handle wafer 410.

[0084] In step 403, the handle wafer 410 including the porous material 414 are bonded to the BOX layer 420 and the top device layer 430. When bonding the handle wafer 410 with embedded porous material 414 to the top device wafer 430, there are regions of the silicon wafer (with or without oxide) that may participate in the wafer bonding to supplement the bond to the embedded porous silicon. This technique provides the capability of tuning the properties of the wafer along the entire wafer surface. Rather than having a single set of properties across the entire wafer, the properties at specific locations may be predetermined based on the presence or absence of the porous silicon layer.

[0085] FIG. 5 is a flow diagram of another method 500 of forming a structured dielectric layer. The method 500 includes step 510 of etching a crystalline semiconductor substrate to form a plurality of cavities and / or pillars on a surface of the crystalline semiconductor substrate.

[0086] Cavities and pillars in the handle wafer may be formed by selectively etching the handle wafer (e.g., by photolithography and DRIE). The cavities may form pillar arrays, trenches, or a combination thereof. Photolithography may be used to arrange the cavities and / or pillars (e.g., spacing between pillars). The cavity shapes may include-22-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 hexagonal shapes, triangular shapes, circular shapes, oval shapes, square shapes, square shapes with rounded comers, rectangular shapes, cruciform, or any combination of two or more thereof. The cavity shape may include an orientation, for example two orthogonal sets of cavities. Photolithography may be used to determine the dimension or feature size of the pillars and cavities. The pillars may have a width, length, diameter, and / or other dimension of about 100 nm to about 1 mm (e.g., about 100 nm to about 10 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween). The cavities may have a width, length, diameter, and / or other dimension of about 100 nm to about 10 mm (e.g., about 100 nm to about 1 mm, about 100 nm to about 10 pm, about 100 nm to about 1 pm, about 100 nm to about 500 nm, about 100 nm to about 200 nm, or any value or subrange therebetween).

[0087] The amount of etching may determine the depth of the cavities and the corresponding height of the pillars. The height of the pillars, and the corresponding depth of the cavities may be determined based on the resistivity of the handle wafer in which the structured dielectric layer is formed. For example, the handle wafer may have a high resistivity (e.g., 1000 Ohm cm to about 10000 Ohm cm) and the depth of the cavities may be less than 0.5 pm (e.g., about 0.05 pm to about 0.5 pm, about 0.1 pm to about 0.5 pm, or any value or subrange therebetween). For example, the handle wafer may have a standard resistivity (e.g., about 1 Ohm cm to about 10 Ohm cm) and the depth of the cavities may be greater than 5 pm (e.g., about 5 pm to about 2000 pm, about 5 pm to about 1500 pm, about 5 pm to about 1000 pm, about 5 pm to about 150 pm, or any value or subrange therebetween). For example, the handle wafer may have a low resistivity (e.g., less than 1 Ohm cm) and the depth of the cavities 412 may be greater than 0.5 pm (e.g., about 0.5 pm to about 1500 pm, about 0.5 pm to about 10 pm, about 0.5 pm to about 5 pm, about 0.5 pm to about 1 pm, or any value or subrange therebetween).

[0088] The etching step 510 may include patterning the crystalline semiconductor so that one or more regions of the crystalline semiconductor remain unmodified, planar regions free of pillar structures and cavities.

[0089] The method 500 includes step 520 of disposing a filler material in regions separating the plurality of pillars. The filler material may include a gas, a porous material (e.g., a porous semiconductor or dielectric material), a solid nonporous dielectric (e.g., a-23-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 nonporous semiconductor or dielectric material), a gas (e.g., air, dry air, argon, xenon, nitrogen, or a combination of any two or more thereof), or a combination of any two or more thereof.

[0090] Porous materials may be deposited onto a handle wafer using wet deposition techniques based on slurry dispersions of particles or nanoflakes in a fluid carrier. Slurries may use any suitable fluid carrier, such as deionized water, aminomethyl propanol, isopropyl alcohol, and other solvents. Solid particulates in the slurry may range from about 10% to about 40% by weight. Additives for particulate dispersion, surface tension modification, defoaming, and binding of particulates may be included at weight percentages of 0.1% to 5%. The slurries may be mixed by stirring, ultrasonic agitation, or planetary centrifugal mixing. The slurries may be coated with any suitable technique, such as doctor blading and spin coating.

[0091] The method 500 may further include bonding the handle wafer including the porous regions to the BOX layer and the device layer to form an SOI or POI article. When bonding the handle wafer with embedded porous silicon to the top silicon wafer, there are regions of the silicon wafer (with or without oxide) that may participate in the wafer bonding to supplement the bond to the embedded porous silicon.

[0092] A comparative chart summarizing the characteristics of conventional SOI, HR-TR SOI, electrochemically etched porous silicon, and the structured dielectric region approach described herein is provided in Table 1, below.Table 1 : Characterization of SOI Articles-24-4833-5236-891 1.1Atty. Dkt. No. 132447-0111Applications of Engineered Porous Structures

[0093] The present technology is effective across a range of substrate resistivities. In high-resistivity wafers, shallow trenches may interrupt conduction in the thin parasitic layer near the BOX. In lower-resistivity wafers, deeper trenches are used to disrupt conduction governed by RF skin depth, allowing displacement currents to dominate. This flexibility allows the present technology to be implemented using both high-resistivity and cost-effective standard substrates.

[0094] The present technology supports a spectrum of porosity and dielectric behavior, providing tailored substrate designs for RF communications, acoustic wave devices, and monolithic active pixel sensors. By addressing the limitations of existing substrate technologies, this present technology offers a versatile and manufacturable solution for improving the electrical and mechanical properties of engineered substrates used in advanced electronic and photonic systems.

[0095] The present technology, thus generally described, will be understood more readily by reference to the following examples, which are provided by way of illustration and are not intended to be limiting of the present invention.EXAMPLES

[0096] Example 1. Dielectric Constant and Permittivity of Different Porosity Configurations4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0097] Graphs comparing dielectric constant and effective permittivity for different materials are shown in FIGs. 6A-7B, including homogenous, columnar, and layered porosity composites.

[0098] FIGS. 7A-7B illustrate how effective dielectric constant values demonstrated to be effective with columnar porosity at porosity levels of 65 - 75% may be achieved with layered porosity with porosity at just 20-30%. The larger difference for a solid dielectric constant of 10 occurs at a volume percentage of pores of approximately 50% at which the effective dielectric constant with lamellar porosity is approximately 66.9% lower than columnar porosity. The higher solids loading of the lamellar porous structure provides enhanced mechanical strength, better thermal conduction, and better thermomechanical stability.

[0099] FIG. 6A-6B compare effective dielectric constant of columnar and lamellar (i.e., layered) porous composites with a solid dielectric constant of 10. FIG. 6A plots the dielectric constant of these two porous composite arrangements with respect to the volume percentage of pores, ranging from 0 to 100%. The effective dielectric constants were equal in the extreme cases of 0 and 100% volume percentage pores, but they differed significantly at values between these extremes. The effective dielectric constant of the lamellar porous composite was significantly lower than the effective dielectric constant of the columnar composite.

[0100] FIGS. 7A-7B compare the effective dielectric constant of homogeneous and lamellar (i.e., layered) porous composites with a solid dielectric constant of 10. FIG. 7A plots the dielectric constant of these two porous composite arrangements with respect to the volume percentage of pores, ranging from 0 to 100%. The effective dielectric constants were equal in the extreme cases of 0 and 100% volume percentage pores, but they differed significantly at values between these extremes. The effective dielectric constant of the lamellar porous composite was significantly lower than the effective dielectric constant of the homogeneous porous composite. The larger difference in the effective dielectric constant from lamellar porosity compared to homogeneous porosity was greater than approximately 46.1% at approximately 32% volume of pores.

[0101] Dielectric constant values provided in these figures indicated two of the applications of lamellar porosity to reduce the effective dielectric constant. First, the -26-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 dielectric constant of 10 is representative of several dielectrics (e.g., diamond, aluminum oxide, aluminum nitride, etc.) and semiconductors (e.g., silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, germanium, or a combination of any two or more thereof) that have dielectric constants within ±15% of this value. To achieve a dielectric constant of 3.5 or less with these materials, the volume percentage of pores with homogenous and columnar porosity would be at or above approximately 45% and 72%, respectively. With lamellar porosity, an effective dielectric constant of 3.5 or less may be achieved with a volume percentage of pores as low as approximately 21%. The higher solid volume percentage in the porous composite with lamellar porosity provides advantages in mechanical strength and thermal conductivity.

[0102] Example 2. Formation of SOI with Structured Dielectric Region

[0103] The following process describes an example of integrating a layer of structured dielectric region, including a layer incorporating nanoscale lamellar porosity, into an engineered substrate for silicon on insulator or piezo on insulator applications. The process started with two commercially available substrates. One substrate formed the primary device layer, in or on which the electronics, conductors, or other functional elements may be fabricated. This substrate had an oxide layer on at least one surface that later formed the buried oxide layer. The other commercial wafer formed the bulk or handle layer. This handle layer was modified with a layer of the dielectric structures and integrated with the wafer including the buried oxide layer to form the complete engineered substrate. Onto the bulk substrate, a porous layer was coated using a wet-deposition techniques based on nanoscale flakes in a slurry.

[0104] A slurry was made to deposit the porous Si layer applicable to a silicon wafer. After a dispersion of silicon nanoflakes in deionized (DI) water is sonicated, centrifugation is used to reduce the liquid content and separate ultrafine particles from the bulk of the nanoflakes. The nanoflakes were then dispersed in aminomethyl propanol [H2NC(CHS)2CH2OH], DI water, and WTO 15 silicone copolymer from Polymer Innovations. The copolymer increased the wetting of the powders. This slurry was mixed with a Flacktek Speedmixer, which uses a planetary centrifugal mixing method.

[0105] The two wafers were bonded with the BOX layer bonded to the porous silicon. To simplify manufacturing and avoid the chemical mechanical planarization-27-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 process to achieve the surface roughness for direct bonding, a spin-on-glass (SOG) was applied between the BOX and porous layers. This SOG acted as both an adhesive layer in the bonding process and a small additional insulating layer (about 50 nm in thickness).

[0106] There have been demonstrations of implementing this type of porous Si in the engineered substrate. The electrical performance was shown to reduce capacitive coupling between the device layer and handle wafer, effectively mitigate the parasitic conduction layer, and significantly reduce cross-talk on top-layer devices.

[0107] Commercially available silicon powders from multiple manufacturers were investigated, with selected powders being further evaluated via scanning electron microscopy (SEM) for comparison of characteristics and quality. Favorable selection criteria included particle size, size distribution and particle shape, aspect ratio (flake geometry), purity / composition, and cost and availability.

[0108] A slurry was made to deposit the porous Si layer applicable to a silicon wafer. After a dispersion of 9723HK silicon nanoflakes in deionized (DI) water was sonicated, centrifugation was used to reduce the liquid content and separate ultrafine particles from the bulk of the nanoflakes. The nanoflakes were then dispersed in aminomethyl propanol [EEN CHs^CEEOH], DI water, and WTO 15 silicone copolymer from Polymer Innovations. The copolymer increased the wetting of the powders. This slurry was mixed with a Flacktek Speedmixer, which used a planetary centrifugal mixing method.

[0109] Wafer substrates were prepared by rinsing with a sequence of acetone, methanol, and isopropyl alcohol to remove any dust or particles. A wafer to be coated was set in a plastic template and the slurry was loaded directly on the template. A doctor blade with known gap size was used to push the slurry from the template across the wafer in one pass. The doctor blade and template were then removed and the wafer on an alumina plate was transferred to a furnace for heat treatment (10 °C / min ramp up, 4 hours dwell at 700 °C in ambient atmosphere, 10 °C / min ramp down). After heat treatment, the wafer substrates are dried and organic compounds were removed. The remaining coating was a porous network of silicon nanoflakes that adhered to the wafer. Thus, it was demonstrated that the porous layer may be fabricated to adhere to the base wafer and have cohesion with-28-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 itself without the use of binders or other contaminants, maintaining an all Si-SiCh substrate.

[0110] FIG. 8 A is an image of a cross-section of a coated substrate. The HSQ- treated, porous-silicon coating layer is shown in a fractured specimen prepared for tilt plane surface characterization. The image shows the general topography of the porous silicon layer, which has been reduced by the application of the HSQ SiCh film surface. The porous silicon layer is approximately 12 pm in thickness, while the HSQ layer is approximately 200 nm in the analyzed region.

[0111] Handle wafers comprising porous cavities were also fabricated. FIG. 8B is a photograph of an etched wafer with porous silicon deposited in cavities. FIG. 8C is an optical microscopy image of individual cavities with a length of 1,000 pm and width from 10 to 40 pm.

[0112] Example 3. Electrical Measurements of Porous Materials

[0113] The first set of electrical measurements were taken using a four-point probe (Lucas Labs). This simple characterization method enables measurement of each layer (bare Si wafer, porous Si on Si wafer, and HSQ on either a bare Si wafer or on a Si porous layer on Si wafer) individually. Since calculation of the layer resistivity includes both the thickness of each layer and assumptions about measurement impacts from lower layers, the sheet resistance is reported here as a means of comparison. A porous Si layer of 30 pm has a sheet resistance ten orders of magnitude greater than the standard resistivity Si wafer that supports it. However, the porous layer has not been converted into a highly resistive oxide. For comparison, the HSQ was demonstrated to be a very effective oxide insulator with sheet resistances on the order of 1014- 1015Q / sq. The level of conductivity of the porous Si layer indicates that it may accept charge from the parasitic conduction layer, as desired, while being a trap-rich, resistive layer in which there is low charge mobility.Table 2. Order of magnitude of sheet resistance for layers of SOI Articles-29-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0114] RF testing was conducted by depositing coplanar waveguide patterns on top of the test article. The RF test setup used to evaluate such articles is illustrated in FIG. 9A, which includes both cross-sectional and top-down views of the coplanar waveguide (CPW) structures. The test articles described here were: 1. An article incorporating the new porous Si layer on top of a standard resistivity Si wafer (1 - 10 Q-cm) with a layer of HSQ on top to form an oxide (Wafer designated S4); 2. An article without the porous layer, consisting of a layer of PECVD-deposited oxide on a standard resistivity Si wafer (1 - 10 Q-cm) (Wafer designated SI); 3. An article without the porous layer, consisting of a layer of HSQ-deposited oxide on a low resistivity Si wafer (1 - 10 Q-cm) (Wafer designated S2). The wafers were processed through lithography and deposition processes, which demonstrated the article with the porous layer’s compatibility with Al etch, piranha etch, and high vacuum processes.

[0115] The three articles were tested and compared for RF harmonic distortion at 900 MHz, the characteristic impedance and effective permittivity vs. frequency, and crosstalk vs. frequency. These are the standard tests for evaluating SOI articles for RF applications. The measurements indicate the level of coupling, or reduction thereof, between the device layer and handle wafer based on the layers between and provide direct information on the expected level of cross-talk between adjacent devices built upon SOI or POI articles incorporating layers with dielectric structures.

[0116] FIGs. 10A and 10B show the harmonic distortion for the second (H2 - left) and third (H3 - right) harmonics for the three wafers. The harmonic distortion was significantly lower (e.g., greater than 50 dBm reduction) for the wafer with the porous layer (S4) compared to the articles without the porous layer. This harmonic distortion data indicated that the porous layer significantly reduced the effects of the parasitic conduction layer that forms below the BOX, provided a trap-rich and highly resistive layer, and reduced the capacitive coupling between the device layer and handle wafer.

[0117] FIGs. 10C and 10D compare the characteristic impedance (FIG. 10C) and effective permittivity (FIG. 10D) of the three articles. Again, the data indicated that the article incorporating the porous Si layer offered highly differentiated performance. Due to the porous layer, the characteristic impedance was much higher, and the effective-30-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 permittivity was much lower. This data indicated the significant reduction in capacitive coupling between the device layer and the handle wafer.

[0118] FIG. 11 compares the cross-talk levels for the three wafers. Again, the performance of the article with the porous layer (S4) indicated significantly improved performance by reducing cross-talk, especially at frequencies above 200 kHz. It is noted that even though these test articles were fabricated on standard resistivity Si wafers, the cross-talk performance of the article with the porous layer had S21 levels 20 dB lower than even a commercially available high resistivity SOI article with a traditional trap-rich layer. This cross-talk data indicated that articles with the porous layer may significantly reduce cross-talk between devices in the device layer, improving signal-to-noise and data integrity.

[0119] This data indicates that dielectric structures based on porous silicon formed with larger dimensions and deposition techniques are effective at improving the RF properties of substrates for SOI and POI applications. These alternative dielectric structures may be implemented in multiple embodiments and improve the mechanical strength, thermal conductivity, and thermomechanical stability over fine porous silicon from electrochemical etching.

[0120] Example 4. Fabrication of SOI Wafers with Structured Dielectric Regions

[0121] Test wafers fabricated according to the process described with respect to FIG. 4 were designed and etched with test cavity patterns. The initial set of cavities were designed to evaluate the effect of cavity size (varied in three sets from 500 to 1,500 pm in length and 30 widths from 10 to 1,000 pm), shape (square and rounded comers at each width and length combination), and orientation (two orthogonal sets of cavities). The cavity structures were implemented through a process of photolithography and deep reactive ion etching (DRIE). The typical etch depth for these cavities was 10 pm.

[0122] Through testing of porous silicon deposition in these cavities, it was determined that multiple deposition techniques, including doctor blade and spin coating, are used to deposit the porous silicon into all sizes, shapes, and orientations of the cavities.-31-4833-5236-891 1.1Atty. Dkt. No. 132447-0111However, it was also observed that the larger cavities were prone to having the unannealed porous silicon removed from the central regions of the cavities.

[0123] To both provide implementation of the embedded porous silicon at any size, including across the entire wafer, and mitigate risk of removal of the porous silicon from the cavities, silicon supports were integrated into the design of the cavities. These silicon supports were implemented in a range of shapes, sizes, and spacings to design for specific wafer properties and optimize for deposition and other wafer processing steps. The shapes of the supports included simple cylindrical posts, crosses (also called X- shaped), and several other shapes, but many supports were implemented as hexagonal pillars. Hexagons are one of a set of shapes that tesselate when the gap spacing is reduced towards zero. Thus, the gaps between all pillar supports may be equal throughout. FIGs. 12A-12B shows SEM images of two implementations of support size and spacing. On the small end of the pillar size spectrum, FIG. 12A shows pillars designed for a hexagon size of 7.5 pm with a spacing between supports of 35 pm. In FIG. 12B, the spacing between hexagons is minimized for maskless photolithography equipment (e.g., MLA150) at about 0.6 pm, and the hexagon size is 15 pm. In both cases, there is evidence of some loss of resolution through the photolithography and etching steps. This is evidenced by the rounding of the 7.5 pm hexagons on the left and spacing between the large hexagons on the right being larger than 1 pm. While these issues do not prevent the success of subsequent deposition of the porous silicon, this loss of resolution are minimized with improved lithography with finer resolution and reduction of lateral etching during DRIE.

[0124] Porous silicon was deposited into the etched structures using wet deposition processes, thoroughly filling between the support structures. As shown in FIG. 13 A, the porous silicon fills the gaps between the support structures (lower right) and is on an even plane with the surrounding unetched silicon (upper left). FIG. 13B shows a closer image of the porous silicon between the silicon pillars prior to polishing.

[0125] After deposition of the porous silicon, it was annealed to improve its mechanical properties for subsequent polishing and wafer bonding. The annealing process was implemented in a controlled atmosphere furnace. A rough vacuum was pulled on the furnace followed by a flow of argon to reduce the oxygen concentration. As a measure to further reduce oxygen concentrations at the wafers, a quartz tube was implemented. This-32-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 atmospheric control in the furnace demonstrated annealing of the porous silicon to achieve improved mechanical strength and hardness without excessive oxidation.

[0126] An effective means of evaluating the porosity of the deposited silicon is by examining a cross-section after annealing. Preparing a cross-section is enabled using focused ion beam (FIB) milling within the scanning electron microscope (SEM). FIG. 15 provides an example of a porous cross-section imaged after milling with the FIB. While some distortion of the porosity is expected due to the milling action of the ion beam, the porosity is preserved such that the desired structure and interfaces may be verified.

[0127] Example 5. Electrical Measurements of SOIs with Structured Dielectric Regions

[0128] Improvements to the RF properties of engineered articles incorporating localized layers with structured dielectrics have been demonstrated. The following data describes testing of articles incorporating structured dielectric layers in substrates that had a standard resistivity of 1 - 10 Ohm-cm prior to modification with the structured dielectric layers. The structured dielectric layer consisted of localized regions of hexagons with dimensions of 5 microns separated by a distance of 0.6 microns. The 3” test substrate included 12 localized regions of the structured dielectric layers with each localized region having a rectangular area of 2 mm by 3 mm. The hexagonal patterns were defined through standard lithographic techniques, such as the use of a Heidelberg MLA150 Maskless Lithography system or JEOL 81 OOFS Electron Beam Lithography System. The hexagonal pillar structure was etched using DRIE tools such as the PlasmaTherm Deep Reactive Ion Etcher for Silicon. Typical depths of etching ranged from 5 to 20 microns, and the following results are for an etch depth of 7 microns.

[0129] The article including the handle layer included unmodified standard resistivity silicon, and the layer incorporating localized regions of structured dielectrics may be implemented with the etched pores between hexagonal pillars left empty with only vacuum or gas filling the pores, partially filled with solids to maintain partial porosity, or fully filled with solids. All three embodiments are options when bonding to the modified handle wafer to form the complete SOI or POI article. However, when depositing an oxide layer onto the handle wafer rather than wafer bonding, as was done to prepare test substrates, it is often useful to fill the pores between pillars. For RF testing, an insulating -33- 4833-5236-891 1.1Atty. Dkt. No. 132447-0111 oxide is deposited across the top surface through a plasma enhanced chemical deposition (PECVD) process, so the pores between the hexagonal pillars were filled by an electrically insulating epoxy (e.g., EpoxyBond 14 from Allied). The oxide deposited by PECVD was approximately 400 nm thick. Aluminum contacts were deposited onto the PECVD, lithographically patterned for coplanar waveguides for RF testing, and etched to remove the aluminum from all other areas.

[0130] FIG. 16 provides data for the second and third harmonic (H2 and H3, respectively) when coplanar waveguides were driven at 900 MHz at power levels between -20 and +35 dBm. There is a demonstrated reduction in H2 and H3 across power levels due to the use of the structured dielectric layer. The reduction in H2 and H3 is greater than 25 dBm.

[0131] FIG. 17 provides experimental data of the cross-talk as measured between 100 kHz and 3 GHz. Compared to similar articles without the layer of structured dielectrics, the cross-talk was reduced.

[0132] While certain embodiments have been illustrated and described, it should be understood that changes and modifications can be made therein in accordance with ordinary skill in the art without departing from the technology in its broader aspects as defined in the following claims.

[0133] The embodiments, illustratively described herein may suitably be practiced in the absence of any element or elements, limitation or limitations, not specifically disclosed herein. Thus, for example, the terms “comprising,” “including,” “containing,” etc. shall be read expansively and without limitation. Additionally, the terms and expressions employed herein have been used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the claimed technology. Additionally, the phrase “consisting essentially of’ will be understood to include those elements specifically recited and those additional elements that do not materially affect the basic and novel characteristics of the claimed technology. The phrase “consisting of’ excludes any element not specified.-34-4833-5236-891 1.1Atty. Dkt. No. 132447-0111

[0134] The present disclosure is not to be limited in terms of the particular embodiments described in this application. Many modifications and variations can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods and compositions within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is to be understood that this disclosure is not limited to particular methods, reagents, compounds, compositions, or biological systems, which can of course vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

[0135] In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group.

[0136] As will be understood by one skilled in the art, for any and all purposes, particularly in terms of providing a written description, all ranges disclosed herein also encompass any and all possible subranges and combinations of subranges thereof. Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into at least equal halves, thirds, quarters, fifths, tenths, etc. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc. As will also be understood by one skilled in the art all language such as “up to,” “at least,” “greater than,” “less than,” and the like, include the number recited and refer to ranges which can be subsequently broken down into subranges as discussed above. Finally, as will be understood by one skilled in the art, a range includes each individual member.

[0137] All publications, patent applications, issued patents, and other documents referred to in this specification are herein incorporated by reference as if each individual publication, patent application, issued patent, or other document was specifically and individually indicated to be incorporated by reference in its entirety. Definitions that are-35-4833-5236-891 1.1Atty. Dkt. No. 132447-0111 contained in text incorporated by reference are excluded to the extent that they contradict definitions in this disclosure.

[0138] Other embodiments are set forth in the following claims.4833-5236-891 1.1

Claims

Atty. Dkt. No. 132447-0111WHAT IS CLAIMED IS:

1. An article comprising: a crystalline semiconductor substrate; a structured dielectric region disposed on the crystalline semiconductor substrate; an insulating oxide layer disposed on the structured dielectric region; and a device layer disposed on the insulating oxide layer, the device layer comprising a crystalline semiconductor or piezoelectric material; wherein: the structured dielectric region comprises: a plurality of pillars extending from the crystalline semiconductor substrate, and a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor material, vacuum, a gas, or a combination of any two or more thereof disposed in regions separating the plurality of pillars; each pillar of the plurality of pillars has a width of about 100 nm to about 40 pm; the plurality of pillars are formed of the crystalline semiconductor substrate; and the structured dielectric region exhibits an effective resistivity higher than a resistivity of the crystalline semiconductor substrate, or the filler material exhibits an effective permittivity lower than a permittivity of the crystalline semiconductor substrate.

2. The article of claim 1, wherein the insulating oxide layer is further disposed on portions of the crystalline semiconductor substrate free of the structured dielectric region.

3. An article comprising: a crystalline semiconductor substrate comprising a surface having a plurality of pillars extending therefrom, and a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor-37--5236-891 1.1Atty. Dkt. No. 132447-0111 material, vacuum, a gas, or a combination thereof disposed in regions separating the plurality of pillars; wherein: each pillar of the plurality of pillars has a width of about 100 nm to about 40 pm; the plurality of pillars are formed of the crystalline semiconductor substrate; and a combination of the plurality of pillars and the filler material exhibits an effective resistivity higher than a resistivity of the crystalline semiconductor substrate, or the filler material exhibits an effective permittivity lower than a permittivity of the crystalline semiconductor substrate.

4. The article of claim 3, wherein the crystalline semiconductor substrate further comprises planar regions free of the plurality of pillars.

5. The article of any one of claims 1-4, wherein each pillar of the plurality of pillars is spaced apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 100 pm.

6. The article of any one of claims 1-5, wherein each pillar of the plurality of pillars is spaced apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 2 pm.

7. The article of any one of claims 1-6, wherein each pillar of the plurality of pillars is uniformly spaced apart from each other pillar of the plurality of pillars.

8. The article of any one of claims 1-7, wherein the filler material comprises the porous dielectric material, and the porous dielectric material comprises a dielectric material having a plurality of pores dispersed throughout the dielectric material.

9. The article of claim 8, wherein the plurality of pores comprise a lamellar porosity.

10. The article of any one of claims 1-7, wherein the filler material comprises the nonporous dielectric material or a nonporous semiconductor material.-38--5236-891 1.1Atty. Dkt. No. 132447-011111. The article of claim 10, wherein the nonporous dielectric material comprises a ceramic or a polymer.

12. The article of claim 7, wherein the filler material comprises the porous semiconductor material or nonporous semiconductor material and the porous semiconductor material or nonporous semiconductor material comprises an amorphous semiconductor material or a polycrystalline semiconductor material.

13. The article of any one of claims 1-12 further comprising a planar surface oxide disposed on the plurality of pillars.

14. The article of any one of claims 1-13, wherein the crystalline semiconductor substrate comprises silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, or germanium.

15. The article of any one of claims 1-14, wherein each pillar of the plurality of pillars has a triangular, rectangular, square, ovular, circular, cruciform, or hexagonal cross- sectional shape.

16. A monolithic active pixel sensor comprising the article of any one of claims 1-15.

17. An article comprising: a plurality of pillars disposed on a crystalline semiconductor substrate, the plurality of pillars comprising a crystalline semiconductor, each pillar of the plurality of pillars having a width of about 100 nm to about 40 pm; and a porous dielectric material or porous semiconductor material disposed around the plurality of pillars, the porous dielectric material or porous semiconductor material having a plurality of pores dispersed throughout the porous dielectric material or porous semiconductor material.

18. The article of claim 17, wherein the porous dielectric material or porous semiconductor material comprises a lamellar porosity.

19. A method of making an article, the method comprising:-39--5236-891 1.1Atty. Dkt. No. 132447-0111 etching a crystalline semiconductor substrate to form a plurality of pillars on a surface of the crystalline semiconductor substrate, each pillar of the plurality of pillars having a width of about 100 nm to about 40 pm; and disposing a filler material comprising a porous dielectric material, a nonporous dielectric material, a porous semiconductor material, a nonporous semiconductor material, or a combination thereof in regions separating the plurality of pillars.

20. The method of claim 19, wherein the filler material comprises the porous dielectric material or the porous semiconductor material, wherein the porous dielectric material or the porous semiconductor material comprises a plurality of pores dispersed throughout the porous dielectric material or the porous semiconductor material.

21. The method of claim 20, wherein the plurality of pores comprises a lamellar porosity.

22. The method of claim 19, wherein the filler material comprises the nonporous dielectric material or the nonporous semiconductor material.

23. The method of any one of claims 19-22, wherein the etching comprises spacing each pillar of the plurality of pillars apart from another pillar of the plurality of pillars by a distance of about 100 nm to about 100 pm.

24. The method of any one of claims 19-23, wherein the etching comprises spacing each pillar of the plurality of pillars uniformly apart from each other pillar of the plurality of pillars.

25. An article comprising: a substrate comprising a crystalline semiconductor and a discrete region within the crystalline semiconductor, the discrete region comprising a porous dielectric material or a porous semiconductor; an insulating oxide layer disposed on the substrate; and a device layer disposed on the insulating oxide layer, the device layer comprising a crystalline semiconductor or piezoelectric material.-40--5236-891 1.1Atty. Dkt. No. 132447-011126. The article of claim 25, wherein the porous dielectric material or porous semiconductor material comprise a lamellar porosity. -5236-891 1.1

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