Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes a substrate, a metal layer, a shielding layer, and a pixel electrode layer. The metal layer is disposed on the substrate. The shielding layer is disposed on the metal layer. The pixel electrode layer is disposed on the side of the shielding layer opposite to the metal layer. The shielding layer shields the capacitive coupling between the metal layer and the pixel electrode layer. The metal layer and the pixel anode layer form a capacitor. When the voltage signal of the metal layer changes, the metal layer can affect the voltage signal of the pixel anode layer through the capacitive coupling formed between them, thus causing display abnormalities in the display panel. In this application, the shielding layer is disposed between the metal layer and the pixel anode layer. Changes in the voltage signal of the metal layer will act on the shielding layer and will not affect the pixel anode layer. This achieves the shielding of the capacitive coupling between the metal layer and the pixel anode layer, thereby eliminating the capacitive coupling phenomenon, eliminating display abnormalities in the display panel, and improving the quality of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display panels and display devices. Background Technology

[0002] With the continuous development of LCD technology, the wide viewing angle, low power consumption, and high charging rate of LCDs have become important performance indicators for measuring product advancement. As LCDs become more widespread, consumers are increasingly inclined towards larger and brighter displays. Among them, TFT-LCD (Thin Film Transistor Liquid Crystal Display) LCDs have a higher charging rate than other types of LCDs, resulting in higher display brightness. However, traditional TFT-LCD LCDs are prone to capacitive coupling, causing display abnormalities. Summary of the Invention

[0003] Therefore, it is necessary to provide a display panel and display device to address the problem that traditional TFT-LCD liquid crystal displays are prone to capacitive coupling, which can cause abnormal display phenomena.

[0004] To achieve the above objectives, in one aspect, embodiments of this application provide a display panel, including:

[0005] Substrate;

[0006] A metal layer is disposed on the substrate;

[0007] A shielding layer is disposed on the metal layer and is provided with insulation from the metal layer; and

[0008] The pixel electrode layer is disposed on the side of the shielding layer away from the metal layer and is insulated from the shielding layer by a gap.

[0009] The shielding layer shields the capacitive coupling between the metal layer and the pixel electrode layer.

[0010] In one embodiment, the metal layer includes a plurality of spaced data lines, the pixel electrode layer includes a plurality of spaced pixel electrodes, and the shielding layer shields the capacitive coupling between the data lines and the pixel electrodes.

[0011] In one embodiment, the display panel includes N pixel units; the metal layer includes a plurality of spaced data lines, and the pixel electrode layer includes a plurality of spaced pixel electrodes, each pixel electrode including a main stem and a branch connected to the main stem;

[0012] Each pixel unit includes at least one data line and one pixel electrode; the orthographic projection of the data line onto the plane containing the pixel electrode covers at least a portion of the main body of the pixel electrode; or

[0013] The orthographic projection of the data line onto the plane containing the pixel electrode is located between two adjacent pixel units.

[0014] In one embodiment, the pixel unit includes a first data line and a second data line, which are arranged in parallel and spaced apart.

[0015] The orthographic projection of the first data line onto the plane where the pixel electrode is located covers at least a portion of the main body of the pixel electrode;

[0016] The orthographic projection of the second data line onto the plane containing the pixel electrode is located between two adjacent pixel units.

[0017] In one embodiment, the N pixel units are arranged in a matrix in both the horizontal and vertical directions;

[0018] In the same column, the first data lines of adjacent pixel units are connected, and the second data lines are connected.

[0019] In one embodiment, the N pixel units are arranged in a matrix in both the horizontal and vertical directions;

[0020] In a column, the first data line of a pixel unit is connected to the second data line of another pixel unit adjacent to it in the same column; the second data line of a pixel unit is connected to the first data line of another pixel unit in an adjacent column and an adjacent row.

[0021] In one embodiment, the N pixel units are arranged in a matrix in both the horizontal and vertical directions;

[0022] In some pixel units, the first data line of one pixel unit is connected to the first data line of another adjacent pixel unit located in the same column, and the second data line of the same pixel unit is connected to the second data line of the adjacent pixel unit located in the same column.

[0023] In another part of the pixel units, the first data line of one pixel unit is connected to the second data line of another adjacent pixel unit located in the same column; the second data line of the one pixel unit is connected to the first data line of another pixel unit located in an adjacent column and adjacent row.

[0024] In one embodiment, the shielding layer transmits a voltage signal, and in another embodiment, the voltage signal transmitted on the shielding layer is the same as the voltage signal transmitted on the metal layer.

[0025] In one embodiment, the display panel further includes a thin-film transistor, one of the source and drain electrodes of the thin-film transistor being connected to a metal layer, and the other of the source and drain electrodes of the thin-film transistor being connected to a pixel electrode layer.

[0026] On the other hand, a display device is provided, including a control motherboard and a display panel as described above; the control motherboard is electrically connected to the display panel.

[0027] One of the above technical solutions has the following advantages and beneficial effects:

[0028] The display panel provided in the embodiments of this application includes a substrate, a metal layer, a pixel electrode layer, and a shielding layer. In the display panel structure, the metal layer is disposed on the substrate. The shielding layer is disposed on the metal layer. The pixel electrode layer is disposed on the side of the shielding layer opposite to the metal layer. In conventional display panel structures, the metal layer and the pixel electrode layer are disposed opposite each other, with other material layers between them. The metal layer and the pixel electrode layer form a capacitor. When the voltage signal of the metal layer changes, the metal layer will affect the voltage signal of the pixel electrode layer through the capacitive coupling formed between them, thereby causing display abnormalities in the display panel. In this application, the shielding layer is disposed between the metal layer and the pixel electrode layer. Changes in the voltage signal of the metal layer will act on the shielding layer and will not affect the pixel electrode layer. The shielding layer blocks the capacitive coupling between the metal layer and the pixel electrode layer, thereby eliminating the capacitive coupling phenomenon, eliminating display abnormalities in the display panel, and improving the quality of the display panel. Attached Figure Description

[0029] Figure 1 A schematic diagram of a display panel provided for implementation of this application.

[0030] Figure 2 A schematic diagram of a display panel provided for implementation of this application.

[0031] Figure 3 A schematic diagram of a display panel provided for implementation of this application.

[0032] Figure 4 A schematic diagram of the pixel electrode layer provided for implementation of this application.

[0033] Figure 5 A schematic diagram of a pixel unit provided for implementation of this application.

[0034] Figure 6 A schematic diagram of a pixel unit provided for implementation of this application.

[0035] Figure 7 A schematic diagram of a pixel unit provided for implementation of this application. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0037] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to and integrated with the other component, or there may be an intervening component present. The terms "mounted," "one end," "the other end," and similar expressions used in this document are for illustrative purposes only.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] A typical liquid crystal display (LCD) panel includes a control motherboard, backlight, lower polarizer, driver substrate, liquid crystal layer, color filters, and upper polarizer. The control motherboard controls the entire LCD panel; for example, it connects to the driver substrate and provides various signals to control it. The backlight provides light to the LCD panel; in one example, it could be a cold cathode fluorescent lamp (CCFL) or a light-emitting diode (LED). The lower and upper polarizers polarize the natural light emitted from the backlight. The liquid crystal layer changes its alignment under the influence of an electric field, thus altering the light transmission. Color filters select a small range of wavelengths of light to pass through, including blue, red, and green filters.

[0040] The metal layer 11 on the driving substrate (not shown) is capacitively coupled to the pixel electrode layer 13. Due to this capacitive coupling, changes in the voltage signal on the metal layer 11 affect the pixel electrode layer 13, causing instability in the voltage signal on the pixel electrode layer 13. This affects the liquid crystal rotation on the liquid crystal layer, resulting in display abnormalities. To solve this problem, such as... Figure 1As shown, this application provides a display panel. The display panel includes a substrate (not shown), a metal layer 11, a pixel electrode layer 13, and a shielding layer 15. The substrate supports the metal layer 11, the pixel electrode layer 13, and the shielding layer 15; in one example, the substrate is a glass substrate. In one example, the pixel electrode layer 13 is made of a transparent conductive material, for example, ITO (indium tin oxide), or TCO (glass oxide) and silver. The metal layer 11 and the pixel electrode layer 13 are positioned opposite each other; since both the metal layer 11 and the pixel electrode layer 13 are made of conductive materials, they together form a capacitor. It should be noted that the size of the capacitor is related to the distance and overlap area between the two electrodes of the capacitor, expressed by the formula C = f(S, d). The capacitive coupling is calculated according to the formula Q = C * V. That is, when the relevant TFT (Thin Film Transistor) on the driving substrate is turned off, Q and C are constant. However, when the voltage signal on the metal layer 11 changes, it will cause the voltage signal of the pixel electrode layer 13, which forms a capacitor with the metal layer 11, to change, thereby causing display abnormalities.

[0041] In one example, the display panel also includes gate scan lines (not shown) and a common electrode (not shown).

[0042] A shielding layer 15 is disposed between the pixel electrode layer 13 and the metal layer 11. Since the shielding layer 15 is made of a transparent conductive material, sandwiching it between the pixel electrode layer 13 and the metal layer 11 creates a capacitor between them. This transfers the influence of voltage signal changes on the metal layer 11 on the pixel electrode layer 13 to the shielding layer 15, preventing the voltage signal on the metal layer 11 from affecting the voltage signal on the pixel electrode layer 13. Thus, the shielding layer 15 shields the capacitive coupling between the metal layer 11 and the pixel electrode layer 13. In other words, the shielding layer 15, covering the metal layer 11, acts as a shielding electrode. The shielding layer 15 between the pixel electrode layer 13 and the metal layer 11 can shield the coupling effect of the voltage signal on the metal layer 11 on the voltage signal on the pixel electrode layer 13, thereby eliminating the capacitive coupling between the pixel electrode layer 13 and the metal layer 11. In one example, the shielding layer 15 is made of ITO (indium tin oxide) material, or of TCO (toluene oxide glass) material and silver metal. The shielding layer 15 can be a transparent conductive material; no specific limitation is made here. It should be noted that the shielding layer 15 is not in direct contact with the pixel electrode layer 13 and the metal layer 11. Other material layers of the display panel exist between the shielding layer 15 and the pixel electrode layer 13. Other material layers of the display panel also exist between the shielding layer 15 and the metal layer 11.

[0043] The dimensions of the shielding layer 15 can be set according to actual needs. In one example, the thickness of the shielding layer 15 is 600 to 800 angstroms. For example, the thickness of the shielding layer 15 is 650 angstroms, the thickness of the shielding layer 15 is 700 angstroms, and the thickness of the shielding layer 15 is 750 angstroms. The thickness of the shielding layer 15 listed here is for illustrative purposes only. The specific thickness is designed according to actual needs, and no specific limit is made to the thickness of the shielding layer 15 here.

[0044] In one example, a voltage signal is transmitted on the shielding layer 15. Inputting a voltage signal onto the shielding layer 15 eliminates the influence of voltage signal changes on the metal layer 11 on the shielding layer 15. When the shielding layer 15 receives a stable input voltage signal, any changes in the voltage signal on the metal layer 11 will instantly restore the coupling effect of that voltage signal on the shielding layer 15, thus preventing any change in the signal of the shielding layer 15 itself. In one example, a voltage signal is input to the shielding layer 15 via a voltage source, for example, a voltage source located on the control board of the liquid crystal display panel, or a voltage source located on the driving substrate.

[0045] Furthermore, to reduce the design complexity of the voltage signal transmitted on the shielding layer 15, in one example, the voltage signal transmitted on the shielding layer 15 is the same as the voltage signal transmitted on the metal layer 11. In implementation, two voltage sources can be used to transmit the same voltage signal to the shielding layer 15 and the metal layer 11 respectively, or the same voltage source can be used to transmit the same voltage signal to both the shielding layer 15 and the metal layer 11.

[0046] In one example, such as Figure 2 As shown, the metal layer 11 includes a plurality of spaced data lines 111. The pixel electrode layer 13 includes a plurality of spaced pixel electrodes 131. The shielding layer 15 shields the capacitive coupling between the data lines 111 and the pixel electrode layer 13. It should be noted that the data lines 111 are used to transmit data signals. Since the shielding layer 15 is made of a transparent conductive material, sandwiching the shielding layer 15 between the pixel electrode layer 13 and the data lines 111 creates a capacitor between the shielding layer 15 and the data lines 111. This transfers the influence of changes in the data signal on the data lines 111 on the pixel electrode layer 13 to the shielding layer 15, preventing the data signal on the data lines 111 from affecting the voltage signal on the pixel electrode layer 13. Therefore, the shielding layer 15 shields the capacitive coupling between the data lines 111 and the pixel electrode layer 13. In other words, the shielding layer 15 covers the data line 111 and exists as a shielding electrode. That is, the shielding layer 15 between the pixel electrode layer 13 and the data line 111 can shield the coupling effect of the data signal on the data line 111 to the voltage signal on the pixel electrode layer 13. Thus, the introduction of the shielding layer 15 can eliminate the capacitive coupling between the pixel electrode layer 13 and the data line 111.

[0047] In various embodiments of the display panel of this application, the display panel includes a substrate, a metal layer 11, a pixel electrode layer 13, and a shielding layer 15. In the display panel structure, the metal layer 11 is disposed on the substrate. The shielding layer 15 is disposed on the metal layer 11. The pixel electrode layer 13 is disposed on the side of the shielding layer 15 facing away from the metal layer. In a conventional display panel structure, the metal layer 11 and the pixel electrode layer 13 are disposed opposite each other, and there is another material layer between them. The metal layer 11 and the pixel electrode layer 13 form a capacitor. When the voltage signal of the metal layer 11 changes, the metal layer 11 will affect the voltage signal of the pixel electrode layer 13 through the capacitive coupling formed between them, thereby causing display abnormalities in the display panel. In this application, the shielding layer 15 is disposed between the metal layer 11 and the pixel electrode layer 13. The voltage signal change of the metal layer 11 will act on the shielding layer 15 and will not affect the pixel electrode layer 13. The shielding layer 15 shields the capacitive coupling between the metal layer 11 and the pixel electrode layer 13, thereby eliminating the capacitive coupling phenomenon, eliminating the display abnormality phenomenon of the display panel, and improving the quality of the display panel.

[0048] In traditional TFT-LCD liquid crystal displays, a-Si (amorphous silicon) devices are widely used due to their good stability. However, in large-size, high-resolution TFT-LCD liquid crystal displays, as the panel driving load increases, the requirements for charging time and charging rate also become more stringent. Therefore, the HG2D architecture is generally adopted to improve the panel charging rate. However, the increased number of data lines in the panel leads to a significant decrease in pixel aperture ratio, thereby reducing the panel's display brightness.

[0049] To address the issue of increased data lines in the aforementioned panel leading to a significant decrease in pixel aperture ratio and consequently reduced display brightness, this application provides a display panel comprising a substrate (not shown), a metal layer 11, a pixel electrode layer 13, and a shielding layer 15. The display panel includes N pixel units. These N pixel units are arranged in a matrix according to a certain rule, for example, in a square matrix arranged horizontally and vertically. Figure 3 As shown, the pixel electrode layer 13 includes a plurality of pixel electrodes 131 spaced apart, wherein each pixel electrode 131 includes a main stem 1311 and a branch 1313 connected to the main stem. Pixel units correspond one-to-one with pixel electrodes 131.

[0050] The metal layer 11 includes a plurality of spaced data lines 111, and a shielding layer 15 is disposed between the pixel electrode layer 13 and the data lines 111. The data lines 111 are used to transmit data signals. The shielding layer 15 shields the capacitive coupling between the data lines 111 and the pixel electrode layer 13. It should be noted that the shielding principle of the shielding layer 15 is the same as in the previous embodiment, and will not be repeated here. In one example, the display panel also includes a thin-film transistor 113. One of the source and drain terminals of the thin-film transistor 113 is connected to the metal layer 11, and the other of the source and drain terminals of the thin-film transistor 113 is connected to the pixel electrode 131.

[0051] Each pixel unit includes at least one data line 111 and one pixel electrode 131. Depending on the pixel size within the pixel unit, a larger pixel size allows for the use of more data lines 111 to ensure charging time and charging rate. For example, a pixel unit may include one data line 111, two data lines 111, three data lines 111, or more data lines 111.

[0052] There are two ways to arrange the data cable 111:

[0053] The first type: such as Figure 3 As shown, the orthographic projection of the data line 111 onto the plane containing the pixel electrode 131 at least covers a portion of the main stem 1311 of the pixel electrode 131. It should be noted that the data line 111 is arranged parallel to the main stem 1311 of the pixel electrode 131, and viewed from the inside of the liquid crystal display panel perpendicular to the display surface. The data line 111 and the main stem 1311 of the pixel electrode 131 at least partially overlap; in other words, the main stem 1311 of the pixel electrode 131 blocks part of the structure of the data line 111. Wherein, as... Figure 4 As shown, the main stem 1311 of the pixel electrode 131, also known as the "keel," is the supporting part of the pixel electrode 131 and does not emit light. When the data line 111 overlaps with the main stem 1311 of the pixel electrode 131, the occlusion effect of the data line 111 on the pixel is reduced, thereby increasing the pixel aperture ratio and improving the display brightness of the panel. For example, the orthographic projection of the data line 111 onto the plane where the pixel electrode 131 is located can cover one-third, one-half, two-thirds, or 100% of the main stem 1311 of the pixel electrode 131, depending on the actual situation, and no specific limitation is made here. Of course, 100% coverage has the greatest effect on improving the aperture ratio and display brightness.

[0054] The second type: such as Figure 3As shown, the orthographic projection of the data line 111 onto the plane containing the pixel electrode 131 lies in the non-aperture area 133 between two adjacent pixel units. It should be noted that the portion of the non-aperture area 133 between two adjacent pixel units is the non-aperture area 133. Since the non-aperture area 133 between pixel units does not emit light, overlapping the data line 111 with the non-aperture area 133 reduces the occlusion effect of the data line 111 on the pixels, thereby increasing the pixel aperture ratio and improving the display brightness of the panel. For example, the orthographic projection of the data line 111 onto the plane containing the pixel electrode 131 can cover one-quarter, one-half, three-quarters, or 100% of the non-aperture area 133 between two adjacent pixel units, depending on the actual situation, and is not specifically limited here. Of course, 100% coverage has the greatest effect on improving the aperture ratio and display brightness.

[0055] Regarding the two methods described above, it should be noted that the non-aperture area 133 between two adjacent pixel units and the main stem 1311 of the pixel electrode 131 are parallel to the data line 111. In one example, the main stem 1311 of the pixel electrode 131 is arranged vertically. The non-aperture area 133 between two adjacent pixel units is also arranged vertically.

[0056] When a pixel unit includes two data lines 111, that is, a first data line 111A and a second data line 111B, the first data line 111A and the second data line 111B are arranged parallel and spaced apart. The orthographic projection of the first data line 111A onto the plane containing the pixel electrode 131 at least covers a portion of the main branch 1311 of the pixel electrode 131. The orthographic projection of the second data line 111B onto the plane containing the gate scan line is located between two adjacent pixel units. That is, of the two data lines 111 in the pixel unit, one data line 111 is parallel to and overlaps with the main branch 1311 of the pixel electrode 131, and one data line 111 is located in the non-opening region 133 of two adjacent pixel units.

[0057] In conventional technology, due to the shielding layer 15 of this application, in order to eliminate the capacitive coupling caused by the data signal on the data line 111, the two data lines 111 must be designed symmetrically to achieve left-right cancellation of capacitive coupling; otherwise, display abnormalities will occur. In this design, both data lines 111 block the light-emitting part of the pixel, so the opening space occupied is relatively large. However, after adding the shielding layer 15 in this application, the data lines 111 can be designed asymmetrically. Therefore, the data lines 111 can be placed between pixels that are not used as display areas (i.e., at the position of the gate scan line) and below the main trunk 1311 of the pixel electrode 131, which greatly improves the aperture ratio.

[0058] In the example where a pixel unit includes two data lines 111, there are at least three ways in which adjacent pixel units can be connected to each other:

[0059] The first method: such as Figure 5 As shown, N pixel units are arranged in a matrix horizontally and vertically. In the same column, the first data line 111A of adjacent pixel units is connected, and the second data line 111B is connected. It should be noted that, vertically, the first data line 111A is located on the same side of the pixel unit, and the second data line 111B is located on the other side of the pixel unit. That is, vertically, the data lines 111 on the same side of the pixel unit are connected. It should also be noted that the data line 111 corresponding to the non-opening area 133 of adjacent pixel units is the first data line 111A, and the data line 111 corresponding to the main trunk 1311 of the pixel electrode layer 13 is the second data line 111B.

[0060] The second method: such as Figure 6 As shown, N pixel units are arranged in a matrix horizontally and vertically. The first data line 111A of a pixel unit in a column is connected to the second data line 111B of another pixel unit adjacent to it in the same column. The second data line 111B of a pixel unit in a column is connected to the first data line 111A of another pixel unit in an adjacent column and adjacent horizontal column. It should be noted that the data line 111 in the non-aperture area 133 corresponding to the adjacent pixel unit is the first data line 111A, and the data line 111 in the main trunk 1311 of the pixel electrode layer 13 is the second data line 111B.

[0061] In this method, the data lines 111 of the pixel units are alternately connected. Taking pixel units 1 and 2 in the first column and pixel units 3 and 4 in the second column as an example, with pixel units 1 and 3 located in the first row and pixel units 2 and 4 located in the second row: the first data line 111A of pixel unit 1 is connected to the second data line 111B of pixel unit 2, and the second data line 111B of pixel unit 1 is connected to the first data line 111A of pixel unit 4. The first data line 111A of pixel unit 3 is connected to the second data line 111B of pixel unit 4, and so on, alternately connected.

[0062] The third method: such as Figure 7As shown, N pixel units are arranged in a matrix horizontally and vertically. In some pixel units, the first data line 111A of one pixel unit is connected to the first data line 111A of another adjacent pixel unit located in the same column, and the second data line 111B of one pixel unit is connected to the second data line 111B of another adjacent pixel unit located in the same column; in other pixel units, the first data line 111A of one pixel unit is connected to the second data line 111B of another adjacent pixel unit located in the same column; and the second data line 111B of one pixel unit is connected to the first data line 111A of another pixel unit located in an adjacent column and adjacent horizontal column.

[0063] It should be noted that, vertically, the first data line 111A is located on the same side of the pixel unit, and the second data line 111B is located on the other side of the pixel unit. It should also be noted that the data line 111 corresponding to the non-opening area 133 of the adjacent pixel unit is the first data line 111A, and the data line 111 corresponding to the main trunk 1311 of the pixel electrode layer 13 is the second data line 111B.

[0064] In this method, the data lines 111 of some pixel units are directly connected in the same column, while the data lines 111 of some pixel units are interleaved.

[0065] Taking pixel units 1, 2, 3, and 4 in the first column, and pixel units 5, 6, 7, and 8 in the first column, with pixel units 1 and 5 located in the first row, pixel units 2 and 6 in the second row, pixel units 3 and 7 in the third row, and pixel units 4 and 8 in the fourth row as an example: The first data line 111A of pixel unit 1 is connected to the second data line 111B of pixel unit 2, and the second data line 111B of pixel unit 1 is connected to the first data line 111A of pixel unit 6. The first data line 111A of pixel unit 2 is connected to the second data line 111B of pixel unit 3, and the second data line 111B of pixel unit 2 is connected to the first data line 111A of pixel unit 7. The first data line 111A of pixel unit 3 is connected to the first data line 111A of pixel unit 4, and the second data line 111B of pixel unit 3 is connected to the second data line 111B of pixel unit 4. The first data line 111A of pixel unit 5 is connected to the second data line 111B of pixel unit 6. The first data line 111A of pixel unit 6 is connected to the second data line 111B of pixel unit 7. The first data line 111A of pixel unit 7 is connected to the first data line 111A of pixel unit 8, and the second data line 111B of pixel unit 7 is connected to the second data line 111B of pixel unit 8, and so on. It should be noted that the connection method of pixel units 1-8 is only for illustrative purposes. There are many combinations of this third method, which cannot be exhaustively listed here.

[0066] In the liquid crystal display panel of this application, the addition of a shielding layer 15 eliminates the capacitive coupling between the metal layer 11 and the pixel electrode layer 13, so that the data lines 111 do not need to be symmetrically arranged as in conventional technology. Therefore, the data lines 111 of this application can be arranged in any position. In this application, the data lines 111 are arranged below the main trunk 1311 of the pixel electrode layer 13 and the gate scan line to avoid the data lines 111 occupying the pixel opening, thereby increasing the pixel aperture ratio and improving the brightness of the liquid crystal display panel.

[0067] In one example, a display device is provided, including a display panel.

[0068] It should be noted that the display panel in this embodiment is the same as the display panel described in the various embodiments of the display panel in this application, and will not be described again here.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Substrate; A metal layer is disposed on the substrate; A shielding layer is disposed on the metal layer and is provided insulated from the metal layer at a distance; as well as A pixel electrode layer is disposed on the side of the shielding layer opposite to the metal layer and is insulated from the shielding layer by a distance; The display panel includes N pixel units; the N pixel units are arranged in a matrix in a horizontal and vertical direction; the metal layer includes a plurality of spaced data lines; the pixel electrode layer includes a plurality of spaced pixel electrodes; each pixel electrode includes a main stem and a branch connected to the main stem; the shielding layer shields the capacitive coupling between the data lines and the pixel electrodes. Each pixel unit includes a first data line, a second data line, and at least one pixel electrode. The first data line and the second data line are arranged in parallel and spaced apart. The orthographic projection of the first data line onto the plane where the pixel electrode is located covers at least a portion of the main body of the pixel electrode. The orthographic projection of the second data line onto the plane where the pixel electrode is located is located between two adjacent pixel units. In this configuration, the first data line of one pixel unit in a column is connected to the second data line of another pixel unit adjacent to it in the same column; the second data line of the pixel unit is connected to the first data line of another pixel unit in an adjacent column and an adjacent row.

2. The display panel according to claim 1, characterized in that, The display panel also includes a thin-film transistor, one of the source and drain of the thin-film transistor being connected to the metal layer, and the other of the source and drain of the thin-film transistor being connected to the pixel electrode layer.

3. A display panel, characterized in that, include: Substrate; A metal layer is disposed on the substrate; A shielding layer is disposed on the metal layer and is provided insulated from the metal layer at a distance; as well as A pixel electrode layer is disposed on the side of the shielding layer opposite to the metal layer and is insulated from the shielding layer by a distance; The display panel includes N pixel units; the N pixel units are arranged in a matrix in a horizontal and vertical direction; the metal layer includes a plurality of spaced data lines; the pixel electrode layer includes a plurality of spaced pixel electrodes; each pixel electrode includes a main stem and a branch connected to the main stem; the shielding layer shields the capacitive coupling between the data lines and the pixel electrodes. Each pixel unit includes a first data line, a second data line, and at least one pixel electrode. The first data line and the second data line are arranged in parallel and spaced apart. The orthographic projection of the first data line onto the plane where the pixel electrode is located covers at least a portion of the main body of the pixel electrode. The orthographic projection of the second data line onto the plane where the pixel electrode is located is located between two adjacent pixel units. In some of the pixel units, the first data line of one pixel unit is connected to the first data line of another adjacent pixel unit located in the same column, and the second data line of one pixel unit is connected to the second data line of an adjacent pixel unit located in the same column. In another portion of the pixel units, the first data line of one pixel unit is connected to the second data line of another adjacent pixel unit located in the same column; the second data line of the one pixel unit is connected to the first data line of another pixel unit located in an adjacent column and adjacent row.

4. The display panel according to claim 3, characterized in that, The display panel also includes a thin-film transistor, one of the source and drain of the thin-film transistor being connected to the metal layer, and the other of the source and drain of the thin-film transistor being connected to the pixel electrode layer.

5. A display device, characterized in that, It includes the display panel as described in claim 1 or 2, or the display panel as described in claim 3 or 4.

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