Design method, system, device and terminal for instruction prediction processor circuit stress

Abstract

The application belongs to the technical field of processor aging prediction, and discloses a design method, system, device and terminal for predicting the pressure of an instruction processor circuit, wherein an instruction machine code in an instruction cache is sent into a replication circuit by replicating an instruction decoding circuit in the processor; after decoding by the replication circuit, a counter is used to measure the decoded signal to obtain an SP value of an operation circuit and determine the SP influence of the instruction on the operation circuit. The application uses an easily monitored instruction machine code to represent an SP value which is difficult to measure, thereby reducing the monitoring difficulty of the SP and reducing the invasion of the processor core circuit. The design method for predicting the SP of the instruction based on the replication circuit converts the difficult-to-measure SP into the easily obtained instruction machine code, thereby providing a certain basis for the research on the aging degree of the model prediction processor. The application has low invasiveness, does not affect the critical path of the CPU operation circuit, and has little overall impact on the CPU timing.

Description

Technical Field

[0001] The present invention belongs to the technical field of processor aging prediction, and in particular relates to a design method, system, device and terminal for predicting processor circuit pressure through instructions. Background Art

[0002] Currently, among the factors that affect processor circuit aging, the signal probability (SP) of key signals is difficult to measure directly, but is closely related to circuit stress.

[0003] As SoC chips become increasingly complex, the complex semiconductor processes used in circuit manufacturing inevitably introduce process variations. Furthermore, some specialized SoCs operate in harsh environments, accelerating SoC aging. Therefore, detecting and predicting SoC aging becomes crucial. The processor is the core component of the SoC and bears the heaviest workload within the SoC's internal structure, making aging prediction and mitigation crucial.

[0004] Three effects contribute to transistor aging: hot carrier injection (HCI), negative bias temperature instability (NBTI), and time-dependent dielectric breakdown (TDDB). Research has shown that NBTI and HCI have the greatest impact on processor aging. With advancements in process technology, NBTI has become increasingly dominant among aging effects. The NBTI effect is closely related to the semiconductor process element (SP).

[0005] Processor aging prediction methods can generally be categorized into three types: failure prediction based on aging characterization circuits, failure prediction based on failure symptom monitoring, and model-based failure prediction. The first two methods suffer from significant drawbacks, presenting a conflict between accuracy and invasiveness in aging detection: methods with high accuracy are too invasive to the circuit itself, impacting performance; whereas less invasive methods offer low prediction accuracy and reliability. Therefore, the current mainstream aging prediction method uses data-based training of aging models for aging estimation.

[0006] Lifetime loss models are based on mainstream model prediction methods. Most lifetime loss models employ machine learning. To build accurate machine learning models, it is necessary to comprehensively consider various aging factors and determine multi-dimensional model inputs. To fully account for the impact of both NBTI and HCI, machine learning models can use voltage, temperature, switch-activity (SA), and signal processing (SP) as inputs. Among these environmental parameters, SP is difficult to monitor directly. Directly measuring SP in processor circuits requires inserting detectors or detection circuits within the processor, which is highly invasive and has a significant impact on processor performance. Existing solutions use simulation methods for model prediction, allowing model training using SP values ​​generated in the simulator. However, due to process variations and environmental factors during actual chip use, simulated models are not accurate enough and cannot be tailored to specific chips. In aging tests using actual chips, SP is a manual input and cannot reflect the variable SP values ​​during chip use.

[0007] In order to solve the problem that SP is difficult to measure, it is urgent to design a new design method for instruction prediction processor circuit pressure.

[0008] Through the above analysis, the problems and defects of the existing technology are as follows:

[0009] (1) Existing methods for predicting processor aging have a contradiction between accuracy and intrusiveness in aging detection. Detection methods with high accuracy are too intrusive to the circuit, affecting the performance of the circuit itself; while detection methods with low intrusiveness have low prediction accuracy and reliability.

[0010] (2) Among the environmental parameters used by existing machine learning models, SP is difficult to monitor directly. Directly detecting SP in the processor circuit requires inserting a detector or detection circuit inside the processor, which is highly invasive and has a significant impact on the performance of the processor.

[0011] (3) The machine learning model trained using simulation cannot accurately predict the degree of chip aging during actual use; in experiments using actual chips, SP is artificially added and cannot reflect the variable SP value during actual operation. Summary of the Invention

[0012] In response to the problems existing in the prior art, the present invention provides a design method, system, device and terminal for instruction prediction processor circuit pressure, and in particular, relates to a design method, system, medium, device and terminal for instruction prediction SP based on replica circuit.

[0013] The present invention is implemented as follows: a design method for an instruction prediction processor circuit pressure, the design method comprising: obtaining instruction machine code by bypassing the output of the instruction cache, inputting the instruction machine code into a FIFO module, and then sending the instruction machine code in the FIFO into the copy circuit through the instruction decoding circuit in the copy processor; after decoding by the copy circuit, measuring the decoded signal through a counter to obtain the SP value of the operation circuit, and determining the SP impact of the instruction on the operation circuit.

[0014] Furthermore, the design method for predicting processor circuit pressure by instructions includes the following steps:

[0015] Step 1: Use the FIFO module to temporarily store the instruction machine code in the instruction cache. This step is primarily used to address potential cross-clock domain transmission issues. When the clocks of the subsequent SP calculation module and decoding circuit module differ from the clock of the processor circuit under test, an asynchronous FIFO can be used to handle cross-clock domain data transmission.

[0016] Step 2: Using the decoding circuit module, the instruction machine code is decoded and input into the arithmetic circuit workload. This step is used to decode the instruction machine code into the input signal of the arithmetic circuit, facilitating direct calculation of the workload. The main purpose of this step is to represent the easily measurable instruction machine code as the input signal of the arithmetic circuit, which is not easily measurable.

[0017] Step three: Use the SP calculation circuit to convert the decoded workload into a specific SP value. This step uses a counter to convert the workload of the processor arithmetic circuit into a specific SP value. This step can also be used independently, inserted directly after the dispatch module of the processor circuit under test and before the processor arithmetic circuit, to directly calculate the SP value. However, this will be too invasive.

[0018] Furthermore, the design method for predicting processor circuit pressure through instructions also includes:

[0019] The instruction prediction SP module obtains the instruction by bypassing the instruction cache of the CPU, and the obtained machine code is sent to the FIFO for temporary storage. The copy circuit module needs to be connected to the storage circuit of the CPU to obtain the data value stored in the storage module; the SP calculation module performs periodic refresh to obtain the real-time SP value; when the SP integral value is obtained, the signal is bypassed from the positive and negative counters respectively, and the total number of cycles of 1 and 0 obtained is stored and then input into the divider to calculate the integral value of SP.

[0020] Another object of the present invention is to provide an instruction prediction processor circuit pressure design system that applies the instruction prediction processor circuit pressure design method, and the instruction prediction processor circuit pressure design system includes: a FIFO module, a decoding circuit module and an SP calculation module.

[0021] The input end of the FIFO module is fed by the instruction cache of the CPU, and the output end is fed into the copy circuit, which is responsible for temporarily storing the instruction machine code in the instruction cache;

[0022] The decoding circuit module is a replica circuit of the instruction decoding circuit in the processor, and is used to decode the machine code of the instruction into a workload input to the operation circuit;

[0023] The SP calculation module is used to convert the decoded workload into a specific SP value.

[0024] Furthermore, the FIFO module is used to solve the problem of data transmission across clock domains. The clock frequency of the CPU and the instruction prediction SP module are different, requiring asynchronous FIFO processing. The instruction decoder is a replica of the CPU's decoding stage circuit, and the replica circuit architecture varies depending on the CPU architecture.

[0025] Furthermore, the decoding circuit module includes an instruction decoding part, a register group part and a transmitting part; the three parts are completely replica structures of the extracted CPU and are used to decode the extracted instruction machine code.

[0026] The instructions include arithmetic instructions, memory access instructions and branch instructions. The arithmetic instructions include ADD and SUB, the memory access instructions include STR and LDR, and the branch instructions include BLT and BGT.

[0027] The instruction decoding part is used to distinguish the type of instruction and perform different processing on different types of instructions; when the instruction is an arithmetic instruction, it distinguishes what kind of arithmetic operation the arithmetic instruction is, and when the instruction is a branch instruction, it determines the condition of the branch instruction; when the instruction is a memory access instruction, it distinguishes whether it is a load instruction or a store instruction; using the instruction decoding part, the source operand and destination operand in the instruction and whether there is an immediate number in the instruction are separated; for the register group part, the register group that is the same as the original CPU is copied to the storage state of the register group in the CPU; the emission part is the last step before the CPU executes the instruction, and the emission process is the process of sending the instructions in the emission queue to the next stage.

[0028] Furthermore, the SP calculation module is based on a calculator and consists of three parts: a positive counter, a negative counter and a divider; wherein the positive counter and the negative counter are used to calculate the number of cycles of 1 and 0 respectively, and the divider is used to divide the calculation results of the positive counter and the negative counter to obtain the final SP value and output it.

[0029] Another object of the present application is to provide a computer device comprising a memory and a processor, the memory storing a computer program, the computer program being executed by the processor to cause the processor to perform the steps of the design method for predicting the stress of a processor circuit.

[0030] Another object of the present application is to provide a computer-readable storage medium storing a computer program, the computer program being executed by a processor to cause the processor to perform the steps of the design method for predicting the stress of a processor circuit.

[0031] Another object of the present application is to provide an information data processing terminal for implementing the design system for predicting the stress of a processor circuit.

[0032] In combination with the above technical solutions and the technical problems solved, the technical solution of the present application has the following advantages and positive effects:

[0033] In order to solve the problem that the SP is difficult to measure, the present application proposes a method for characterizing the SP of an operation circuit by copying the circuit. The method obtains the machine code of an instruction from an instruction cache, then obtains the workload of an input operation circuit by copying the circuit, and then measures the SP by using a counter.

[0034] The present application proposes a design method for predicting the SP by using instruction machine code. The method copies the instruction decoding circuit in the processor, sends the instruction machine code in the instruction cache into the copied circuit, decodes the copied circuit, then measures the decoded signal by using a counter to obtain the SP value of the operation circuit, and finally obtains the influence of the instruction on the SP of the operation circuit.

[0035] The design method for predicting the SP based on the copied circuit has the following advantages: 1) the SP which is difficult to measure is converted into the instruction machine code which is easy to obtain, thereby providing a basis for the research on the aging degree of the processor based on the model; and 2) the method has low invasiveness, does not affect the critical path of the CPU operation circuit, and has little influence on the overall CPU timing.

[0036] The design method for predicting SP using instructions, provided by the present invention, uses easily monitored instruction machine code to characterize the difficult-to-measure SP value, reducing the difficulty of SP monitoring and minimizing intrusion into the processor's core circuitry. By obtaining the instruction machine code from the instruction cache and subsequently converting it into the SP value of the arithmetic circuit, the present invention avoids inserting sensors or monitoring circuits into the timing-constrained arithmetic circuit, which can lead to processor timing constraints and performance degradation. Furthermore, the SP value provided is a real-time, accurate SP value for the CPU, rather than an estimated, statistical SP value. This accurate SP value can be used in subsequent model training to derive processor aging information.

[0037] The technical solution of the present invention fills a technological gap in the industry at home and abroad: the current mainstream method used for processor aging prediction is model-based prediction. Model prediction requires various parameters of the processor, including easily obtainable temperature, voltage, etc. and less easily obtainable SP, SA, etc. The current common method for obtaining SP is to directly capture the SP inside the processor through simulation. However, in actual use, the model obtained by simulation does not take into account the environmental factors of the chip under actual conditions and the process deviations between each chip; the SP value obtained through simulation analysis is not real-time and accurate enough, and the SP measured by sensor methods has a greater impact on the performance of the processor. This patent reduces the intrusiveness by replicating the circuit method, and obtains real-time and accurate SP values ​​with almost no impact on the processor performance.

[0038] Does the technical solution of this invention solve a long-cherished but unsuccessful technical problem: the difficulty in obtaining the processor's real-time SP value when using models to predict processor aging? The SP value obtained through simulation is not accurate enough, branch prediction is difficult, and obtaining a real-time SP value is difficult. This invention solves this problem by replicating the circuit, directly decoding the instruction machine code to obtain the processor's SP value, providing technical support for future processor aging prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a flow chart of a design method for predicting processor circuit pressure through instructions provided by an embodiment of the present invention;

[0041] Figure 2 This is a structural diagram of a design system for instruction prediction processor circuit pressure provided by an embodiment of the present invention;

[0042] Figure 3 1 is a structural diagram of an SP calculation circuit provided by an embodiment of the present invention;

[0043] Figure 4 Schematic diagram of the location of the instruction prediction SP module provided by an embodiment of the present invention;

[0044] Figure 5 This is a connection diagram between the instruction prediction SP module and the CPU provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] In response to the problems existing in the prior art, the present invention provides a design method, system, device and terminal for instruction prediction processor circuit pressure. The present invention is described in detail below with reference to the accompanying drawings.

[0047] In order to enable those skilled in the art to fully understand how to implement the present invention, this section provides an explanatory embodiment that expands on the technical solutions of the claims.

[0048] like Figure 1 As shown, the design method for instruction prediction processor circuit pressure provided by the embodiment of the present invention includes the following steps:

[0049] S101, using the FIFO module to temporarily store the instruction machine code in the instruction cache;

[0050] S102, using a decoding circuit module to decode the machine code of the instruction and input it into the computing circuit workload;

[0051] S103 , using an SP calculation circuit to convert the decoded workload into a specific SP value.

[0052] like Figure 2 As shown, the instruction prediction processor circuit stress design system provided by the embodiment of the present invention is mainly composed of three parts: a FIFO module, a decoding circuit module, and an SP calculation module. The FIFO module is responsible for temporarily storing the instruction machine code in the instruction cache; the decoding circuit module is a replica of the instruction decoding circuit in the processor, which is used to decode the instruction machine code into the workload input to the arithmetic circuit; and the SP calculation circuit is used to convert the decoded workload into a specific SP value.

[0053] The FIFO module provided in embodiments of the present invention is used to address cross-clock domain data transmission issues. The CPU clock frequency differs from the instruction prediction SP module clock frequency, necessitating an asynchronous FIFO for processing. The instruction decoder is a replica of the CPU's decoding circuitry. The replica circuit architecture varies depending on the CPU architecture. The replica circuit comprises the following components: an instruction decoding section, a register set, and an emit section. Instructions can be divided into three categories: arithmetic instructions (such as ADD and SUB), memory access instructions (such as STR and LDR), and branch instructions (such as BLT and BGT). The instruction decoding section must distinguish instruction types and process them differently. For arithmetic instructions, it must determine the type of arithmetic operation. For branch instructions, it must determine the branch condition. For memory access instructions, it must determine whether the instruction is a load or store instruction. The instruction decoding section then needs to separate the source and destination operands in the instruction, as well as whether the instruction contains immediate operands. The register set must be identical to the original CPU's, replicating the CPU's register set's storage state. The launch part is the last step before the CPU executes instructions. The launch process is the process of sending the instructions in the launch queue to the next stage.

[0054] The SP calculation part provided by the embodiment of the present invention is mainly implemented based on a calculator, such as Figure 3 As shown in Figure 2, the instruction decoder module converts the instruction into a workload and transmits it to the SP calculation module. The positive counter (P-Counter) counts the number of cycles occupied by 1s, while the negative counter (N-Counter) counts the number of cycles occupied by 0s. The calculated values ​​are then fed into the divider, whose output serves as the SP output.

[0055] Figure 4 The embodiment of the present invention provides a classic five-stage pipeline processor architecture, which bypasses data from the instruction cache between the instruction fetch (IF) stage and the instruction decode (DE) stage in the processor to the instruction prediction SP module implemented by the present invention.

[0056] The connection mode between the present invention and the CPU is as follows Figure 5As shown in the figure, in typical RISC processors, the I-CACHE is not written directly to, but rather uses the D-CACHE. When writing an instruction, the instruction's machine code is written to the D-CACHE. The D-CACHE then writes the instruction as data to the lower-level cache (L2 cache) and invalidates the instruction in the I-CACHE. Since the I-CACHE and D-CACHE share the L2 cache, the I-CACHE can also read data from the L2 cache as instructions. Based on the PC value, the I-CACHE then transfers the instruction's machine code to the instruction buffer. After the instruction buffer, a signal is bypassed to the FIFO module. Memory access instructions require access to the CPU's memory space, so the copy circuitry also needs to access the CPU's memory to obtain the data stored at the corresponding address. In practical implementation, the counter needs to be refreshed periodically to obtain the real-time SP value. When the SP integral is required, signals are bypassed from the positive and negative counters, respectively. The values ​​are then added and fed into the divider for SP calculation.

[0057] In order to prove the creativity and technical value of the technical solution of the present invention, this section provides application examples of the claimed technical solution on specific products or related technologies.

[0058] The present invention can perform stress estimation on the computing circuit of the Hummingbird E203 processor. The Hummingbird E203 has a two-stage pipeline architecture. The first stage of the pipeline is the instruction fetch stage. According to the PC's instruction, the instruction is fetched from the ITCM (Instruction Tightly Coupled Memory) and placed in the IR register. The second stage of the pipeline includes multiple stages such as decoding, execution, and write-back. The present invention mainly focuses on the process of sending the IFU (Instruction Fetch Unit) to the execution stage through the IR register. In the Hummingbird E203, the IR register is the instruction cache part in the present invention, and the machine code of the instruction is temporarily stored in the IR register.

[0059] In order to prove the low intrusiveness of the present invention, the implementation process is divided into three parts. In the first part, the EDA tool is used to synthesize the Hummingbird E203 to obtain the maximum frequency of the Hummingbird E203. The second part directly bypasses the output of the IR register and connects it to the input of the FIFO module of the present invention. Then, the EDA tool is used for synthesis to check the intrusiveness to the entire CPU. In the third part, the SP counting module of the present invention is directly connected to the dispatch module of the Hummingbird E203, and the SP of the operation circuit is directly measured inside the processor. Afterwards, the EDA tool is also used for synthesis, and the experimental results are compared with those of the first part of the experiment to analyze the degree of intrusiveness of the two. By observing the timing reports of the two, the impact on the processor timing is obtained to measure the degree of intrusiveness.

[0060] This experiment was synthesized using SMIC's 110nm process library. In the second part of the experiment, adding the present invention's CPU circuit had little impact on timing, maintaining the same maximum frequency as in the first part, but with increased load and area. In the third part of the experiment, inserting the present invention's SP calculation module directly after the CPU's dispatch module resulted in significant CPU timing compression and a 20% drop in maximum frequency, resulting in significant intrusion.

[0061] Directly inserting the SP calculation circuit into the arithmetic circuit with the most stringent timing in the CPU will change the critical path in the arithmetic circuit and increase the input load of the circuit, thereby reducing the maximum frequency of the entire CPU and affecting the performance of the CPU; while the instruction machine code bypassed through the instruction cache is not in the core circuit of the CPU, is less invasive, and has less impact on CPU performance.

[0062] The experimental results show that the present invention has low intrusion to the CPU, and at the same time proves the necessity of low intrusion: too high intrusion will affect the maximum frequency of the processor circuit, causing timing tension and performance degradation.

[0063] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware portion can be implemented using dedicated logic; the software portion can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. Those skilled in the art will appreciate that the above-mentioned devices and methods can be implemented using computer-executable instructions and / or contained in processor control code, for example, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, or can be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0064] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A design method for instruction prediction processor circuit pressure, characterized in that: The instruction machine code is obtained by bypassing the output of the instruction cache and input into the FIFO module. Then the instruction decoding circuit in the processor is copied and the instruction machine code in the FIFO is sent to the copied instruction decoding circuit. After decoding by the replica circuit, the decoded signal is measured by a counter to obtain the SP value of the operation circuit and determine the impact of the instruction on the SP of the operation circuit.

2. The method for designing instruction prediction processor circuit pressure according to claim 1, wherein: The design method for predicting processor circuit pressure through instructions comprises the following steps: Step 1: Use the FIFO module to temporarily store the instruction machine code in the instruction cache; Step 2: using a decoding circuit module to decode the machine code of the instruction and input it into the computing circuit workload; Step 3: Use the SP calculation circuit to convert the decoded workload into a specific SP value.

3. The design method for reducing circuit pressure of an instruction prediction processor according to claim 1, wherein: The design method for predicting the circuit pressure of the instruction prediction processor further includes: The instruction prediction SP module obtains the instruction by bypassing the instruction cache of the CPU, and the obtained machine code is sent to the FIFO for temporary storage. The copy circuit module needs to be connected to the storage circuit of the CPU to obtain the data value stored in the storage module; the SP calculation module performs periodic refresh to obtain the real-time SP value; when the SP integral value is obtained, the signal is bypassed from the positive and negative counters respectively, and the total number of cycles of 1 and 0 obtained is stored and then input into the divider to calculate the integral value of SP.

4. A system for designing instruction prediction processor circuit pressure using the method for designing instruction prediction processor circuit pressure according to any one of claims 1 to 3, characterized in that: The design system for instruction prediction processor circuit pressure includes: a FIFO module, a decoding circuit module and an SP calculation module; The instruction cache of the CPU is fed into the input end of the FIFO module, and the output end feeds the instruction machine code into the copy circuit, which is responsible for temporarily storing the instruction machine code in the instruction cache. The decoding circuit module is a replica circuit of the instruction decoding circuit, and is used to decode the machine code of the instruction into a workload input to the operation circuit; The SP calculation module is used to convert the decoded workload into a specific SP value.

5. The design system for predicting processor circuit pressure according to claim 4, wherein: The FIFO module is used to solve the problem of data transmission across clock domains; the clock frequency in the CPU is different from the clock frequency of the instruction prediction SP module, and an asynchronous FIFO is required for processing; the instruction decoder is a replica circuit of the CPU decoding stage circuit, and the replica circuit architecture is different depending on the CPU architecture.

6. The system for designing instruction prediction processor circuit pressure according to claim 4, wherein: The decoding circuit module includes an instruction decoding part, a register group part and a transmitting part; the three parts are completely replica structures of the extracted CPU and are used to decode the extracted instruction machine code; The instructions include arithmetic instructions, memory access instructions and branch instructions, the arithmetic instructions include ADD and SUB, the memory access instructions include STR and LDR, and the branch instructions include BLT and BGT; The instruction decoding part is used to distinguish the type of instruction and perform different processing on different types of instructions; when the instruction is an arithmetic instruction, it distinguishes what kind of arithmetic operation the arithmetic instruction is, and when the instruction is a branch instruction, it determines the condition of the branch instruction; when the instruction is a memory access instruction, it distinguishes whether it is a load instruction or a store instruction; using the instruction decoding part, the source operand and destination operand in the instruction and whether there is an immediate number in the instruction are separated; for the register group part, the register group that is the same as the original CPU is copied to the storage state of the register group in the CPU; the emission part is the last step before the CPU executes the instruction, and the emission process is the process of sending the instructions in the emission queue to the next stage.

7. The system for designing instruction prediction processor circuit pressure according to claim 4, wherein: The SP calculation module is based on a calculator and consists of three parts: a positive counter, a negative counter, and a divider. The positive counter and the negative counter are used to calculate the number of cycles of 1 and 0, respectively. The divider is used to divide the calculation results of the positive counter and the negative counter to obtain the final SP value and output it.

8. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the design method for instruction prediction processor circuit pressure according to any one of claims 1 to 3.

9. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the design method for predicting processor circuit stress by instructions according to any one of claims 1 to 3.

10. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the design system for instruction prediction processor circuit pressure as described in any one of claims 4 to 7.

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