A method and system for implementing fast operation of peripherals through a streaming device interface

Abstract

The application discloses a kind of method and system for realizing the high efficiency and fast operation of peripheral equipment by stream device interface, comprising: CPU and FPGA cooperation, various peripheral IO signal access FPGA, FPGA will input IO signal information buffer to cache area, CPU obtains the information in the cache area by stream device interface timing refresh, realizes the timing of input signal and sends up;At the same time, CPU will need to output information buffer and output to FPGA by stream device interface timing refresh, and FPGA will receive the information output to peripheral equipment again.The CPU of the application expands IO peripheral interface by stream device interface in the form of timing refresh, solves the problem that stream device interface cannot refresh peripheral IO flexibly, and further improves the adaptability of domestic CPU.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of embedded systems, and relates to a method and system for realizing efficient and rapid operation of peripherals through a stream device interface. BACKGROUND

[0002] Generally, as shown in the figure, in a real-time embedded system formed by a CPU combined with an FPGA architecture, the CPU will adopt a way of reading and writing internal registers of the FPGA through a parallel bus interface in order to flexibly and timely control IO extended by the FPGA, so that the peripherals can be directly mapped to a memory address space, and bus operation is equivalent to atomic operation, which is fast and reliable. Figure 1

[0003] However, at present, it is difficult to select a parallel bus interface supported embedded processor with strong processing capability and appropriate power consumption produced in China, and only the stream device interface such as SDIO / SPI can be used to realize IO peripheral operation. Figure 2 As shown in the figure, if the original way of operating IO peripherals one by one in real time is still maintained, CPU resources will be severely consumed because a large amount of communication overhead is required for each operation of peripheral IO, and there is a risk of operation failure or even misoperation due to the long operation time of the stream device peripheral interface such as SDIO / SPI and the risk of being interrupted by other CPU tasks.

[0004] In view of the above situation, the domestic CPU urgently needs to solve the problem that the stream device interface cannot flexibly refresh peripheral IO. SUMMARY

[0005] In order to solve the problems in the prior art, the present application provides a method and system for realizing efficient and rapid operation of peripherals through a stream device interface, which no longer operates individual peripheral IO in real time, but instead uniformly and timely refreshes all actual peripherals, that is, Figure 4 the rightmost content, fully utilizes the DMA and stream device interface peripherals of the CPU, and liberates the CPU, so as to improve the IO refresh efficiency and flexibility under the condition that the CPU only supports the stream device interface such as SDIO / SPI in the localization protection.

[0006] In order to achieve the above-mentioned target, the present application adopts the following technical scheme:

[0007] A method for realizing efficient and rapid operation of peripherals through a stream device interface, a CPU and an FPGA cooperate, various peripheral IO signals are connected to the FPGA, the FPGA caches the input IO signal information to a cache area, the CPU timely refreshes and acquires the information in the cache area through the stream device interface, and realizes the timely uploading of the input signal;

[0008] ​Meanwhile, the CPU buffers the information to be output and outputs the information to the FPGA in a timing refresh manner through the stream device interface, and the FPGA outputs the received information to the external device.

[0009] The application further comprises the following preferred schemes:

[0010] Preferably, the method comprises the following steps:

[0011] Step 1: the CPU controls the FPGA to generate a timing signal;

[0012] Step 2: the FPGA latches the input IO signal information to the buffer area at the rising edge of the timing signal;

[0013] Step 3: the CPU initiates a DMA transfer from the stream device interface to the memory in a timing interrupt, and the stream device cooperates with the DMA controller to complete the data transfer according to the configuration;

[0014] Step 4: after the CPU detects the transfer completion signal, the CPU checks the IO image data in the memory according to the need, and completes the input of the IO signal, i.e. realizes the timing uploading of the input signal;

[0015] Step 5: the CPU also writes the data to be output into the sending buffer area allocated in the memory in the timing interrupt, and then initiates a DMA transfer from the memory to the stream device interface.

[0016] Preferably, the timing period of the timing signal is set according to the frequency of the IO signal to be refreshed in the application.

[0017] Preferably, the information comprises switch input, received data frame of longitudinal differential protection, and ADC sampling data.

[0018] Preferably, the buffer area in the FPGA reserves space for each kind of IO signal, and additionally stores data validity, update time stamp, and IO state information.

[0019] Preferably, the sending buffer area additionally stores output attribute of the output data.

[0020] Preferably, if the input and output tasks are executed in the same interrupt, the input and output use different device interfaces to form a full-duplex channel.

[0021] A system for realizing efficient and fast operation of an external device through a stream device interface, which is used to realize the above method, in the system, a CPU and an FPGA cooperate, various external device IO signals are connected to the FPGA, the FPGA is provided with a buffer area, and the CPU is provided with a stream device interface.

[0022] The FPGA caches the input IO signal information to a cache area, the CPU refreshes and acquires the information in the cache area through a stream device interface at a timing, and input signal is sent at a timing.

[0023] Meanwhile, the CPU caches information to be output and outputs the information to the FPGA through the stream device interface at a timing, and the FPGA outputs the received information to the peripheral device.

[0024] Preferably, the stream device interface comprises SDIO and SPI.

[0025] Preferably, the IO signal comprises GPIO, ADC sampling, serial port and communication interface signal of longitudinal differential protection.

[0026] The present application has the following advantages compared with the prior art:

[0027] In the present application, the CPU and the FPGA cooperate, various peripheral IO signals are input into the FPGA, the FPGA caches the input IO signal information to a cache area, the CPU refreshes and acquires the information in the cache area through a stream device interface at a timing, and input signal is sent at a timing; meanwhile, the CPU caches information to be output and outputs the information to the FPGA through the stream device interface at a timing, and the FPGA outputs the received information to the peripheral device. The CPU of the present application expands the IO peripheral interface through a stream device interface in a timing refreshing mode, solves the problem that the stream device interface cannot refresh the peripheral IO flexibly, and further improves the adaptability of the domestic CPU, and realizes efficient and fast operation of the peripheral device.

[0028] The present application is based on a CPU supporting high-speed stream device interfaces such as SDIO / SPI and not supporting synchronous / asynchronous parallel ports, cooperates with an FPGA chip as an IO peripheral expansion, defines a specific IO timing refreshing data mode according to the interface characteristics of the stream device peripheral such as SDIO / SPI, refreshes IO data at a timing, solves the problem that the CPU with the above characteristics cannot refresh the peripheral IO flexibly, greatly improves the efficiency of IO refreshing while ensuring the real-time performance of IO refreshing, guarantees the reliability of IO refreshing, and realizes efficient and fast operation of the peripheral device; and is suitable for the domestic power system control device with large IO data throughput and high real-time processing requirement. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 Figure 1 is a schematic diagram of the CPU expanding the IO peripheral interface through a parallel bus in a register mode;

[0030] Figure 2 Figure 2 is a schematic diagram of the CPU expanding the IO peripheral interface through a stream device interface in a register mode;

[0031] Figure 3The CPU of the application extends the IO peripheral interface through the flow device interface in a timing refreshing mode;

[0032] Figure 4 The CPU of the application extends the IO peripheral interface through the flow device interface in a timing refreshing mode. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical scheme and advantages of the application clearer, the technical scheme of the application will be described clearly and completely below in combination with the drawings in the embodiments of the application. The embodiments described in the application are only a part of the embodiments of the application, but not all the embodiments. Based on the spirit of the application, other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0034] As shown in Figure 3 and 4 Embodiment 1 of the application provides a method for efficiently and quickly operating peripherals through a flow device interface. The CPU and the FPGA cooperate, and various peripheral IO signals are connected to the FPGA. In the preferred but non-limiting embodiment of the application, the FPGA caches the input IO signal information to a cache area, the CPU obtains the information in the cache area through the flow device interface in a timing refreshing mode, and the input signal is uploaded in a timing refreshing mode.

[0035] At the same time, the CPU caches the information to be output and outputs the information to the FPGA through the flow device interface in a timing refreshing mode, and the FPGA outputs the received information to the peripheral.

[0036] In this way, the problem that the flow device interface cannot flexibly refresh the peripheral IO can be solved, and the adaptability of the domestic CPU can be improved.

[0037] Further preferably, the method for efficiently and quickly operating peripherals through the flow device interface comprises the following steps 1-5:

[0038] Step 1: The CPU controls the FPGA to generate a timing signal, and the timing period of the timing signal depends on the frequency at which the IO signal needs to be refreshed in the application;

[0039] Step 2: The FPGA latches the input IO signal information to the buffer area at the rising edge of the timing signal;

[0040] The information usually includes on-off input, low-speed serial interface (485, received data frame of longitudinal differential protection), ADC sampling data, etc.

[0041] The buffer area reserves space for each IO signal and attaches attribute information such as data validity, update timestamp and IO state.

[0042] Step 3: The CPU initiates a DMA transfer from the streaming device peripheral to memory in a timer interrupt. The streaming device peripheral, in cooperation with the DMA controller, completes the data transfer according to the configuration. The CPU incurs very little overhead.

[0043] Step 4: After the CPU detects the DMA transfer completion signal from Step 3, it can check the I / O image data in memory as needed and complete an I / O signal input, thus achieving timed uploading of the input signal. Because this process involves data transfer completed by the peripheral device and the DMA controller, it is not affected by the CPU multitasking potentially interrupting the peripheral device operation, resulting in high data reliability.

[0044] Step 5: During the timer interrupt, the CPU writes the data to be output into the allocated transmit buffer in memory. This transmit buffer is set in memory, and then a DMA transfer from memory to the streaming device interface is initiated. The overhead incurred by the CPU is still very small. After the DMA transfer is complete and the data verification passes, the FPGA begins to send the data out.

[0045] The transmit buffer also includes output attributes for downlink output data, such as whether the message needs to be output periodically;

[0046] It is important to note that if input and output tasks are executed in the same interrupt, different peripherals should be used for uplink and downlink to form a full-duplex channel and avoid mutual interference in order to ensure safe and reliable operation.

[0047] like Figure 4 As shown, Embodiment 2 of the present invention provides a system for efficient and fast operation of peripherals through a streaming device interface, used to implement the above method. In the system, the CPU and FPGA cooperate, and various peripheral I / O signals are connected to the FPGA.

[0048] The FPGA has a buffer, and the CPU has a stream device interface;

[0049] The FPGA buffers the input I / O signal information into a buffer area, and the CPU refreshes and obtains the information in the buffer area periodically through the streaming device interface to realize the periodic uploading of the input signal.

[0050] Meanwhile, the CPU buffers the information that needs to be output and refreshes it to the FPGA periodically through the streaming device interface. The FPGA then outputs the received information to the peripheral device.

[0051] Further preferably, the embodiment is constituted by a CPU with a SDIO, SPI and other stream device interface and a common FPGA, for the convenience of description, the uplink and downlink of IO data use two SDIO peripherals of the CPU. The SDIO and SPI are both peripherals of the CPU, and the SDIO or SPI and other stream device interfaces are only the interface types of the CPU and the FPGA, and in actual use, one or more of them can be selected according to the actual situation.

[0052] The SDIO clock is 50M, and the theoretical bandwidth is 200M bits / s.

[0053] The peripheral includes 16 GPIOs, each of which supports output, and the refresh rate of 1ms is required; 48 ADC samples, each of which is a 16-bit signed number, with a sampling rate of 2000 points / s; 4 serial ports, with a maximum rate of 1M bits / s, and a maximum frame length of 64 bytes; 2 optical differential channels, that is, longitudinal differential protection communication interfaces, with a rate of 2.048M bits / s, a frame length of 100 bytes, and 300 frames per second;

[0054] It can be seen that only a timing refresh period of 250us can meet the real-time requirements of the above-mentioned several IOs.

[0055] The beneficial effects of the present application are that, compared with the prior art:

[0056] In the present application, the CPU and the FPGA cooperate, various peripheral IO signals are input into the FPGA, the FPGA caches the input IO signal information to the cache area, the CPU refreshes and obtains the information in the cache area through the stream device interface, realizes the timing of the input signal, and at the same time, the CPU caches the information to be output and outputs it to the FPGA through the stream device interface, and the FPGA outputs the received information to the peripheral. The CPU of the present application expands the IO peripheral interface through the stream device interface in a timing refresh mode, solves the problem that the stream device interface cannot flexibly refresh the peripheral IO, and further improves the adaptability of the domestic CPU, realizes the efficient and rapid operation of the peripheral;

[0057] The present application is based on a CPU supporting SDIO / SPI and other high-speed stream device interfaces, and not supporting synchronous / asynchronous parallel ports, cooperates with an FPGA chip as an IO peripheral expansion, and defines a specific IO timing refresh data mode according to the interface characteristics of the SDIO / SPI and other stream device peripherals, refreshes the IO data, solves the problem that the CPU with the above characteristics cannot flexibly refresh the peripheral IO, greatly improves the efficiency of the IO refresh while ensuring the real-time of the IO refresh, and ensures the reliability of the IO refresh;

[0058] The present application is suitable for the domestic power system control device with large IO data throughput and high real-time processing requirements.

[0059] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0060] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, a

[0061] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0062] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0063] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0064] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0065] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0066] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0067] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, but not limiting the technical solutions of the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application. Any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered within the protection scope of the claims of the present application.

Claims

1. A method for achieving fast operation of peripherals through a streaming device interface, wherein the CPU and FPGA cooperate, and various peripheral I / O signals are connected to the FPGA, characterized in that: The FPGA buffers the input I / O signal information into a buffer area, and the CPU refreshes and obtains the information in the buffer area periodically through the streaming device interface to realize the periodic uploading of the input signal. Meanwhile, the CPU buffers the information that needs to be output and refreshes it to the FPGA periodically through the streaming device interface. The FPGA then outputs the received information to the peripheral device. The method includes the following steps: Step 1: The CPU controls the FPGA to generate timing signals; Step 2: The FPGA latches the input I / O signal information into the buffer on the rising edge of the timing signal; Step 3: The CPU initiates a DMA transfer from the streaming device interface to memory in a timer interrupt. The streaming device peripheral, in cooperation with the DMA controller, completes the data transfer according to the configuration. Step 4: After the CPU detects the relocation completion signal, it checks the IO image data in memory as needed and completes one IO signal input, thus realizing the timed uploading of the input signal; Step 5: In the timer interrupt, the CPU also writes the data to be output into the allocated send buffer in memory, and then initiates a DMA transfer from memory to the stream device interface.

2. The method for achieving fast operation of peripherals through a streaming device interface according to claim 1, characterized in that: The timing period of the timing signal is set according to the frequency at which the IO signal needs to be refreshed in the application.

3. The method for achieving fast operation of peripherals through a streaming device interface according to claim 1, characterized in that: The information includes digital inputs, received data frames from longitudinal differential protection, and ADC sampling data.

4. The method for achieving fast operation of peripherals through a streaming device interface according to claim 1, characterized in that: The buffer in the FPGA reserves space for each type of I / O signal and adds data validity, update time stamp, and I / O status information.

5. The method for achieving fast operation of peripherals through a streaming device interface according to claim 1, characterized in that: The send buffer adds output attributes to the output data.

6. The method for achieving fast operation of peripherals through a streaming device interface according to claim 1, characterized in that: If input and output tasks are executed in the same interrupt, then the input and output use different device interfaces to form a full-duplex channel.

7. A system for implementing fast operation of peripherals via a streaming device interface, used to implement the method of any one of claims 1-6, wherein in the system, the CPU and FPGA cooperate, and various peripheral I / O signals are connected to the FPGA, characterized in that: The FPGA has a buffer, and the CPU has a stream device interface; The FPGA buffers the input I / O signal information into a buffer area, and the CPU refreshes and obtains the information in the buffer area periodically through the streaming device interface to realize the periodic uploading of the input signal. Meanwhile, the CPU buffers the information that needs to be output and refreshes it to the FPGA periodically through the streaming device interface. The FPGA then outputs the received information to the peripheral device.

8. A system for rapid operation of peripherals via a streaming device interface according to claim 7, characterized in that: The streaming device interface includes SDIO and SPI.

9. A system for rapid operation of peripherals via a streaming device interface according to claim 7, characterized in that: The I / O signals include GPIO, ADC sampling, serial port, and longitudinal differential protection communication interface signals.

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