Resource management chip, method, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a resource management chip, including: a device controller, a hub, a plurality of bus devices, a plurality of first buffers, and an access controller; the hub includes a plurality of ports and a plurality of first endpoints; the device controller is configured to receive a resource acquisition instruction, allocate a bus device for receiving data, and configure a corresponding port and first endpoint for the bus device; the bus device includes a plurality of second endpoints; the bus device is configured to send the received data to the corresponding first buffer through the second endpoint; the first buffer is configured to store data and send the data to the hub under the control of the access controller; the hub is configured to receive data through the first endpoint and output the data to the outside of the chip under the control of the access controller; the access controller is configured to receive a control instruction sent by the device controller and control data transmission between the first buffer and the hub, and between the hub and the outside of the chip according to the control instruction.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a resource management chip, method, electronic device and readable storage medium. Background Art

[0002] Since its introduction, Universal Serial Bus (USB) has been widely used in computers, complex terminals, network infrastructure and other fields, becoming one of the standard expansion interfaces and essential interfaces of this century. The latest USB protocol has developed to USB 4.0 version. Currently, the data exchange between computers and other smart devices and the outside world is mainly carried out through USB interface and network.

[0003] In the prior art, for large network devices such as servers or switches, on the device side of the USB bus, USB devices include single-function and multi-function USB devices. However, regardless of whether it is a single-function or multi-function USB device, the function and related configuration of the device have been solidified at the factory, so there is a problem that the USB device hardware has a single function and resources cannot be allocated. Summary of the invention

[0004] The present invention provides a resource management method, device, electronic device and readable storage medium, so as to solve the problem that the USB device hardware has a single function and cannot allocate resources.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0006] In a first aspect, the present invention provides a resource management chip, the chip comprising: a device controller, a hub, a plurality of bus devices, a plurality of first buffers and an access controller;

[0007] The hub includes a plurality of ports and a plurality of first endpoints;

[0008] The device controller is used to receive a resource acquisition instruction, and allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding port and a first endpoint for the bus device; wherein the bus device is connected to the hub through the port;

[0009] The bus device comprises a plurality of second endpoints; the bus device is used to send received data to the corresponding first buffer via the second endpoints;

[0010] The first buffer is used to store the data and send the data to the hub under the control of the access controller;

[0011] The hub is used to receive the data through the first endpoint and output the data outside the chip under the control of the access controller;

[0012] The access controller is used to receive the control instructions sent by the device controller and control the data transmission between the first buffer and the hub, and between the hub and the outside of the chip according to the control instructions.

[0013] Optionally, the device controller includes a first register, a second register, and a third register;

[0014] The first register is used to query the current status of each bus device and the hub, and set the bus device for receiving data, the corresponding port of the bus device, and the first endpoint according to the resource acquisition instruction;

[0015] The second register is used to send a first control instruction to the access controller, so that the access controller opens a specified data transmission channel according to the first control instruction;

[0016] The third register is used to set a corresponding first buffer for each bus device and query the current status of each first buffer.

[0017] Optionally, the bus device includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint is arranged in the first interface;

[0018] The second control endpoint is used to control the second endpoint to receive data under the control of the first register and send the data to the corresponding first buffer;

[0019] The first register is further used to set the data transmission type of the first interface according to the resource acquisition instruction, so that the first interface receives data of the data transmission type through the second endpoint; wherein, the data transmission type is any one of a video control type, a video transmission type, a serial port transmission type, a network transmission type, and a human-computer interaction type.

[0020] Optionally, the hub further includes a first control endpoint and a second buffer;

[0021] The first control endpoint is used to control the first endpoint to receive the data sent by the first buffer under the control of the first register and send the data to the second buffer for storage through the first endpoint;

[0022] The second buffer is used to receive and store the data sent by each of the first endpoints, and to send the data to the outside of the chip according to the second control instruction sent by the access controller.

[0023] Optionally, the second buffer includes a frame linked list and a data linked list;

[0024] The data linked list is used to cache the data sent by the bus device to the hub through the first buffer;

[0025] The frame linked list is used to determine the data to be transmitted by the hub currently, and to send the data to be transmitted to the outside of the chip according to the second control instruction.

[0026] Optionally, the frame linked list is an array of pointers, and any pointer in the frame linked list points to a piece of data in the data linked list;

[0027] The frame linked list is further used to set the proportion of each type of data packet to be transmitted in the current frame according to the second control instruction, and to obtain the data to be transmitted in the next frame from the data linked list according to the next pointer after sending the data in the current frame, and update the pointer to be stored in the device controller.

[0028] Optionally, the access controller includes a plurality of transmission channels, a channel selection module and a bus arbiter;

[0029] Each of the plurality of transmission channels has a channel number and a corresponding channel priority;

[0030] The channel selection module is used to open the transmission channel specified by the first control instruction sent by the device controller according to the first control instruction; wherein, the first control instruction includes the channel number of the transmission channel to be opened;

[0031] The bus arbiter is used to sort the transmission channels according to the channel numbers when the channel priorities of the plurality of transmission channels are the same, and control the transmission channels to perform data transmission according to the sorting order.

[0032] Optionally, the first buffer includes a routing logic module, a shared transmission buffer and a dedicated transmission buffer;

[0033] The routing logic module is used to parse the data packet type of the data sent by the bus device, and filter the data packets that do not meet the preset regulations to determine that the data sent by the bus device is the first data that meets the first latency requirement or the second data that meets the second latency requirement;

[0034] The shared transmission buffer is used to receive the first data routed by the routing logic module and, under the control of the access controller, send the first data to the hub;

[0035] The dedicated transmission buffer is used to receive the second data routed by the routing logic module and, under the control of the access controller, send the second data to the hub.

[0036] In a second aspect, the present invention provides a resource management method applied to any one of the resource management chips described above. The method includes:

[0037] Sending a resource acquisition instruction to the device controller to control the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configuring a corresponding hub port and a first endpoint for the bus device;

[0038] Controlling the bus device to receive the data through the device controller and sending the data to the corresponding first buffer through the second endpoint;

[0039] Controlling the first buffer to receive and store the data sent by the bus device through the device controller;

[0040] Sending a control instruction to the access controller through the device controller to control the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and output the data to the outside of the chip.

[0041] Optionally, the resource acquisition instruction is generated according to a remote access instruction sent by a remote client to an external device of the chip; when the remote access instruction indicates that the remote client sends data to the external device, before sending the resource acquisition instruction to the device controller, the method further includes:

[0042] Receiving a remote data packet sent by the remote client through a resource management program running on the chip;

[0043] Sending the remote data packet to a data transmission program running on the chip through the resource management program for parsing and processing to obtain a first data packet;

[0044] The sending the resource acquisition instruction to the device controller to control the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configuring a corresponding hub port and a first endpoint for the bus device includes:

[0045] The resource management program sends a resource acquisition instruction to the device controller through the chip driver running on the chip, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding hub port and a first endpoint for the bus device;

[0046] Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and output the data to the outside of the chip, includes:

[0047] Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and transmit the data to the external device, so as to realize the remote access of the remote client to the external device.

[0048] Optionally, in the case that the remote access instruction indicates that the external device sends data to the remote client, sending a resource acquisition instruction to the device controller, controlling the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding hub port and a first endpoint for the bus device, includes:

[0049] The resource management program sends a resource acquisition instruction to the device controller through the chip driver, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding hub port and a first endpoint for the bus device;

[0050] Controlling the bus device to receive the data through the device controller, and sending the data to the corresponding first buffer through the second endpoint, includes:

[0051] Controlling the bus device to receive a local data packet sent by the central processing unit of the external device through the device controller, and sending the local data packet to the corresponding first buffer for storage through the second endpoint;

[0052] Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and output the data to the outside of the chip, includes:

[0053] Send a control instruction to the access controller through the device controller, control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub to receive the data through the first endpoint and transmit the data to the data transfer program;

[0054] After sending the control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and transmit the data to the data transfer program, the method further includes:

[0055] Parse and process the local data packet through the data transfer program to obtain a second data packet, and send the second data packet to the resource management program;

[0056] Send the second data packet to the remote client through the resource management program to realize remote access of the remote client to the external device.

[0057] In a third aspect, the present invention provides an electronic device including the resource management chip described in any one of the above.

[0058] In a fourth aspect, the present invention provides a readable storage medium, when the instructions in the storage medium are executed by the chip of the electronic device, enabling the electronic device to execute the resource management method described in any one of the above.

[0059] The resource management chip provided by the embodiments of the present invention can dynamically allocate bus devices for receiving data through the device controller in the chip, and configure corresponding hub ports and first endpoints for the bus devices, so that multiple bus devices of the chip, multiple ports of the hub, and multiple first endpoints are dynamically configurable in hardware, and can be flexibly configured through the device controller according to requirements to implement various different functions, and to a certain extent solve the problems of resource solidification of USB physical devices, single function in hardware, and inability to allocate resources. In addition, by setting a first buffer corresponding to each of the multiple bus devices in the chip, a data cache area can be added to the bus device, thereby increasing the data storage capacity of the chip. In addition, the device controller can control the first buffer to send the stored data to the hub through the access controller, and control the hub to output the stored data to the outside of the chip. In this way, the access controller is used to control the data transmission between the first buffer and the hub, and between the hub and the outside of the chip, which can better coordinate multiple bus devices in the chip, multiple ports of the hub, and multiple first endpoints, and also provides a hardware basis for improving the overall data transmission efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0061] Figure 1 It is a structural diagram of a resource management chip provided by an embodiment of the present invention;

[0062] Figure 2 It is a topology diagram of a USB bus in the prior art;

[0063] Figure 3 It is a schematic internal logic diagram of a USB device in the prior art;

[0064] Figure 4 It is a structural diagram of another resource management chip provided by an embodiment of the present invention;

[0065] Figure 5 It is a time slice schematic diagram of a USB protocol in the prior art;

[0066] Figure 6 It is a schematic diagram of the DMA control logic provided by an embodiment of the present invention;

[0067] Figure 7 It is a structural diagram of yet another resource management chip provided by an embodiment of the present invention;

[0068] Figure 8 It is a step flowchart of a resource management method provided by an embodiment of the present invention;

[0069] Figure 9 It is a schematic diagram of remote access to a server or a switch provided by an embodiment of the present invention;

[0070] Figure 10 It is a structural diagram of an electronic device provided by an embodiment of the present invention.

[0071] Reference numerals:

[0072] Device controller 10; Hub 20; Bus device 30; First buffer 40; Access controller 50; Port 201; First endpoint 202; Second endpoint 301; First register 101; Second register 102; Third register 103. Detailed implementation manners

[0073] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0074] Figure 1 FIG. 4 is a structural diagram of a resource management chip provided by an embodiment of the present invention. The chip includes: a device controller 10, a hub 20, a plurality of bus devices 30, a plurality of first buffers 40, and an access controller 50; the hub 20 includes a plurality of ports 201 and a plurality of first endpoints 202; the device controller 10 is configured to receive a resource acquisition instruction, and allocate a bus device 30 for receiving data according to the resource acquisition instruction, and configure a corresponding port 201 and a first endpoint 202 for the bus device 30; wherein, the bus device 30 accesses the hub 20 through the port 201; the bus device 30 includes a plurality of second endpoints 301; the bus device 30 is configured to send the received data to a corresponding first buffer 40 through the second endpoint 301; the first buffer 40 is configured to store the data and send the data to the hub 20 under the control of the access controller 50; the hub 20 is configured to receive the data through the first endpoint 202 and output the data to the outside of the chip under the control of the access controller 50; the access controller 50 is configured to receive a control instruction sent by the device controller 10 and control data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip according to the control instruction.

[0075] In an embodiment of the present invention, the device controller 10 is connected to the hub 20, a plurality of bus devices 30, a plurality of first buffers 40, and the access controller 50 through internal circuits of the chip. The device controller 10 can perform general logical settings on the hub 20, a plurality of bus devices 30, a plurality of first buffers 40, and the access controller 50, and query the status of the hub 20 and a plurality of bus devices 30. The device controller 10 can issue a control instruction to the access controller 50 to control the access controller 50 to control the hub 20, a plurality of bus devices 30, and a plurality of first buffers 40 to perform data interaction between the inside of the chip and external devices of the chip.

[0076] In an embodiment of the present invention, the hub 20 includes a plurality of ports 201 and a plurality of first endpoints 202. The device controller 10 is configured to receive a resource acquisition instruction sent by software running on the chip or software running on the central processing unit (CPU) of a computer device connected to the chip, allocate a bus device 30 for receiving data according to the resource acquisition instruction, and configure a corresponding port 201 and a first endpoint 202 for the bus device 30. Among them, a plurality of bus devices 30 are respectively connected to the hub 20 through a plurality of ports 201 of the hub 20. The device controller 10 can form an analog "insertion" action by configuring the port 201 and the first endpoint 202 of the hub 20 for the bus device 30, so that the bus device 30 establishes an actual communication connection with the hub 20. The bus device 30 can access the hub 20 through the port 201, and the first endpoint 202 of the hub 20 can receive the data sent by the bus device 30.

[0077] In an embodiment of the present invention, the bus device 30 includes a plurality of second endpoints 301. The second endpoint 301 is the smallest addressable unit in the bus device 30, corresponding to a data buffer on the hardware of the bus device 30. The second endpoint 301 is used to receive and send data. The second endpoint 301 may be a single-byte or 4-byte 32-bit buffer. This is only an example here, and the embodiment of the present invention does not make any limitations. The bus device 30 is configured to receive data sent from outside the chip through the second endpoint 301 and send the received data to the corresponding first buffer 40 through the second endpoint 301. When there is data in a plurality of second endpoints 301 in the bus device 30, the data can be sent to the corresponding first buffer 40 of the bus device 30 in real time for storage. The device controller 10 configures a corresponding first buffer 40 for a plurality of bus devices 30 during chip initialization, that is, by establishing an address mapping between the first buffer 40 and the corresponding bus device 30, so that the first buffer 40 is bound to the corresponding bus device 30, thereby receiving the data sent by the bus device 30 through the second endpoint 301.

[0078] In an embodiment of the present invention, a plurality of first buffers 40 are, in hardware, a random access memory (RAM) divided into a plurality of regions. One region serves as a first buffer 40. The first buffer 40 has more storage space than the second endpoint 301 and can store more data than the second endpoint 301. The first buffer 40 is configured to store the data sent by the corresponding bus device 30 through the second endpoint 301. When the first buffer 40 receives a data transfer instruction from the access controller 50, it can route the corresponding data in the stored data to the first endpoint 20 corresponding to the bus device 30 in the hub 20 according to the data transfer instruction.

[0079] In an embodiment of the present invention, the hub 20 includes a plurality of ports 201, which can support the access of a plurality of bus devices 30. The hub 20 can manage the plurality of accessed bus devices 30 and monitor the hot plug and unplug events of the bus devices 30. The hub 20 is used to receive data sent by the bus device 30 through the first buffer via the first endpoint 202. Among them, the first endpoint 202 is the smallest addressable unit in the hub 20, corresponding to a data buffer on the hub 20, and the first endpoint 202 is used to receive and send data. The first endpoint 202 can be a single-byte or 4-byte 32-bit buffer. This is only an example here, and the embodiment of the present invention is not limited thereto. When there is data in a plurality of first endpoints 202 in the hub 20, the data can be sent to the data cache area of the hub 20 in real time for storage. When the hub 20 receives a data transmission instruction from the access controller 50, it can output the data stored in the data cache area to the outside of the chip according to the data transmission instruction.

[0080] In an embodiment of the present invention, after the access controller 50 receives the control instruction sent by the device controller 10, it controls the first buffer 40 to send the stored data to the hub 20 according to the data transmission requirements represented by the control instruction, and the hub 20 outputs the stored data to the outside of the chip.

[0081] For example, the resource management chip according to the embodiment of the present invention may be a Field Programmable Gate Array (FPGA) chip. The USB function logic (USB IP) implemented inside the FPGA chip may include: a USB device controller, a USB hub, multiple USB bus devices, multiple first buffers 40, and an access controller 50. Among them, the first buffer 40 may be a First Input First Output (FIFO) memory, and the access controller 50 may be a Direct Memory Access (DMA) controller. Among them, the USB hub may include six downstream ports 201 and 15 first endpoints 202, and may support up to six USB bus devices to be connected to the USB hub through the ports respectively for management. The USB device may include 15 second endpoints 301. Among them, the first endpoints 202 and the second endpoints 301 according to the embodiment of the present invention may be programmable endpoints. The programmable endpoints support all four data transfer types, namely Bulk transfer, Control transfer, Isochronous transfer, and Interrupt transfer, and also support dynamic adjustment of parameters, such as parameters like the maximum transfer packet size and polling time interval of data transfer.

[0082] It should be noted that as a high-speed transmission bus, USB needs to carry the transmission of data packets of multiple service types. In order to make full use of its bandwidth, in the USB protocol, from the three perspectives of bandwidth, latency, and integrity check, the data packets are divided into 4 transfer types: Control transfer, Isochronous transfer, Interrupt transfer, and Bulk transfer. Among them, Control transfer is used to transmit bursty and non-periodic data, with a small amount of data transmitted, and has low requirements for bandwidth and latency, but requires the data to be correct, so integrity check is required; Isochronous transfer is used to transmit isochronous data, with a large amount of data, and has high requirements for bandwidth and latency, but does not require the data to be correct, such as a camera; Interrupt transfer is used to transmit small amounts of real-time data, with high requirements for latency and requires the data to be correct, such as a keyboard and a mouse; Bulk transfer is used to transmit large amounts of storage-type data, with low requirements for latency but requires the data to be correct, such as a USB flash drive.

[0083] The resource management chip provided by the embodiment of the present invention can dynamically allocate the bus device 30 for receiving data through the device controller 10 in the chip, and configure the corresponding port 201 and the first endpoint 202 for the bus device 30, so that multiple bus devices 30 of the chip, multiple ports 201 of the hub, and multiple first endpoints 202 are dynamically configurable in hardware, and can be flexibly configured through the device controller according to requirements, realizing a variety of different functions, and to a certain extent solving the problems of resource solidification of USB physical devices, single function in hardware, and inability to allocate resources. In addition, a first buffer 40 corresponding to each of the multiple bus devices 30 is provided in the chip, which can add a data cache area for the bus device 30, thereby increasing the data storage capacity of the chip. In addition, the device controller 10 can control the access controller 50 to control the first buffer 40 to send the stored data to the hub 20, and control the hub 20 to output the stored data to the outside of the chip. In this way, the access controller is used to control the data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip, which can better coordinate multiple bus devices 30 in the chip, multiple ports 201 of the hub, and multiple first endpoints 202, and also provides a hardware basis for improving the overall data transmission efficiency of the chip.

[0084] It should be noted that in the prior art, the mandatory components of the USB bus topology include: USB controller and root hub. Among them, the root hub is generally integrated inside the USB controller, and the optional components included in the root hub include: non-root hubs of up to 5 levels and various forms of USB devices. The USB controller and the root hub are hardware implementations on the host side, which are used to initiate USB request block (USB Request Block, URB) requests and detect hot plug events of USB devices. The current USB controller standards include: OHCI interface standard (Open Host Controller Interface, OHCI), EHCI interface standard (Enhanced Host Controller Interface, EHCI) and XHCI interface standard (eXtensible Host Controller Interface, XHCI), which support USB1.1, USB2.0, and USB3.0 protocols respectively. As a device-side implementation on the USB bus, a functional logic of a USB device is called a function. A single-function USB device only contains one function, such as a USB flash drive, a mouse, etc. There are two ways to implement multifunctional USB device hardware design. One is called a compound device, which consists of a hub and multiple functions bound to it. The other is called a composite device, which consists of multiple independent functions directly and is organized by Interface Association Descriptors (IADs). Existing USB products, whether they are single-function USB devices, compound devices, or composite devices, have their functions fixed at the factory. For example, a USB flash drive only supports storage functions, and a USB serial port only supports serial communication functions.

[0085] Figure 2 It is a topological diagram of the USB bus in the prior art, such as Figure 2 As shown, the first layer is the host and the root hub. The root hub is generally integrated in the USB controller. The root hub can include up to 5 levels of non-root hubs and various forms of USB devices. A functional logic of a USB device is called a function. Figure 2 The second to sixth layers include five levels of non-root hubs: hub 2 to hub 7. The third to sixth layers also include multiple functions of USB devices. Hub 7 on the sixth layer and the functions on the seventh layer can form a composite device.

[0086] It should be noted that the resource management chip provided by the embodiment of the present invention can implement a composite device with dynamically configurable device-side resources through the hub 20 and multiple bus devices 30. In the USB protocol, the internal resources of the device are further refined into three levels, including Configuration, Interface, and Endpoint. An Interface represents a basic functional logic of a USB device, and in the USB protocol, it is also called a function. When a USB device has multiple functions, it will include multiple Interfaces. Multiple Interfaces combined together are called a Configuration, and different Configurations make the device exhibit different function combinations. An Endpoint is the smallest addressable unit in a USB device, corresponding to a data buffer on the hardware, used to store and send USB data, and an Interface can include multiple Endpoints. Figure 3 It is a schematic diagram of the internal logic of a USB device in the prior art, as Figure 3 shown. The device includes two function combinations, Configuration 0 and Configuration 1. Configuration 0 includes two functions, Interface 0 and Interface 1, and Configuration 1 includes three functions, Interface 0, Interface 1, and Interface 2. Each interface includes 1 or 2 endpoints, used to store and send USB data.

[0087] Figure 4It is a structural diagram of another resource management chip provided by an embodiment of the present invention. The chip includes: a hub 20, a plurality of bus devices 30, a plurality of first buffers 40, an access controller 50, a first register 101, a second register 102, and a third register 103; the hub 20 includes a plurality of ports 201 and a plurality of first endpoints 202; the first register 101 is used to query the current status of each of the bus devices 30 and the hub 20, and, according to the resource acquisition instruction, set the bus device 30 for receiving data, the port 201 corresponding to the bus device 30, and the first endpoint 202; the second register 102 is used to send a first control instruction to the access controller 50, so that the access controller 50 opens a specified data transmission channel according to the first control instruction; the third register 103 is used to respectively set a corresponding first buffer 40 for each bus device 30, and query the current status of each of the first buffers 40; wherein, the bus device 30 accesses the hub 20 through the port 201; the bus device 30 includes a plurality of second endpoints 301; the bus device 30 is used to send the received data to the corresponding first buffer 40 through the second endpoint 301; the first buffer 40 is used to store the data, and, under the control of the access controller 50, send the data to the hub 20; the hub 20 is used to receive the data through the first endpoint 202, and, under the control of the access controller 50, output the data to the outside of the chip; the access controller 50 is used to receive the first control instruction sent by the second register 102, and control data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip according to the first control instruction.

[0088] It should be noted that the descriptions of the hub 20, the plurality of bus devices 30, the plurality of first buffers 40, the access controller 50, the port 201, the first endpoint 202, and the second endpoint 301 can refer to the detailed description of the above resource management chip, and will not be repeated here.

[0089] In an embodiment of the present invention, the overall resources of the chip are configured and managed through a first register 101, a second register 102, and a third register 103. Among them, the first register 101 is used for setting general logic and querying status, and can query the current status of each bus device 30 and hub 20. After receiving a resource acquisition instruction sent by software running on the chip or software running on the CPU of a computer device connected to the chip, it can set the bus device 30 for receiving data according to the resource acquisition instruction, and configure the corresponding hub port 201 and the first endpoint 202 for the bus device 30 to form an analog insertion action, so that the bus device 30 establishes an actual communication connection with the hub 20. The bus device 30 can access the hub 20 through the port 201, and the first endpoint 202 of the hub 20 can receive the data sent by the bus device 30.

[0090] In an embodiment of the present invention, the second register 102 is used to send a first control instruction to the access controller 50, so that the access controller 50 opens a specified data transmission channel according to the first control instruction, controls the first buffer 40 to send the stored data to the hub 20 according to the data transmission requirements represented by the first control instruction, and the hub 20 outputs the stored data to the outside of the chip. The third register 103 is used to configure respective corresponding first buffers 40 for multiple bus devices 30 during chip initialization, that is, by establishing an address mapping between the first buffer 40 and the corresponding bus device 30, so that the first buffer 40 is bound to the corresponding bus device 30, thereby receiving the data sent by the bus device 30 through the second endpoint 301. The third register 103 is also used to query the current status of each first buffer 40, support the Packet Internet Groper Flow (PING Flow) unique to the USB2.0 protocol high-speed mode, in response to the request of the USB host controller to actively query whether the USB device is currently idle, and determine whether the USB device is ready to receive data before actually sending a data transmission request, which can provide hardware support for software optimization.

[0091] The resource management chip provided by the embodiment of the present invention can dynamically allocate the bus device 30 for receiving data through the first register 101 in the chip, and configure the corresponding port 201 and the first endpoint 202 for the bus device 30, so that multiple bus devices 30 of the chip, multiple ports 201 of the hub, and multiple first endpoints 202 are dynamically configurable in hardware, and can be flexibly configured through the device controller according to requirements, realizing a variety of different functions, and to a certain extent solving the problems of resource solidification of USB physical devices, single function on hardware, and inability to allocate resources. In addition, a first buffer 40 corresponding to each of the multiple bus devices 30 is provided in the chip, which can add a data cache area for the bus device 30, thereby increasing the data storage capacity of the chip. In addition, the second register 102 can control the first buffer 40 to send the stored data to the hub 20 through the access controller 50, and control the hub 20 to output the stored data to the outside of the chip. In this way, the access controller is used to control the data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip, which can better coordinate multiple bus devices 30 in the chip, multiple ports 201 of the hub, and multiple first endpoints 202. The third register 103 can determine whether the USB device is ready to receive data before actually sending a data transmission request by querying the current status of each first buffer 40, which can provide a hardware basis for improving the overall data transmission efficiency of the chip.

[0092] Optionally, the bus device 30 includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint 301 is disposed in the first interface; the second control endpoint is used to control the second endpoint 301 to receive data under the control of the first register 101, and send the data to the corresponding first buffer 40; the first register 101 is further used to set the data transmission type of the first interface according to the resource acquisition instruction, so that the first interface receives data of the data transmission type through the second endpoint 301; wherein, the data transmission type is any one of a video control type, a video transmission type, a serial port transmission type, a network transmission type, and a human-computer interaction type.

[0093] In an embodiment of the present invention, an interface represents a basic functional logic of any bus device, and an interface may include multiple endpoints. The bus device 30 in the embodiment of the present invention includes one interface, i.e., the first interface, indicating that the bus device 30 has a certain functional logic. The bus device 30 in the embodiment of the present invention may have any one of functions such as video control, video transmission, serial port transmission, network transmission, and human-computer interaction, and the embodiment of the present invention does not limit this. The first interface may include a second control endpoint and multiple second endpoints 301. The second control endpoint is used to control the multiple second endpoints 301 to receive data and send the data to the corresponding first buffer 40 of the bus device 30.

[0094] For example, the USB hub of the resource management chip in the embodiment of the present invention may include six downstream ports 201 and 15 first endpoints 202, and may support up to six USB bus devices to be respectively connected to the USB hub through the ports for management. Among them, each USB bus device includes a first interface and at most 15 second endpoints 301. The first interface may be a programmable interface, and each first interface may correspond to a certain functional logic. In this way, the resource management chip in the embodiment of the present invention may have 6 programmable interfaces, which are respectively used for UVC video control, video transmission, CDC serial port transmission / ACM, CDC (ECM) network transmission, and two groups of human interface devices (Human Interface Device, HID). Compared with a solid-state USB device, the programmable interface can support dynamic adjustment of its own parameters. For example, the number of bound ports, whether to enable alternate settings, etc. can be flexibly set, and the interface can be dynamically combined through the USB device controller to form a functional combination, i.e., configuration. It can also simulate the action of inserting or unplugging the USB hub by the USB device controller.

[0095] In the embodiment of the present invention, the first register 101 is further used to set the data transmission type of the first interface according to the resource acquisition instruction, that is, to set the function for the bus device 30, so that the bus device 30 may have any one of functions such as video control, video transmission, serial port transmission, network transmission, and human-computer interaction. Under the control of the first register 101, the first interface may receive data of the corresponding data transmission type through the second endpoints 301; wherein, the data transmission type is any one of video control, video transmission, serial port transmission, network transmission, and human-computer interaction.

[0096] The bus device 30 according to an embodiment of the present invention includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint 301 is disposed in the first interface; the second control endpoint is configured to control the second endpoint 301 to receive data under the control of the first register 101, and send the data to the corresponding first buffer 40; the first register 101 is further configured to set the data transfer type of the first interface according to the resource acquisition instruction, so that the first interface receives data of the data transfer type through the second endpoint 301; wherein, the data transfer type is any one of a video control type, a video transfer type, a serial port transfer type, a network transfer type, and a human-computer interaction type. In this way, the chip according to the embodiment of the present invention can have a bus device 30 with multiple functions. Further, the first register 101 can dynamically allocate multiple bus devices 30 according to actual requirements, so as to solve the problems of fixed bus device resources, single function, and inability to be flexibly configured.

[0097] Optionally, the hub 20 further includes a first control endpoint and a second buffer; the first control endpoint is configured to control the first endpoint 202 to receive the data sent by the first buffer 40 under the control of the first register 101, and send the data to the second buffer for storage through the first endpoint 202; the second buffer is configured to receive and store the data sent by each of the first endpoints 202, and send the data to the outside of the chip according to the second control instruction sent by the access controller 50.

[0098] In an embodiment of the present invention, the hub 20 may include a default control endpoint, that is, a first control endpoint and a second buffer. The second buffer is a cache area in terms of hardware. The second buffer has more storage space than the first endpoint 202 and can store more data than the first endpoint 202. The second buffer is configured to receive and store the data sent by the first buffer 40 through each of the first endpoints 202. When the second buffer receives the second control instruction sent by the access controller 50, it can send the corresponding data to the outside of the chip according to the data transfer requirements represented by the second control instruction. Optionally, the hub 20 according to an embodiment of the present invention may further include a status interrupt input endpoint, and the status interrupt input endpoint is used to characterize that the endpoint is of an input type, indicating that the current data transfer direction is from the bus device to the host external to the chip.

[0099] For example, a USB hub may include a first control endpoint, a status interrupt input endpoint, at most 15 first endpoints 202, and a second buffer. Among them, the second buffer may be a FIFO memory. The USB hub can be connected to the USB host controller inside the CPU of an external computer device through 4 USB pins of the FPGA chip via a USB cable.

[0100] The hub 20 provided by the embodiment of the present invention can conveniently implement data transmission between the first buffer 40 and the second buffer through the first control endpoint to control the first endpoint 202. Setting the second buffer can add a data cache area for the hub 20, thereby increasing the data storage capacity of the chip. In addition, under the control of the access controller 50, the second buffer can conveniently implement data transmission between the chip and external devices, providing a hardware basis for improving the overall data transmission efficiency of the chip.

[0101] Optionally, the second buffer includes a frame linked list and a data linked list; the data linked list is used to cache data sent by the bus device 30 to the hub 20 through the first buffer 40; the frame linked list is used to determine the data to be transmitted by the hub 20 currently, and send the data to be transmitted to the outside of the chip according to the second control instruction.

[0102] It should be noted that to meet the transmission of multiple types of data on the same shared path, the USB protocol divides data transmission into multiple time slices from the time dimension. Each time slice is called a frame or a microframe. In each frame, the highest 80% of the time is used to preferentially transmit data with high latency requirements, such as interrupt transmission and isochronous transmission type data, and the remaining time is used to transmit data with low latency requirements, such as control transmission and bulk transmission type data.

[0103] The second buffer of the embodiment of the present invention includes two levels of linked lists. The first level is a data linked list, and the second level is a frame linked list. Among them, the frame linked list is used to determine the data to be transmitted within the current time slice of the hub 20, and preferentially transmit interrupt transmission and isochronous transmission type data within the highest 80% of the time of each frame according to the second control instruction of the access controller 50, and transmit control transmission and bulk transmission type data in the remaining time, and send the data to be transmitted to the outside of the chip.

[0104] Figure 5 is a schematic diagram of the time slice of the USB protocol in the prior art, as Figure 5 shown, the time slice size of a full-speed or low-speed frame is 1 millisecond, and each frame includes a full-speed isochronous data payload. The time slice size of a high-speed microframe is 125 microseconds. In the USB2.0 protocol, the scale of the high-speed microframe is 1 / 8 of the full-speed frame. Each frame includes a high-speed isochronous data payload. In the highest 80% of the time of each frame including a full-speed isochronous data payload, interrupt transmission and isochronous transmission type data are preferentially transmitted, and control transmission and bulk transmission type data are transmitted in the remaining time.

[0105] The second buffer in the embodiment of the present invention can meet the requirements of the bus protocol for the data transmission time slice through the frame linked list and the data linked list, which can make the chip in the embodiment of the present invention have better compatibility and practical value, and also provide a hardware basis for improving the overall data transmission efficiency of the chip.

[0106] Optionally, the frame linked list is an array of pointers, and any pointer in the frame linked list points to a piece of data in the data linked list; the frame linked list is further configured to set the proportion of each type of data packet to be transmitted in the current frame according to the second control instruction, and after sending the data in the current frame, obtain the data to be transmitted in the next frame from the data linked list according to the next pointer, and update the pointer to be stored in the device controller.

[0107] In the embodiment of the present invention, the frame linked list is an array of pointers, including multiple pointers. Each pointer in the frame linked list points to multiple pieces of data in the data linked list respectively. After receiving the second control instruction sent by the access controller 50, the frame linked list can set the proportion of each type of data packet to be transmitted in the current frame according to the second control instruction, and determine to preferentially transmit data of the interrupt transmission and synchronous transmission types within the highest 80% of the time of the current frame, and then transmit data of the control transmission and bulk transmission types in the remaining time. After the current frame starts transmission, the frame linked list can prepare the data to be sent in the next frame, that is, select the specified data to be transmitted from the data linked list through the pointer, and send the pointer corresponding to the selected data to the register corresponding to the frame linked list in the device controller.

[0108] The frame linked list in the embodiment of the present invention can reasonably arrange the order and type of data transmission through each pointer, and conveniently meet the requirements of the bus protocol for the data transmission time slice.

[0109] Optionally, the access controller 50 includes a plurality of transmission channels, a channel selection module, and a bus arbiter; each of the plurality of transmission channels has a channel number and a corresponding channel priority; the channel selection module is configured to open the transmission channel specified by the first control instruction according to the first control instruction sent by the device controller; wherein, the first control instruction includes the channel number of the transmission channel to be opened; the bus arbiter is configured to sort the transmission channels according to the channel number when the channel priorities of the plurality of transmission channels are the same, and control each transmission channel to perform data transmission according to the sorting order.

[0110] In an embodiment of the present invention, the access controller 50 may include multiple transmission channels of the storage device type. Software running on the chip or software running on the CPU of the computer device connected to the chip may set the priority of each transmission channel during chip initialization. The access controller in the embodiment of the present invention can support up to four levels of priority settings. After the channel selection module receives the first control instruction sent by the register related to the access controller in the device controller 10, first, the software running on the chip or the software running on the CPU of the computer device connected to the chip performs arbitration at the software stage to determine the priority of the transmission channel specified to be opened by the first control instruction, and opens the specified transmission channel according to the channel priority. In the case where the channel priorities of multiple transmission channels are the same during the arbitration at the software stage, the bus arbiter may sort the transmission channels with the same priority according to the channel numbers, determine that the transmission channel with a lower number has a higher transmission priority than the transmission channel with a higher number, and control each transmission channel to perform data transmission according to the sorting order.

[0111] For example, the access controller 50 in the embodiment of the present invention may be a DMA controller. The DMA controller may include 8 DMA transmission channels of the memory-device type. Software running on the chip or software running on the CPU of the computer device connected to the chip may control the channel selection module to open the specified transmission channel through the DMA-related registers given by the USB device controller. The bus arbiter may preferentially transmit the data of the specified transmission channel according to the priority of the DMA transmission request.

[0112] It should be noted that to meet the requirements of USB data bandwidth and service response speed, the chip in the embodiment of the present invention includes DMA control logic for transmitting data between the hardware FIFO corresponding to the USB device and the memory. The DMA controller may be directly connected to the 32-bit Advanced High Performance Bus (AHB) and support access to all 4G bus addresses. It should be noted that the number of FIFOs used in real time in the software service may be greater than the number of DMA transmission channels. Therefore, the software running on the chip or the software running on the CPU of the computer device connected to the chip may re-initiate the DMA transmission request when the transmission channel application fails.

[0113] In an embodiment of the present invention, the access controller 50 can conveniently control the data transmission in multiple transmission channels through the channel selection module and the bus arbiter, reasonably arrange the data transmission order on the bus according to the numbers and priorities of each transmission channel, and provide hardware support for improving the overall transmission efficiency of the chip.

[0114] Figure 6It is a schematic diagram of the DMA control logic according to an embodiment of the present invention. As Figure 6 shown, the DMA controller includes a plurality of transmission channels, a channel selection module, and a bus arbiter. The plurality of transmission channels of the DMA controller can be connected to a plurality of FIFOs. The registers related to the DMA controller in the device controller can be connected to the channel selection module and the bus arbiter. The channel selection module can open a specified transmission channel according to the first control instruction sent by the device controller. After receiving the control instruction for hardware arbitration, the bus arbiter can sort the transmission channels with the same priority according to the channel numbers, determine that the transmission channel with a lower number has a higher transmission priority than the transmission channel with a higher number, and control each transmission channel to perform data transmission through the channel selection module according to the sorted order, so that the DMA controller can perform data transmission between the FIFO and the memory of the external device of the chip under the control of the device controller.

[0115] Optionally, the first buffer 40 includes a routing logic module, a shared transmission buffer, and a dedicated transmission buffer; the routing logic module is configured to parse the packet type of the data sent by the bus device 30, and filter the packets that do not meet the preset regulations to determine that the data sent by the bus device 30 is the first data that meets the first latency requirement or the second data that meets the second latency requirement; the shared transmission buffer is configured to receive the first data routed by the routing logic module, and send the first data to the hub 20 under the control of the access controller 50; the dedicated transmission buffer is configured to receive the second data routed by the routing logic module, and send the second data to the hub 20 under the control of the access controller 50.

[0116] The routing logic module according to the embodiment of the present invention can parse the packet type of the data sent by the bus device 30, and can also filter illegal packets by judging the packet type. Among them, the packet type includes four transmission types: control transmission, synchronous transmission, interrupt transmission, and bulk transmission. Among them, the packets of the control transmission and bulk transmission types have low requirements for latency during transmission. The data sent by the bus device 30 with low requirements for latency, that is, the data that meets the first latency requirement, can be determined as the first data, and the first data is transmitted by the shared transmission buffer. Among them, the packets of the synchronous transmission and interrupt transmission types have high requirements for latency during transmission. The data sent by the bus device 30 with high requirements for latency, that is, the data that meets the second latency requirement, can be determined as the second data, and the second data is transmitted by the dedicated transmission buffer.

[0117] For example, if the first buffer 40 is a FIFO memory, the first buffer 40 may include a FIFO routing logic module, a shared transfer FIFO, and a dedicated transfer FIFO. Optionally, software running on the chip or software running on the CPU of a computer device connected to the chip can set parameters such as the type, size, and trigger threshold of the FIFO interrupt of this part of the FIFO through the registers related to the FIFO in the USB device manager.

[0118] The first buffer 40 of the embodiment of the present invention can conveniently parse the data packet type, filter data packets that do not meet the preset regulations, and reasonably select the shared transfer buffer and the dedicated transfer buffer to transmit the corresponding data according to the type of the data packet through the routing logic module, the shared transfer buffer, and the dedicated transfer buffer, so that the chip of the embodiment of the present invention can meet the requirements of the bus protocol for the data transfer type, can carry the transmission of data packets of multiple service types, and make full use of the bandwidth.

[0119] It should be noted that the device manager 10 of the embodiment of the present invention can support an automatic retry mechanism when the data packet sending fails. The USB device controller hardware supports verifying the number of bytes of each frame of complete data driven onto the bus. When the actual number of frame data bytes does not match, the data corresponding to the current frame in the data linked list will not be deleted from the linked list, but the data in the frame linked list will be cleared. At the same time, the software layer driver is notified through the status register, and the driver adds this frame of data back to the scheduling queue and, at a subsequent appropriate time point, reorganizes a new frame of data, that is, updates the frame linked list. The device manager 10 of the embodiment of the present invention can also support the USB remote wake-up function, and the remote wake-up function can be used when binding the HID human-computer interaction interface. When the USB bus is idle and the USB host controller enters the suspend state, a remote keyboard or mouse can wake up the USB host controller through the remote wake-up function, causing the host controller to resume from the suspend state to the standby state.

[0120] Figure 7 is a structural diagram of another resource management chip according to an embodiment of the present invention, as Figure 7As shown in the figure, the chip includes a USB device controller, a USB hub, a USB device, a DMA controller scheduler, a FIFO routing logic module of a first buffer, a shared transfer FIFO, and a dedicated transfer FIFO, a frame linked list and a data linked list of the USB hub. Among them, the USB device controller includes a DMA controller register, a control and status register, and a FIFO control register. The USB device includes a plurality of second ports 1 to X, and the USB hub includes a plurality of ports 0 to X and a plurality of first endpoints 1 to X. Among them, the frame linked list and the data linked list are in the second buffer of the USB hub. In the resource management chip of the embodiment of the present invention, it may be a PCB circuit board. The device controller connects the DMA controller register to the DMA controller through the circuit on the chip, connects the control and status register to the USB device and the USB hub, and connects the FIFO control register to the first buffer and the second buffer in the USB hub. The USB hub can establish communication connections with each data buffer in the data linked list through a plurality of second endpoints respectively. The pointer of the frame linked list points to a data in the data linked list.

[0121] It should be noted that the resource management chip of the present invention can obtain the effect of dynamically applying for and releasing USB resources through dynamically configurable USB interfaces and endpoints, so as to solve the problem that the resources of USB physical devices are solidified and cannot be flexibly configured according to the product requirements. At the same time, the resource management chip of the present invention provides a chip-level USB resource set, provides hardware support for the cooperation between on-chip USB devices, and improves the overall transmission efficiency of the USB bus and devices based on the FIFO hardware and software driver algorithms. On this basis, the USB resource pool based on the FPGA chip adopts a modular design, has good scalability, can cut the USB resources on the FPGA chip according to the specific project product requirements, flexibly set the total USB resource amount and various USB resource combinations, so that the USB resources are sufficient and not wasted.

[0122] Figure 8 It is a step flowchart of a resource management method provided by an embodiment of the present invention, as Figure 8 shown, a resource management method, applied to the chip described above, the method includes:

[0123] Step 601, send a resource acquisition instruction to the device controller, control the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding hub port and a first endpoint for the bus device.

[0124] Step 602, control the bus device to receive the data through the device controller, and send the data to the corresponding first buffer through the second endpoint.

[0125] Step 603: Control, by the device controller, the first buffer to receive and store the data sent by the bus device.

[0126] Step 604: Send, by the device controller, a control instruction to the access controller, and control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub to receive the data through the first endpoint and output the data to the outside of the chip.

[0127] In an embodiment of the present invention, a resource management program running on the chip may send a resource acquisition instruction to the device controller, and the device manager allocates a bus device for receiving data according to the data transmission requirements indicated by the resource acquisition instruction, and configures a corresponding hub port and a first endpoint for the bus device. The bus device and the hub form an analog "insertion" action through the port to establish an actual communication connection. The bus device can access the hub through the port, and the first endpoint of the hub can receive the data sent by the bus device. For example, the resource management program may send a serial port transmission resource acquisition instruction to the device controller to control the device controller to allocate a bus device for receiving serial port logs, and configure a corresponding hub port and a first endpoint for the bus device.

[0128] In an embodiment of the present invention, a resource management program running on the chip may control the bus device and the hub to transmit data between a remote client and an external device of the chip through the device manager, so as to realize remote access of the remote client to the external device of the chip. Among them, the local CPU sends a URB data packet to the resource management chip of the embodiment of the present invention through a USB cable and a USB protocol stack. The resource management program may drive the bus device and the hub to receive the URB data packet through the device manager, and send the URB data packet to the resource management program. The resource management program is responsible for parsing the URB data packet and repackaging it into a network data packet, and transmitting it to the remote client through a network protocol stack and a network path. After the resource management program receives the network data packet sent by the remote client, various drivers and protocol stacks running on the chip perform parsing and repackaging, and give the raw data to the resource management chip of the embodiment of the present invention. The resource management chip then repackages it into a URB data packet. The resource management program may drive the bus device and the hub to send the URB data packet to the local CPU of the external device of the chip through a USB cable and a USB protocol stack through the device manager.

[0129] In an embodiment of the present invention, by sending a resource acquisition instruction to a device controller, the device controller is controlled to allocate a bus device for receiving data according to the resource acquisition instruction, and a corresponding hub port and a first endpoint are configured for the bus device. The chip resources can be flexibly configured through the device controller according to requirements to implement various different functions. The bus device is controlled by the device controller to receive the data, and the data is sent to a corresponding first buffer through a second endpoint; the first buffer is controlled by the device controller to receive and store the data sent by the bus device; a control instruction is sent by the device controller to an access controller to control the access controller to control the first buffer to send the data to the hub according to the control instruction, and to control the hub to receive the data through the first endpoint and output the data to the outside of the chip. In this way, multiple bus devices, multiple ports of the hub, and multiple first endpoints in the chip can be better coordinated, and the overall data transmission efficiency of the chip can be improved.

[0130] Optionally, the resource acquisition instruction is generated according to a remote access instruction sent by a remote client to an external device of the chip; in the case where the remote access instruction indicates that the remote client sends data to the external device, before sending the resource acquisition instruction to the device controller, the method further includes:

[0131] Step 605, receiving a remote data packet sent by the remote client through a resource management program running on the chip.

[0132] Step 606, sending the remote data packet to a data transmission program running on the chip through the resource management program for parsing and processing to obtain a first data packet.

[0133] Step 601 includes the following steps:

[0134] Step 6011, the resource management program sends a resource acquisition instruction to the device controller through a chip driver program running on the chip, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configures a corresponding hub port and a first endpoint for the bus device.

[0135] Step 604 includes the following steps:

[0136] Step 6041, sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and transmit the data to the external device to implement remote access of the remote client to the external device.

[0137] In an embodiment of the present invention, a resource management program running on a chip may receive a remote access instruction sent by a remote client and generate a resource acquisition instruction according to the remote access instruction. Among them, the remote access instruction may include user security level verification, dynamic adjustment of device resources, and encrypted file transmission. Here, this is only an example, and the embodiments of the present invention do not limit this. Among them, the dynamic adjustment of device resources includes specifying the insertion or removal of a device and adjusting the parameters of a specified device. For example, the resource management program receives a client request sent by a remote personal computer (PC) in the role of a server, requesting access to the serial port log of the server.

[0138] In an embodiment of the present invention, when the remote access instruction indicates that the remote client sends data to an external device, the resource management program receives a remote data packet sent by the remote client, and the data transmission program running on the chip parses and repackages the remote data packet to obtain a first data packet. The resource management program may send a resource acquisition instruction to the device controller through a chip driver program running on the chip, control the device controller to allocate a bus device for receiving data, and configure a corresponding hub port and a first endpoint for the bus device. The bus device receives the first data packet sent by the resource management program under the control of the device controller and sends the first data packet to a first buffer for storage through a second endpoint. Among them, the chip driver program includes a device manager driver.

[0139] In an embodiment of the present invention, the resource management program may control the device manager through the device manager driver and send a first data transmission instruction to the access controller. After receiving the first data transmission instruction, the access controller controls the first buffer to send the first data packet to the hub according to the first data transmission instruction. The hub receives the first data packet sent by the first buffer through the first endpoint and stores the first data packet in a second buffer. Under the control of the access controller, the hub sends the first data packet to the local central processor of the external device through the data linked list and the frame linked list in the second buffer to implement the remote access of the remote client to the external device.

[0140] In an embodiment of the present invention, when the remote access instruction indicates that the remote client sends data to an external device, the data sent by the remote client can be conveniently sent to the external device of the chip through the allocated bus device and the port and the first endpoint of the hub. In addition, the access controller can improve the data transmission efficiency of the chip by controlling the first buffer and the hub, so that the remote client obtains a better access effect.

[0141] Optionally, when the remote access instruction indicates that the external device sends data to the remote client, step 601 may further include the following steps:

[0142] Step 6012: The resource management program sends a resource acquisition instruction to the device controller through the chip driver, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configures a corresponding hub port and a first endpoint for the bus device.

[0143] Step 602 may include the following steps:

[0144] Step 6021: Control the bus device through the device controller to receive the local data packet sent by the local central processor of the external device, and send the local data packet to the corresponding first buffer for storage through the second endpoint.

[0145] Step 604 may further include the following steps:

[0146] Step 6042: Send a control instruction to the access controller through the device controller, control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub to receive the data through the first endpoint and transmit the data to the data transmission program.

[0147] After step 6042, the method further includes:

[0148] Step 607: Parse and process the local data packet through the data transmission program to obtain a second data packet, and send the second data packet to the resource management program.

[0149] Step 608: Send the second data packet to the remote client through the resource management program to implement remote access of the remote client to the external device.

[0150] In the embodiment of the present invention, when the remote access instruction indicates that the external device sends data to the remote client, the resource management program may send a resource acquisition instruction to the device controller through the chip driver, control the device controller to allocate a bus device for receiving data, and configure a corresponding hub port and a first endpoint for the bus device. The bus device receives the local data packet sent by the local central processor of the external device to the resource management chip under the control of the device controller, and sends the local data packet to the first buffer for storage through the second endpoint.

[0151] In an embodiment of the present invention, the resource management program can drive and control the device manager through the device manager driver, and send a second data transmission instruction to the access controller. After receiving the second data transmission instruction, the access controller controls the first buffer to send the local data packet to the hub according to the second data transmission instruction. The hub receives the local data packet sent by the first buffer through the first endpoint, and stores the local data packet in the second buffer. Under the control of the access controller, the hub sends the local data packet to the data transmission program through the data linked list and the frame linked list in the second buffer. The data transmission program is responsible for parsing the local data packet and repackaging it into a network data packet, and transmitting it to the remote client through the network protocol stack and the network path under the control of the resource management program, so as to realize the remote access of the remote client to the external device.

[0152] In an embodiment of the present invention, when the remote access instruction indicates that the external device sends data to the remote client, the data sent by the external device of the chip can be conveniently sent to the remote client through the allocated bus device, the port and the first endpoint of the hub. In addition, the access controller can improve the data transmission efficiency of the chip by controlling the first buffer and the hub, so that the remote client obtains a better access effect.

[0153] Figure 9 is a schematic diagram of remote access of a server or a switch according to an embodiment of the present invention, as Figure 9As shown in the figure, the remote access function is generally divided into three parts. The left part corresponds to the server or switch to be remotely accessed. From top to bottom, they are the USB customized user program in the user space, the USB device driver, the USB core layer, and the USB host controller driver in the kernel space, as well as the CPU hardware entity of the board-level hardware, where the CPU includes the USB host controller. The middle part, from bottom to top, is the USB IP and network IP implemented inside the FPGA chip, the USB function driver, the USB abstraction layer, the USB control driver in the Linux kernel running on the FPGA, the network card, and the USB resource management program in the user space. The right side is the remote PC accessing the server or switch. The management and scheduling of the remote access function are responsible for the USB resource management program running on the FPGA. The main functions of the USB resource management program are described as follows: First, acting as a server, it receives client requests from the remote PC, including user security level verification, dynamic adjustment of specified USB resources, file encrypted transmission, etc. Second, it forwards the interaction data between the local CPU and the remote PC to achieve access to the local server or switch by the remote PC. Among them, the local CPU sends URB data packets to it through the USB cable and the USB protocol stack. The USB resource management program is responsible for parsing the URB data packets and repackaging them into network data packets, which are transmitted to the remote client through the network protocol stack and the network path. The hardware support for the remote access function comes from the USB IP implemented inside the FPGA. The Linux kernel running on the FPGA includes various driver programs corresponding to the USB IP inside the FPGA, the USB IP resource management program exposed to the USB resource management program, and the transmission program for passing through the interaction data between the remote PC and the local CPU.

[0154] It should be noted that in the prior art, the remote access of servers or switches, as well as the USB resource pool shared among different virtual machines on the same physical device, both belong to application scenarios that require multiple USB resources and support dynamic configuration of USB resources. In network infrastructure devices such as servers and switches, supporting remote monitoring and debugging is an essential function item. Remote clients can, through the network, capture the serial port log output of the server on-site, capture the real-time screen of the on-site device monitor, and can also operate the on-site device in real time through the local mouse and keyboard of the server, just as if operating locally. The realization of remote access depends on multiple USB resources inside the server or switch device, and it is preferable that these USB resources support dynamic resource configuration. For example, when the server only wants to interact with remote devices through the serial port, it only needs to load the USB communication device (Communications Device Class, CDC) resources. Another example is that when the server has no need for remote monitoring devices, it can unload all USB resources to meet the possible USB function requirements of the device itself.

[0155] It should be noted that in the prior art, to solve the problem of large investment in hardware devices, virtual machine rental services have emerged. Different virtual machines with different performance configurations can be rented according to business needs, and behind the virtual machines, real hardware resources are supporting. The difference is that a traditional set of hardware resource configurations, such as CPU, memory, hard disk, peripherals, etc., are only allocated to one operating system for management and use, while virtual machines are multiple operating systems sharing a set of hardware resource configurations. For example, if a physical hardware contains 512G of memory, it can support 16 virtual machines with 32G of memory running simultaneously. And as a part of the hardware resources, the diversity and dynamic configuration of USB resources also become an essential function item in this application scenario. It should be noted that the USB resource management program running on the FPGA and the associated management program and transmission program in the kernel space are unique to the remote access function of the server or switch. In the application scenario of virtual machine sharing the USB resource pool, this part of the functional logic can be responsible for by the software running on the CPU.

[0156] Thirdly, the present invention provides an electronic device 70, as Figure 10 shown, including the resource management chip 701 described in any one of the above.

[0157] Fourthly, the present invention provides a readable storage medium. When the instructions in the storage medium are executed by the chip of the electronic device, the electronic device can execute the resource management method described in any one of the above.

[0158] For method embodiments, since they are basically similar to the chip embodiments, they are described relatively simply. For related parts, refer to the corresponding descriptions in the chip embodiments.

[0159] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Based on the above description, the structures required to construct such systems are obvious. In addition, the present invention is not directed to any particular programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the descriptions of specific languages above are for disclosing the best implementation manners of the present invention.

[0160] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0161] Similarly, it should be understood that, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed methods should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all of the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0162] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from those in the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted for all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature providing the same, equivalent, or similar purpose.

[0163] Each component embodiment of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0164] It should be noted that the above embodiments illustrate rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

[0165] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0166] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

[0167] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present invention and should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

[0168] It should be noted that in the embodiments of this application, all processes related to obtaining various data are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device.

Claims

1. A resource management chip, characterized in that, The chip includes: a device controller, a hub, a plurality of bus devices, a plurality of first buffers, and an access controller; The hub includes a plurality of ports and a plurality of first endpoints; The device controller is configured to receive a resource acquisition instruction, and allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding port and first endpoint for the bus device; wherein, the bus device accesses the hub through the port; the device controller includes a first register, a second register, and a third register; the first register is configured to query the current states of the bus devices and the hub, and set the bus device for receiving data, the port and first endpoint corresponding to the bus device according to the resource acquisition instruction; the second register is configured to send a first control instruction to the access controller, so that the access controller opens a specified data transmission channel according to the first control instruction; the third register is configured to set a corresponding first buffer for each bus device respectively, and query the current states of the first buffers; The bus device includes a plurality of second endpoints; the bus device is configured to send the received data to a corresponding first buffer through the second endpoints; The first buffer is configured to store the data, and send the data to the hub under the control of the access controller; The hub is configured to receive the data through the first endpoints, and output the data to the outside of the chip under the control of the access controller; the hub further includes a first control endpoint and a second buffer; the first control endpoint is configured to control, under the control of the first register, the first endpoints to receive the data sent by the first buffer, and send the data to the second buffer for storage through the first endpoints; the second buffer is configured to receive and store the data sent by the first endpoints, and send the data to the outside of the chip according to a second control instruction sent by the access controller; The access controller is configured to receive the control instruction sent by the device controller, and control data transmission between the first buffer and the hub, and between the hub and the outside of the chip according to the control instruction.

2. The chip according to claim 1, characterized in that, The bus device includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoints are arranged in the first interface; The second control endpoint is configured to control, under the control of the first register, the second endpoints to receive data, and send the data to a corresponding first buffer; The first register is further configured to set the data transmission type of the first interface according to the resource acquisition instruction, so that the first interface receives data of the data transmission type through the second endpoints; wherein, the data transmission type is any one of a video control type, a video transmission type, a serial port transmission type, a network transmission type, and a human-computer interaction type.

3. The chip according to claim 1, characterized in that, The second buffer includes a frame linked list and a data linked list; The data linked list is used to cache the data sent by the bus device to the hub through the first buffer; The frame linked list is used to determine the data to be transmitted by the hub currently, and send the data to be transmitted to the outside of the chip according to the second control instruction.

4. The chip according to claim 1, characterized in that, The access controller includes a plurality of transmission channels, a channel selection module and a bus arbiter; Each of the plurality of transmission channels has a channel number and a corresponding channel priority; The channel selection module is used to open the transmission channel specified by the first control instruction according to the first control instruction sent by the device controller; wherein, the first control instruction includes the channel number of the transmission channel to be opened; The bus arbiter is used to sort the transmission channels according to the channel numbers when the channel priorities of the plurality of transmission channels are the same, and control the transmission channels to perform data transmission according to the sorting order.

5. The chip according to claim 1, characterized in that, The first buffer includes a routing logic module, a shared transmission buffer and a dedicated transmission buffer; The routing logic module is used to parse the data packet type of the data sent by the bus device, and filter the data packets that do not meet the preset regulations, so as to determine that the data sent by the bus device is the first data that meets the first delay requirement or the second data that meets the second delay requirement; The shared transmission buffer is used to receive the first data routed by the routing logic module, and send the first data to the hub under the control of the access controller; The dedicated transmission buffer is used to receive the second data routed by the routing logic module, and send the second data to the hub under the control of the access controller.

6. A resource management method, characterized in that, Applied to the chip according to any one of claims 1-5, the method includes: Sending a resource acquisition instruction to the device controller, controlling the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configuring a corresponding port and a first endpoint of the hub for the bus device; Controlling the bus device to receive the data through the device controller, and sending the data to the corresponding first buffer through the second endpoint; Controlling the first buffer to receive and store the data sent by the bus device through the device controller; Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through the first endpoint and output the data to the outside of the chip.

7. An electronic device, characterized in that, Including the resource management chip according to any one of claims 1-5.

8. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the chip of the electronic device, the electronic device can execute the resource management method according to claim 6.

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