Shift register and gate drive circuit

Abstract

The present disclosure provides a shift register and a gate drive circuit, belonging to the technical field of display, which can solve the problem of long leakage time of the first node in the existing shift register, affecting the dimming effect. The shift register of the present disclosure comprises an input unit, a voltage adjusting unit, a cascade unit, an output unit and a reset unit; the input unit is configured to charge the first node with the first level signal in response to the first clock signal and the start voltage signal; the first node is the connection point between the input unit, the voltage adjusting unit, the cascade unit, the output unit and the reset unit; the reset unit is configured to reset the voltage of the first node with the reset clock signal in response to the reset signal; the reset clock signal is a periodically changing pulse modulation signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register and a gate driving circuit. Background Technology

[0002] The EM GOA (Emitting Light Controlled Gate) circuit is a negative pulse width modulation (NPWM) model, where the NPWM pulse width is modulated by the startup voltage waveform. Typically, when data is written, the EM GOA output is low; when the light-emitting device emits light, the EM GOA output is high. A traditional EM GOA circuit (its structure is as follows) Figure 3 In the diagram, the gate of the transistor used for reset is the reset signal, the source is connected to the first node Q, and the drain is connected to a DC high-level signal. Normally, the low-level output of the light-emitting control signal lasts for approximately tens of microseconds, a short period, so the leakage of the high-level signal through the reset transistor to the first node Q has a relatively small impact. However, when the display panel displays a low-frequency or low-grayscale display and requires pulse width modulation (PWM) for dimming to improve the low-grayscale display effect, the overall low-level output time of EMGOA becomes longer. This increases the leakage time of the high-level signal through the reset transistor to the first node Q, raising the voltage of the first node Q and pulling down the voltage of the second node QB. Consequently, the voltage of the light-emitting control signal at the signal output terminal is raised, affecting the dimming effect. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art by providing a shift register and gate drive circuit.

[0004] In a first aspect, embodiments of this disclosure provide a shift register, which includes: an input unit, a voltage adjustment unit, a cascade unit, an output unit, and a reset unit;

[0005] The input unit is configured to charge the first node using a first level signal in response to a first clock signal and a start voltage signal; the first node is the connection point between the input unit, the voltage regulation unit, the cascade unit, the output unit, and the reset unit.

[0006] The voltage regulation unit is configured to adjust the voltage of the first node and the second node in response to a first clock signal, a second clock signal, and a start voltage signal, using a first level signal and a second level signal; the second node is the connection point between the voltage regulation unit, the cascaded unit, and the output unit.

[0007] The cascade unit is configured to input a first-level signal to the cascade signal terminal in response to the voltage of the first node, and to input a second-level signal to the cascade signal terminal in response to the voltage of the second node;

[0008] The output unit is configured to input a first-level signal to a signal output terminal in response to the voltage of the first node, and to input a second-level signal to a signal output terminal in response to the voltage of the second node;

[0009] The reset unit is configured to reset the voltage of the first node in response to a reset signal using a reset clock signal; the reset clock signal is a periodically changing pulse modulation signal.

[0010] Optionally, the duty cycle of the reset clock signal is 40% to 60%.

[0011] Optionally, the voltage regulation unit includes: a first node discharge unit, a second node pre-charge unit, a second node discharge unit, and a third node charge / discharge unit;

[0012] The first node discharge unit is configured to discharge the first node using a second level signal in response to a first clock signal and the voltage of the third node; the third node is the connection point between the first node discharge unit, the second node pre-charge unit, and the third node charge / discharge unit.

[0013] The second node precharge unit is configured to precharge the second node in response to the first clock signal and the voltage of the third node using the first clock signal;

[0014] The second node discharge unit is configured to discharge the second node using a second level signal in response to the voltage of the first node;

[0015] The third node charging and discharging unit is configured to charge the third node using a first level signal in response to a second clock signal, and to discharge the third node using a second clock signal in response to a start-up voltage signal.

[0016] Optionally, the input unit includes: a first transistor and a second transistor;

[0017] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the second transistor.

[0018] The control electrode of the second transistor is connected to the startup voltage terminal, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

[0019] Optionally, the cascaded unit includes: a fourteenth transistor and a fifteenth transistor;

[0020] The control electrode of the fourteenth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the cascaded signal terminal.

[0021] The control electrode of the fifteenth transistor is connected to the second node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the cascaded signal terminal.

[0022] Optionally, the output unit includes: a sixteenth transistor, a seventeenth transistor, a sub-seventeenth transistor, a first storage capacitor, and a second storage capacitor;

[0023] The control electrode of the sixteenth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the signal output terminal.

[0024] The control electrode of the seventeenth transistor is connected to the second node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first electrode of the seventeenth transistor.

[0025] The control electrode of the seventeenth transistor is connected to the second node, the first electrode is connected to the second electrode of the seventeenth transistor, and the second electrode is connected to the signal output terminal;

[0026] One end of the first storage capacitor is connected to the first node, and the other end is connected to the signal output terminal;

[0027] One end of the second storage capacitor is connected to the second node, and the other end is connected to the second level signal terminal.

[0028] Optionally, the reset unit includes: a twelfth transistor;

[0029] The control electrode of the twelfth transistor is connected to the reset signal terminal, the first electrode is connected to the reset clock signal terminal, and the second electrode is connected to the first node.

[0030] Optionally, the first node discharge unit includes: a tenth transistor and an eleventh transistor;

[0031] The control electrode of the tenth transistor is connected to the third node, the first electrode is connected to the second electrode of the eleventh transistor, and the second electrode is connected to the first node;

[0032] The control electrode of the eleventh transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first electrode of the tenth transistor.

[0033] Optionally, the second node precharge unit includes: a seventh transistor, an eighth transistor, and a third storage capacitor;

[0034] The control electrode of the seventh transistor is connected to the third node, the first electrode is connected to the first clock signal terminal, and the second electrode is connected to the first electrode of the eighth transistor and the other end of the third storage capacitor.

[0035] The control terminal of the eighth transistor is connected to the first clock signal terminal, the first terminal is connected to the second terminal of the seventh transistor and the other end of the third storage capacitor, and the second terminal is connected to the second node.

[0036] One end of the third storage capacitor is connected to the third node, and the other end is connected to the second terminal of the seventh transistor and the first terminal of the eighth transistor.

[0037] Optionally, the second node discharge unit includes: a ninth transistor;

[0038] The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second node.

[0039] Optionally, the third node charging and discharging unit includes: a third transistor, a fourth transistor, and a fifth transistor;

[0040] The control electrode of the third transistor is connected to the second clock signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the third node.

[0041] The control electrode of the fourth transistor is connected to the start-up voltage terminal, the first electrode is connected to the second electrode of the fifth transistor, and the second electrode is connected to the third node;

[0042] The control electrode of the fifth transistor is connected to the startup voltage terminal, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the first electrode of the fourth transistor.

[0043] Optionally, the shift register further includes: a first leakage protection unit, a second leakage protection unit, and a third leakage protection unit;

[0044] The first leakage protection unit includes: a thirteenth transistor; the control electrode of the thirteenth transistor is connected to a first level signal terminal, the first electrode is connected to a first node, and the second electrode is connected to the cascaded unit and the output unit;

[0045] The second leakage protection unit includes: an eighteenth transistor; the control electrode of the eighteenth transistor is connected to the signal output terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the signal output unit;

[0046] The third leakage protection unit includes a sixth transistor; the control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the charging and discharging unit of the third node.

[0047] In a second aspect, embodiments of this disclosure provide a gate driving circuit, the gate driving circuit including the shift register as described above;

[0048] The start voltage terminal of this stage shift register is connected to the cascade signal terminal of the previous stage shift register;

[0049] The cascading signal terminal of this stage shift register is connected to the start voltage terminal of the next stage shift register.

[0050] Optionally, the signal at the reset clock signal terminal is provided by the reset clock signal line.

[0051] Optionally, the signal at the reset clock signal terminal is provided by the first clock signal line.

[0052] Thirdly, embodiments of this disclosure provide a display substrate, the display substrate including the gate driving circuit as described above. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of an exemplary pixel driving circuit.

[0054] Figure 2 for Figure 1 The timing diagram of the pixel driving circuit is shown.

[0055] Figure 3 This is a schematic diagram of an exemplary shift register.

[0056] Figure 4a for Figure 3 The diagram shows a simulation schematic of the gate drive circuit.

[0057] Figure 4b for Figure 3 Another simulation diagram of the gate drive circuit shown.

[0058] Figure 5 A shift register is provided for embodiments of this disclosure.

[0059] Figure 6 for Figure 5 The timing diagram of the shift register is shown.

[0060] Figure 7 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure.

[0061] Figure 8 This is a schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0062] Figure 9 for Figure 7The diagram shows a simulation schematic of the gate drive circuit.

[0063] Figure 10 for Figure 7 Another simulation diagram of the gate drive circuit shown.

[0064] Figure 11 for Figure 8 The diagram shows a simulation schematic of the gate drive circuit.

[0065] Figure 12 for Figure 8 Another simulation diagram of the gate drive circuit shown. Detailed Implementation

[0066] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0068] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example.

[0069] In this embodiment, the first level signal refers to a signal that, when input to the control electrode of a transistor, can control the transistor to conduct; the second level signal refers to a signal that, when input to the control electrode of a transistor, can control the transistor to cut off. For an N-type transistor, a high-level signal is the first level signal, and a low-level signal is the second level signal; for a P-type transistor, the opposite is true.

[0070] In the following description, an N-type transistor will be used as an example. In this case, the first level signal refers to a high-level signal, and the second level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signals needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0071] Figure 1 This is a schematic diagram of an exemplary pixel driving circuit, such as... Figure 1 As shown, the pixel circuit includes: a data writing transistor M1, a reset transistor M2, an initialization transistor M3, a light-emitting control transistor M4, a driving transistor M5, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0072] The gate of data writing transistor M1 is connected to the first scan terminal G1, the source is connected to the data signal terminal Data, and the drain is connected to node G. The gate of reset transistor M2 is connected to the second scan signal terminal G2, the source is connected to the reset signal terminal Vref, and the drain is connected to the gate of driving transistor M5. The gate of initialization transistor M3 is connected to the third scan signal terminal G3, the source is connected to the initialization signal terminal Vini, and the drain is connected to the source of driving transistor M5 and the anode of light-emitting device D. The gate of light-emitting control transistor M4 is connected to the light-emitting control signal terminal EM, the source is connected to the first power supply voltage terminal ELVDD, and the drain is connected to the source of driving transistor M5. The gate of driving transistor M5 is connected to the drain of data writing transistor M1 and the drain of reset transistor M2, the source is connected to the drain of light-emitting control transistor M4, and the drain is connected to the anode of light-emitting device D. One end of the first storage capacitor Cst1 is connected to the gate of driving transistor M5, and the other end is connected to the drain of driving transistor M5. One end of the second storage capacitor Cst2 is connected to the anode of light-emitting device D, and the other end is connected to the cathode of light-emitting device D. The anode of the light-emitting device D is connected to the drain of the driving transistor M5, and the cathode is connected to the second power supply voltage terminal ELVSS.

[0073] Figure 2 for Figure 1 The timing diagram of the pixel driving circuit shown is as follows: Figure 2As shown, the entire timing sequence can be divided into a reset phase S1, an initialization phase S2, a data writing phase S3, and a light-emitting phase S4. The states of the transistors in each phase can be found in relevant technologies and will not be detailed here. In the light-emitting phase S4, dimming can be achieved using pulse width modulation (PWM). That is, the light-emitting control signal at the EM terminal is a pulse signal. By controlling the duty cycle of the light-emitting control signal, the light-emitting time of the light-emitting device D can be adjusted, thereby regulating the brightness of the light-emitting device D.

[0074] Figure 1 The light emission control signal in the pixel circuit shown can be provided by a gate driving circuit, which includes multiple cascaded shift registers. Figure 3 This is a schematic diagram of an exemplary shift register, such as... Figure 3 As shown, the shift register includes transistors T1 through T18, and their specific connection method and working principle will be described in detail later. The signal output terminal OUT of the shift register can be connected as follows: Figure 1 The EM terminal of the pixel driving circuit shown provides the light emission control signal to the pixel driving circuit. The twelfth transistor T12 can reset the voltage of the first node Q. Generally, the source of the twelfth transistor T12 can be connected to the high-level signal terminal VGH, and the voltage of the first node Q can be reset by a high-level signal.

[0075] Figure 4a for Figure 3 The diagram shown is a simulation schematic of the gate drive circuit. Figure 4b for Figure 3 Another simulation diagram of the gate drive circuit shown is as follows: Figure 4a and Figure 4b As shown, when dimming is performed using PWM, the low-level duration of the light emission control signal is relatively long. When the voltage of the first node Q is reset using the twelfth transistor T12, the time for the high-level signal to leak to the first node Q through the twelfth transistor T12 increases, the potential of the first node Q is raised, and the output light emission control signal is raised, resulting in instability of the light emission control signal and affecting the dimming effect.

[0076] To at least solve one of the above-mentioned technical problems, this disclosure provides a shift register and a gate driving circuit. The shift register and gate driving circuit provided in this disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0077] In a first aspect, embodiments of this disclosure provide a shift register, Figure 5 A shift register provided in an embodiment of this disclosure, such as Figure 5 As shown, the shift register includes: an input unit 101, a voltage adjustment unit, a cascaded unit 103, an output unit 104, and a reset unit 105; the input unit 101 is configured to charge the first node Q using a first level signal in response to a first clock signal and a start voltage signal; the first node Q is the connection point between the input unit 101, the voltage adjustment unit, the cascaded unit 103, the output unit 104, and the reset unit 105; the voltage adjustment unit is configured to adjust the voltage of the first node Q and the second node QB using the first level signal and the second level signal in response to the first clock signal, a second clock signal, and the start voltage signal. Voltage; cascade unit 103 is configured to input a first-level signal to the cascade signal terminal CR in response to the voltage of the first node Q1, and to input a second-level signal to the cascade signal terminal CR in response to the voltage of the second node QB; output unit 104 is configured to input a first-level signal to the signal output terminal OUT in response to the voltage of the first node Q, and to input a second-level signal to the signal output terminal OUT in response to the voltage of the second node QB; reset unit 105 is configured to reset the voltage of the first node Q in response to a reset signal using a reset clock signal; the reset clock signal is a periodically changing pulse modulation signal.

[0078] In the shift register provided in this embodiment, the reset unit 105 can reset the voltage of the first node Q by inputting a reset clock signal to the first node Q. The reset clock signal is a periodically changing pulse modulation signal, i.e., high-level and low-level signals alternate. Thus, the first node Q experiences high-level leakage during the high-level period of the reset clock signal and low-level leakage during the low-level period. However, in PWM dimming and low-frequency displays, the low-level maintenance time of the light emission control signal is relatively long. Low-level leakage has no effect on the light emission control signal, while high-level signals easily affect the stability of the light emission control signal. In the shift register provided in this embodiment, because the reset clock signal is a periodically changing pulse modulation signal, the high-level maintenance time is reduced. Compared to related technologies that use a constant high-level signal to reset the voltage of the first node Q, the high-level leakage time of the first node Q can be reduced. Therefore, the stability of the light emission control signal output at the signal output terminal OUT can be guaranteed, thereby improving the display effect of low-frequency or low-grayscale dimming displays.

[0079] In some embodiments, the duty cycle of the reset clock signal is 40% to 60%.

[0080] The duty cycle of the reset clock signal can be set according to actual needs. While avoiding prolonged leakage, it also ensures the effective reset of the first node Q, guaranteeing the impact of the current light-emitting control signal on the next frame of display. For example, a 40% duty cycle ensures that the first node Q does not experience high-level leakage for 60% of the frame's display time. A 50% duty cycle ensures that the first node Q does not experience high-level leakage for half of the frame's display time. Therefore, using a reset clock signal to reset the voltage of the first node Q significantly reduces the high-level leakage time, thus ensuring the stability of the light-emitting control signal output at the OUT terminal, thereby improving the display effect of low-frequency or low-grayscale dimming displays.

[0081] In some embodiments, such as Figure 5 As shown, the voltage regulation unit includes: a first node discharge unit 1021, a second node pre-charge unit 1022, a second node discharge unit 1023, and a third node charge / discharge unit 1024; the first node discharge unit 1021 is configured to discharge the first node Q using a low-level signal in response to a first clock signal and the voltage of the third node P; the third node P is the connection point between the first node discharge unit 1021, the second node pre-charge unit 1022, and the third node charge / discharge unit 1024; the second node pre-charge unit 1022 is configured to pre-charge the second node QB using the first clock signal in response to a first clock signal and the voltage of the third node P; the second node discharge unit 1023 is configured to discharge the second node QB using a low-level signal in response to the voltage of the first node Q; the third node charge / discharge unit 1024 is configured to charge the third node P using a high-level signal and discharge the third node P using a low-level signal in response to a start-up voltage signal and a second clock signal.

[0082] The input unit 101 includes: a first transistor T1 and a second transistor T2; the gate of the first transistor T1 is connected to the first clock signal terminal CLKA, the source is connected to the high-level signal terminal VGH, and the drain is connected to the source of the second transistor T2; the gate of the second transistor T2 is connected to the start-up voltage terminal STU, the source is connected to the drain of the first transistor T1, and the drain is connected to the first node Q.

[0083] The cascade unit 103 includes: a fourteenth transistor T14 and a fifteenth transistor T15; the gate of the fourteenth transistor T14 is connected to the first node Q, the source is connected to the high-level signal terminal VGH, and the drain is connected to the cascade signal terminal CR; the gate of the fifteenth transistor T15 is connected to the second node QB, the source is connected to the low-level signal terminal VGL, and the drain is connected to the cascade signal terminal CR.

[0084] The output unit 104 includes: a sixteenth transistor T16, a seventeenth transistor T17, a seventeenth transistor T17', a first storage capacitor C1, and a second storage capacitor C2; the gate of the sixteenth transistor T16 is connected to the first node Q, the source is connected to the high-level signal terminal VGH, and the drain is connected to the signal output terminal OUT; the gate of the seventeenth transistor T17 is connected to the second node QB, the source is connected to the low-level signal terminal VGL, and the drain is connected to the source of the seventeenth transistor T17'; the gate of the seventeenth transistor T17' is connected to the second node QB, the source is connected to the drain of the seventeenth transistor T17, and the drain is connected to the signal output terminal OUT; one end of the first storage capacitor C1 is connected to the first node Q, and the other end is connected to the signal output terminal OUT; one end of the second storage capacitor C2 is connected to the second node QB, and the other end is connected to the low-level signal terminal VGL.

[0085] The reset unit 105 includes: a twelfth transistor T12; the gate of the twelfth transistor T12 is connected to the reset signal terminal RST, the source is connected to the reset clock signal terminal CLKA1, and the drain is connected to the first node Q.

[0086] The first node discharge unit 1021 includes: a tenth transistor T10 and an eleventh transistor T11; the gate of the tenth transistor T10 is connected to the third node P, the source is connected to the drain of the eleventh transistor T11, and the drain is connected to the first node Q; the gate of the eleventh transistor T11 is connected to the first clock signal terminal CLKA, the source is connected to the second level signal terminal VGL, and the drain is connected to the source of the tenth transistor T10.

[0087] The second node precharge unit 1022 includes: a seventh transistor T7, an eighth transistor T8, and a third storage capacitor C3; the gate of the seventh transistor T7 is connected to the third node P, the source is connected to the first clock signal terminal CLKA, and the drain is connected to the source of the eighth transistor T8 and the other end of the third storage capacitor C3; the gate of the eighth transistor T8 is connected to the first clock signal terminal CLKA, the source is connected to the drain of the seventh transistor T7 and the other end of the third storage capacitor C3, and the drain is connected to the second node QB; one end of the third storage capacitor C3 is connected to the third node P, and the other end is connected to the drain of the seventh transistor T7 and the source of the eighth transistor T8.

[0088] The second node discharge unit 1023 includes: a ninth transistor; the gate of the ninth transistor is connected to the first node Q, the source is connected to the second level signal terminal VGL, and the drain is connected to the second node QB.

[0089] The third node charging / discharging unit 1024 includes: a third transistor T3, a fourth transistor T4, and a fifth transistor T5; the gate of the third transistor T3 is connected to the second clock signal terminal CLKB, the source is connected to the high-level signal terminal VGH, and the drain is connected to the third node P; the gate of the fourth transistor T4 is connected to the startup voltage terminal STU, the source is connected to the drain of the fifth transistor T5, and the drain is connected to the third node P; the gate of the fifth transistor T5 is connected to the startup voltage terminal STU, the source is connected to the second clock signal terminal CLKB, and the drain is connected to the source of the fourth transistor T4.

[0090] The shift register also includes: a first leakage protection unit, a second leakage protection unit, and a third leakage protection unit; the first leakage protection unit includes: a thirteenth transistor T13; the gate of the thirteenth transistor T13 is connected to the high-level signal terminal VGH, the source is connected to the first node Q, and the drain is connected to the cascaded unit 103 and the output unit 104; the second leakage protection unit includes: an eighteenth transistor T18; the gate of the eighteenth transistor T18 is connected to the signal output terminal OUT, the source is connected to the high-level signal terminal VGH, and the drain is connected to the signal output unit 104; the third leakage protection unit includes: a sixth transistor T6; the gate of the sixth transistor T6 is connected to the third node P, the source is connected to the first-level signal terminal VGH, and the drain is connected to the third node charging and discharging unit 1024.

[0091] Figure 6 for Figure 5 The timing diagram of the shift register shown is illustrated below. The working principle of the shift register provided in the embodiments of this disclosure will be described in further detail below with reference to the timing diagram.

[0092] When the reset signal arrives, the reset clock signal is high, and the first clock signal and the second clock signal are low. After the reset signal ends, the reset clock signal is a periodic pulse signal, and the first clock signal and the second clock signal are periodic pulse signals with 25% overlap.

[0093] In the first stage, when the reset signal arrives, the twelfth transistor T12, the ninth transistor T9, the thirteenth transistor T13, the fourteenth transistor T14, and the sixteenth transistor T16 are turned on. The first node Q is reset by the reset clock signal, the voltage of the second node QB is pulled low, and the signal output terminal OUT outputs a high-level signal.

[0094] In the second stage, when the startup voltage is low, the third transistor T3 turns on when the high-level signal of the second clock signal arrives, the voltage of the third node P is high, and the tenth transistor T10 turns on.

[0095] In the third stage, when the high-level signal of the first clock signal arrives, the eighth transistor T8 and the eleventh transistor T11 turn on. The voltage of the third node P is further increased due to the capacitor bootstrap. The first node Q is discharged and the second node QB is charged. The fifteenth transistor T15, the seventeenth transistor T17 and the sub-seventeenth transistor T17' turn on, and the signal output terminal OUT outputs a low-level signal.

[0096] In the fourth stage, when the start-up voltage signal is high, the fourth transistor T4 and the fifth transistor T5 are turned on, and the third node P discharges through the second clock signal. When the high-level signal of the first clock signal arrives, the first transistor T1 and the second transistor T2 are turned on, the first node Q is charged, and the signal output terminal OUT outputs a high-level signal.

[0097] Secondly, embodiments of this disclosure provide a gate driving circuit, which includes a shift register as provided in any of the above embodiments; the start-up voltage terminal STU of the current shift register is connected to the cascade signal terminal CR of the previous shift register; the cascade signal terminal CR of the current shift register is connected to the start-up voltage terminal STU of the next shift register. Figure 7 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure. Figure 8 This is a schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0098] In one feasible way, such as Figure 7 As shown, the reset clock signal can be provided by a separate reset clock signal line.

[0099] Within one frame, when the negative pulse output time is relatively long, the high-level signal leaks to the first node Q through the twelfth transistor T12, increasing the leakage time. This pulls down the voltage of the second node QB, and the signal output from the signal output terminal OUT is boosted. The signal simulation diagram using the shift register provided in this embodiment is as follows: Figure 9 As shown, because it is a pulse-modulated waveform, compared with a DC high-level signal, the leakage time of the first node Q is significantly shortened, and the voltage of the second node QB will not be pulled down.

[0100] When the display panel has high requirements for low grayscale display, and PWM dimming is used to improve the low grayscale display effect, that is, a larger pixel drive current is used during the light-emitting phase. Theoretically, the overall brightness of the display panel will be higher. At this time, dimming is combined with the light-emitting control signal, that is, the display brightness of the display panel is adjusted by controlling the length of the light-emitting time. During the light-emitting phase, the light-emitting control signal is a signal that alternates between multiple switching. When the light-emitting control signal output is low, the high-level signal increases the leakage time to the first node Q through the twelfth transistor T12, pulls the second node QB low, and the signal at the signal output terminal is boosted. The signal simulation diagram of the shift register provided in this embodiment is as follows. Figure 10 As shown, because it is a pulse-modulated waveform, compared with a DC high-level signal, the leakage time of the first node Q is significantly shortened, and the voltage of the second node QB will not be pulled down.

[0101] In another possible way, such as Figure 8 As shown, the reset clock signal is provided by the first clock signal line. Figure 8 The gate drive circuit shown is compared to Figure 7 The gate drive circuit shown has one less signal line, which saves on the frame.

[0102] Within one frame, when the negative pulse output time is relatively long, the high-level signal leaks to the first node Q through the twelfth transistor T12, increasing the leakage time. This pulls down the voltage of the second node QB, and the signal output from the signal output terminal OUT is boosted. The signal simulation diagram using the shift register provided in this embodiment is as follows: Figure 11 As shown, because it is a pulse-modulated waveform, compared with a DC high-level signal, the leakage time of the first node Q is significantly shortened, and the voltage of the second node QB will not be pulled down.

[0103] When the display panel has high requirements for low grayscale display, and PWM dimming is used to improve the low grayscale display effect, that is, a larger pixel drive current is used during the light-emitting phase. Theoretically, the overall brightness of the display panel will be higher. At this time, dimming is combined with the light-emitting control signal, that is, the display brightness of the display panel is adjusted by controlling the length of the light-emitting time. During the light-emitting phase, the light-emitting control signal is a signal that alternates between multiple switching. When the light-emitting control signal output is low, the high-level signal increases the leakage time to the first node Q through the twelfth transistor T12, pulls the second node QB low, and the signal at the signal output terminal is boosted. The signal simulation diagram of the shift register provided in this embodiment is as follows. Figure 12 As shown, because it is a pulse-modulated waveform, compared with a DC high-level signal, the leakage time of the first node Q is significantly shortened, and the voltage of the second node QB will not be pulled down.

[0104] Thirdly, embodiments of this disclosure provide a display substrate, which includes a gate driving circuit as provided in any of the above embodiments. The gate driving circuit can be disposed in the non-display area of ​​the display substrate. The display substrate also includes a pixel driving circuit, which can be disposed in the display area of ​​the display substrate, and the specific circuit structure of the pixel driving circuit can be as described above. Figure 1 As shown. The light emission control signal in the pixel driving circuit structure can be provided by the gate driving circuit provided in any of the above embodiments. The implementation principle and beneficial effects of the display substrate provided in this disclosure embodiment are the same as the implementation principle and beneficial effects of the shift register and gate driving circuit provided in any of the above embodiments, and will not be repeated here.

[0105] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized by, The shift register comprises an input unit, a voltage adjusting unit, a cascade unit, an output unit and a reset unit; The input unit is configured to charge the first node with the first level signal in response to the first clock signal and the start voltage signal; the first node is a connection point between the input unit, the voltage adjusting unit, the cascade unit, the output unit and the reset unit; The voltage adjusting unit is configured to adjust the voltages of the first node and the second node with the first level signal and the second level signal in response to the first clock signal, the second clock signal and the start voltage signal; the second node is a connection point between the voltage adjusting unit, the cascade unit and the output unit; The cascade unit is configured to input the first level signal to the cascade signal end in response to the voltage of the first node, and input the second level signal to the cascade signal end in response to the voltage of the second node; The output unit is configured to input the first level signal to the signal output end in response to the voltage of the first node, and input the second level signal to the signal output end in response to the voltage of the second node; the signal output end is connected to a light-emitting control signal end of a pixel driving circuit; The reset unit is configured to reset the voltage of the first node with the reset clock signal in response to the reset signal; the reset clock signal is a periodically-varying pulse modulation signal.

2. The shift register of claim 1, wherein, The duty cycle of the reset clock signal is 40% to 60%.

3. The shift register of claim 1, wherein, The voltage adjusting unit comprises a first node discharging unit, a second node pre-charging unit, a second node discharging unit and a third node charging and discharging unit; The first node discharging unit is configured to discharge the first node with the second level signal in response to the first clock signal and the voltage of the third node; the third node is a connection point between the first node discharging unit, the second node pre-charging unit and the third node charging and discharging unit; The second node pre-charging unit is configured to pre-charge the second node with the first clock signal in response to the first clock signal and the voltage of the third node; The second node discharging unit is configured to discharge the second node with the second level signal in response to the voltage of the first node; The third node charging and discharging unit is configured to charge the third node with the first level signal in response to the second clock signal, and discharge the third node with the second clock signal in response to the start voltage signal.

4. The shift register of claim 3, wherein, The input unit comprises a first transistor and a second transistor; The control electrode of the first transistor is connected to a first clock signal end, the first electrode is connected to a first level signal end, and the second electrode is connected to the first electrode of the second transistor; The control electrode of the second transistor is connected to a start voltage end, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

5. The shift register of claim 3, wherein, The cascade unit comprises a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected to the first node, the first electrode is connected to a first level signal end, and the second electrode is connected to the cascade signal end; The control electrode of the fifteenth transistor is connected with the second node, the first electrode is connected with the second level signal end, and the second electrode is connected with the cascade signal end.

6. The shift register of claim 3, wherein, The output unit comprises a sixteenth transistor, a seventeenth transistor, a first storage capacitor and a second storage capacitor. The control electrode of the sixteenth transistor is connected with the first node, the first electrode is connected with the first level signal end, and the second electrode is connected with the signal output end. The control electrode of the seventeenth transistor is connected with the second node, the first electrode is connected with the second level signal end, and the second electrode is connected with the first electrode of the first seventeenth transistor. The control electrode of the first seventeenth transistor is connected with the second node, the first electrode is connected with the second electrode of the seventeenth transistor, and the second electrode is connected with the signal output end. One end of the first storage capacitor is connected with the first node, and the other end is connected with the signal output end. One end of the second storage capacitor is connected with the second node, and the other end is connected with the second level signal end.

7. The shift register of claim 3, wherein, The reset unit comprises a twelfth transistor. The control electrode of the twelfth transistor is connected with the reset signal end, the first electrode is connected with the reset clock signal end, and the second electrode is connected with the first node.

8. The shift register of claim 3, wherein, The first node discharge unit comprises a tenth transistor and an eleventh transistor. The control electrode of the tenth transistor is connected with the third node, the first electrode is connected with the second electrode of the eleventh transistor, and the second electrode is connected with the first node. The control electrode of the eleventh transistor is connected with the first clock signal end, the first electrode is connected with the second level signal end, and the second electrode is connected with the first electrode of the tenth transistor.

9. The shift register of claim 3, wherein, The second node pre-charge unit comprises a seventh transistor, an eighth transistor and a third storage capacitor. The control electrode of the seventh transistor is connected with the third node, the first electrode is connected with the first clock signal end, and the second electrode is connected with the first electrode of the eighth transistor and the other end of the third storage capacitor. The control electrode of the eighth transistor is connected with the first clock signal end, the first electrode is connected with the second electrode of the seventh transistor and the other end of the third storage capacitor, and the second electrode is connected with the second node. One end of the third storage capacitor is connected with the third node, and the other end is connected with the second electrode of the seventh transistor and the first electrode of the eighth transistor.

10. The shift register of claim 3, wherein, The second node discharge unit comprises a ninth transistor. The control electrode of the ninth transistor is connected with the first node, the first electrode is connected with the second level signal end, and the second electrode is connected with the second node.

11. The shift register of claim 3, wherein, The third node charge / discharge unit comprises a third transistor, a fourth transistor and a fifth transistor. The control electrode of the third transistor is connected with the second clock signal end, the first electrode is connected with the first level signal end, and the second electrode is connected with the third node. The control electrode of the fourth transistor is connected with the starting voltage end, the first electrode is connected with the second electrode of the fifth transistor, and the second electrode is connected with the third node. The control electrode of the fifth transistor is connected with the starting voltage end, the first electrode is connected with the second clock signal end, and the second electrode is connected with the first electrode of the fourth transistor.

12. The shift register of claim 3, wherein, The shift register further comprises a first leakage prevention unit, a second leakage prevention unit and a third leakage prevention unit. The first anti-creeping unit comprises a thirteenth transistor, a control electrode of the thirteenth transistor is connected with a first voltage level signal terminal, a first electrode is connected with a first node, and a second electrode is connected with the cascade unit and the output unit; The second anti-creeping unit comprises an eighteenth transistor, a control electrode of the eighteenth transistor is connected with a signal output terminal, a first electrode is connected with the first voltage level signal terminal, and a second electrode is connected with the signal output unit; The third anti-creeping unit comprises a sixth transistor, a control electrode of the sixth transistor is connected with the third node, a first electrode is connected with the first voltage level signal terminal, and a second electrode is connected with the third node charge-discharge unit.

13. A gate drive circuit, characterized by The gate drive circuit comprises the shift register according to any one of claims 1 to 12. The start voltage terminal of the current stage shift register is connected with the cascade signal terminal of the previous stage shift register. The cascade signal terminal of the current stage shift register is connected with the start voltage terminal of the next stage shift register.

14. The gate drive circuit according to claim 13, characterized by The signal of the reset clock signal terminal is provided by a reset clock signal line.

15. The gate drive circuit of claim 13, wherein, The signal of the reset clock signal terminal is provided by a first clock signal line.

16. A display substrate, comprising: The display substrate comprises the gate drive circuit according to any one of claims 13 to 15.

Images