Semiconductor structure and manufacturing method thereof

Abstract

An embodiment of the present disclosure discloses a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a blank region adjacent to the mark region; forming a target layer and a first core layer located on the target layer on the substrate, the first core layer comprising a first array core layer located on the array region, a first mark core layer located above the mark region, and a first cap layer located above the blank region, wherein the first cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension; forming a first dielectric layer, the first dielectric layer covering the sidewalls of the first core layer; forming a first filling layer covering the surface of the first dielectric layer and filling the gap between adjacent first core layers; etching the first dielectric layer and the target layer along the sidewalls of the first array core layer and the sidewalls of the first mark core layer to transfer the patterns of the first core layer and the first filling layer to the target layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As semiconductor structures continue to shrink in size, processes such as reverse self-aligned double patterning (R-SADP) and reverse self-aligned quadruple patterning (R-SAQP) have been introduced into semiconductor manufacturing processes to increase their integration density. Taking the R-SADP process as an example, it typically involves forming multiple core layers on a target material layer to be etched, followed by forming a dielectric layer covering the sidewalls and top surface of the core layer and a spin-on hard mask layer covering the dielectric layer. The target material layer beneath is then etched using the spin-on hard mask layer and the core layer as masks.

[0003] However, the distribution of the core layer is often uneven. In areas where the core layer is sparsely distributed, depressions are usually formed on the upper surface of the spin-coated hard mask layer. When the target material layer is subsequently etched using the spin-coated hard mask layer and the core layer as masks, over-etching is prone to occur in the depressed areas on the upper surface of the spin-coated hard mask layer, resulting in errors in pattern transfer and damage to the underlying layer. In severe cases, the chip reliability and yield will be reduced. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a blank region adjacent to the mark region;

[0006] forming a target layer and a first core layer on the target layer on the substrate, wherein the first core layer includes a first array core layer on the array area, a first mark core layer above the mark area, and a first cap layer above the blank area, wherein the first cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension;

[0007] forming a first dielectric layer, wherein the first dielectric layer covers a sidewall of the first core layer;

[0008] forming a first filling layer to cover the surface of the first dielectric layer and fill the gap between adjacent first core layers;

[0009] The first dielectric layer and the target layer are etched along sidewalls of the first array core layer and sidewalls of the first marking core layer to transfer patterns of the first core layer and the first filling layer to the target layer.

[0010] In some embodiments, forming a first core layer on the target layer on the substrate includes:

[0011] forming a first mask layer on the target layer;

[0012] forming a first mask pattern on the first mask layer, wherein the first mask pattern includes a first spacer layer located on the array area and the mark area, and a second cap layer located on the blank area, wherein the second cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension;

[0013] The first mask layer is etched using the first mask pattern as a mask to form the first array core layer, the first mark core layer and the first cap layer on the array area, the mark area and the blank area respectively.

[0014] In some embodiments, forming a first mask pattern on the first mask layer includes:

[0015] forming a second mask layer on the first mask layer;

[0016] Etching the second mask layer to form a second core layer, wherein the second core layer includes a second array core layer located on the array area, a second mark core layer located on the mark area, and a second initial cap layer located on the blank area;

[0017] forming a second dielectric layer, wherein the second dielectric layer covers the sidewalls and the upper surface of the second core layer and the upper surface of the first mask layer;

[0018] Etching back the second dielectric layer to form the first spacer layer, wherein the first spacer layer covers the sidewall of the second core layer;

[0019] forming a first barrier layer, wherein the first barrier layer covers a middle region of the second initial cover layer;

[0020] The second array core layer, the second marking core layer and the second initial capping layer are etched using the first barrier layer as a mask to remove the second array core layer and the second marking core layer and form the second capping layer.

[0021] In some embodiments, forming a first dielectric layer, where the first dielectric layer covers a sidewall of the first core layer, includes:

[0022] A first dielectric layer is formed, where the first dielectric layer covers the sidewalls and the upper surface of the first core layer and the upper surface of the target layer.

[0023] In some embodiments, etching the first dielectric layer and the target layer along the sidewalls of the first array core layer and the sidewalls of the first marking core layer to transfer the patterns of the first core layer and the first filling layer to the target layer includes:

[0024] Etching back the first filling layer until the upper surface of the first dielectric layer is exposed;

[0025] The first dielectric layer and the target layer are etched using the first filling layer and the first core layer as masks to transfer patterns of the first core layer and the first filling layer to the target layer to form an initial target pattern.

[0026] In some embodiments, the first array core layer extends along a first direction; after forming the initial target pattern, the method further includes:

[0027] forming a buried layer, wherein the buried layer fills the gaps between the initial target patterns;

[0028] forming a third core layer on the initial target pattern and the buried layer, the third core layer comprising a third array core layer located on the array region and a third cap layer located on the peripheral region; wherein the third array core layer extends along a second direction intersecting the first direction, and the third cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension;

[0029] forming a third dielectric layer, wherein the third dielectric layer covers the sidewalls of the third core layer;

[0030] forming a second filling layer, wherein the second filling layer covers the surface of the third dielectric layer and fills the gaps between adjacent third core layers;

[0031] The third dielectric layer and the initial target pattern are etched along the sidewalls of the third array core layer to transfer the patterns of the second filling layer and the third core layer to the initial target pattern to form a target pattern.

[0032] In some embodiments, a third core layer is formed on the initial target pattern and the buried layer, wherein the third core layer includes a third array core layer located on the array region and a third cap layer located on the peripheral region, including:

[0033] forming a third mask layer on the initial target pattern and the buried layer;

[0034] forming a second mask pattern on the third mask layer, wherein the second mask pattern includes a second spacer layer located on the array region and a fourth capping layer located on the peripheral region, wherein the fourth capping layer has an inclined sidewall and a top dimension smaller than a bottom dimension;

[0035] The third mask layer is etched using the second mask pattern as a mask to form the third array core layer and the third cap layer on the array region and the peripheral region respectively.

[0036] In some embodiments, a second mask pattern is formed on the third mask layer, wherein the second mask pattern includes a second spacer layer located on the array region and a fourth cap layer located on the peripheral region, including:

[0037] forming a fourth mask layer on the third mask layer;

[0038] Etching the fourth mask layer to form a fourth core layer, the fourth core layer comprising a fourth array core layer located on the array region and a fourth initial cap layer located on the peripheral region; wherein the fourth array core layer extends along the second direction;

[0039] forming a fourth dielectric layer, wherein the fourth dielectric layer covers the sidewalls and the upper surface of the fourth core layer and the upper surface of the third mask layer;

[0040] Etching back the fourth dielectric layer to form the second spacer layer, wherein the second spacer layer covers the sidewall of the fourth core layer;

[0041] forming a second barrier layer, wherein the second barrier layer covers a middle region of the fourth initial cover layer;

[0042] The fourth array core layer and the fourth initial cover layer are etched using the second barrier layer as a mask to remove the fourth array core layer and form the fourth cover layer.

[0043] In some embodiments, before forming the target layer on the substrate, the method further includes:

[0044] A conductive layer is formed on the substrate; a pattern transfer layer is formed on the conductive layer; and a hard mask layer is formed on the pattern transfer layer, wherein the hard mask layer is located below the target layer.

[0045] In some embodiments, after etching the third dielectric layer and the initial target pattern along the sidewall of the third array core layer to transfer the patterns of the second filling layer and the third core layer to the initial target pattern to form the target pattern, the method further includes:

[0046] The hard mask layer, the pattern transfer layer and the conductive layer are etched downwards using the target pattern as a mask to transfer the pattern of the target pattern to the conductive layer.

[0047] The present disclosure further provides a semiconductor structure, comprising:

[0048] a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a blank region adjacent to the mark region;

[0049] a target layer and a first core layer located on the target layer, wherein the first core layer includes a first array core layer located on the array area, a first marking core layer located above the marking area, and a first cover layer located above the blank area, wherein the first cover layer has an inclined sidewall and a top dimension smaller than a bottom dimension;

[0050] a first dielectric layer, wherein the first dielectric layer covers a sidewall of the first core layer;

[0051] A first filling layer is located on the first dielectric layer and between adjacent first core layers.

[0052] In some embodiments, the first dielectric layer covers sidewalls and an upper surface of the first core layer and an upper surface of the target layer.

[0053] In some embodiments, the first filling layer has a flat upper surface.

[0054] In some embodiments, the first core layer includes: a main body layer and a cover layer covering an upper surface of the main body layer.

[0055] In some embodiments, the semiconductor structure further includes: a conductive layer located on the substrate; a pattern transfer layer located on the conductive layer; and a hard mask layer located on the pattern transfer layer, wherein the hard mask layer is located below the target layer.

[0056] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method comprises: providing a substrate, wherein the substrate comprises an array region and a peripheral region, wherein the peripheral region comprises a marking region and a blank region adjacent to the marking region; forming a target layer and a first core layer located on the target layer on the substrate, wherein the first core layer comprises a first array core layer located on the array region, a first marking core layer located above the marking region, and a first cap layer located above the blank region, wherein the first cap layer has an inclined sidewall and a top dimension is smaller than a bottom dimension; forming a first dielectric layer, wherein the first dielectric layer covers the sidewalls of the first core layer; forming a first filling layer covering the surface of the first dielectric layer and filling the gap between adjacent first core layers; etching the first dielectric layer and the target layer along the sidewalls of the first array core layer and the sidewalls of the first marking core layer to transfer the patterns of the first core layer and the first filling layer to the target layer. The first core layer provided by the embodiment of the present disclosure includes a first cover layer located above the blank area. The first cover layer plays a role in protecting the blank area, and due to the supporting effect of the first cover layer, the upper surface of the first filling layer located in the blank area will not be recessed. In this way, when etching the target layer located below the first core layer, over-etching in the blank area can be avoided to damage the target layer or other layers located below the target layer. At the same time, the first cover layer has an inclined side wall and the top size is smaller than the bottom size. In this way, etching the target layer downward along the side wall of the first cover layer is avoided, thereby avoiding errors in graphic transfer.

[0057] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the accompanying drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0060] Figures 2 to 29 A process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0063] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0064] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0065] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] As semiconductor structures continue to shrink in size, processes such as reverse self-aligned double patterning (R-SADP) and reverse self-aligned quadruple patterning (R-SAQP) have been introduced into semiconductor manufacturing processes to increase their integration density. Taking the R-SADP process as an example, it typically involves forming multiple core layers on a target material layer to be etched, followed by forming a dielectric layer covering the sidewalls and top surface of the core layer and a spin-on hard mask layer covering the dielectric layer. The target material layer beneath is then etched using the spin-on hard mask layer and the core layer as masks.

[0068] However, the distribution of the core layer is often uneven. In areas where the core layer is sparsely distributed, depressions are usually formed on the upper surface of the spin-coated hard mask layer. When the target material layer is subsequently etched using the spin-coated hard mask layer and the core layer as masks, over-etching is prone to occur in the depressed areas on the upper surface of the spin-coated hard mask layer, resulting in errors in pattern transfer and damage to the underlying layer. In severe cases, the chip reliability and yield will be reduced.

[0069] Based on this, the following technical solutions are proposed in the embodiments of the present disclosure:

[0070] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 1 As shown in the figure, the method includes the following steps:

[0071] Step 101: providing a substrate, the substrate including an array region and a peripheral region, the peripheral region including a mark region and a blank region adjacent to the mark region;

[0072] Step 102: forming a target layer and a first core layer on the target layer on the substrate, wherein the first core layer includes a first array core layer on the array area, a first mark core layer above the mark area, and a first cap layer above the blank area, wherein the first cap layer has inclined sidewalls and a top dimension smaller than a bottom dimension;

[0073] Step 103: forming a first dielectric layer, where the first dielectric layer covers the sidewalls of the first core layer;

[0074] Step 104: forming a first filling layer to cover the surface of the first dielectric layer and fill the gaps between adjacent first core layers;

[0075] Step 105 : Etching the first dielectric layer and the target layer along the sidewalls of the first array core layer and the sidewalls of the first marking core layer to transfer the patterns of the first core layer and the first filling layer to the target layer.

[0076] The following is a detailed description of the specific embodiments of the present disclosure in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagrams will not be magnified according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present disclosure.

[0077] The manufacturing method provided in the embodiments of the present disclosure can be used to manufacture dynamic random access memory (DRAM), but is not limited thereto and can also be used to manufacture any semiconductor structure.

[0078] Figures 2 to 29 A process flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 2 is a top view schematic diagram of a semiconductor structure. Figures 3 to 29 For each process step along Figure 2 The following is a schematic diagram of the cross-sectional structure taken along the lines A-A' and B-B'. Figures 2 to 29 The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail.

[0079] First, execute step 101, such as Figure 3As shown, a substrate 20 is provided. The substrate 20 includes an array region 201 and a peripheral region 202. The peripheral region 202 includes a mark region 202a and a blank region 202b adjacent to the mark region 202a.

[0080] Substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 20 is a silicon substrate, which may be doped or undoped. In actual operation, the semiconductor structure is formed on a wafer, and the mark area 202a may be placed on the dicing street of the wafer. Alignment marks may subsequently be formed on the mark area 202a.

[0081] Then, execute step 102, as Figures 4 to 11 As shown, a target layer 31 and a first core layer 37 located on the target layer 31 are formed on the substrate 20, and the first core layer 37 includes a first array core layer 371 located on the array area 201, a first marking core layer 372 located above the marking area 202a, and a first cover layer 373 located above the blank area 202b, wherein the first cover layer 373 has an inclined sidewall and the top size is smaller than the bottom size. Specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°.

[0082] The target layer 31 can be used as a mask layer, and the pattern of the upper layer can be subsequently transferred to the target layer 31, and then the pattern of the target layer 31 is transferred to the lower layer. The material of the target layer 31 includes but is not limited to oxides, such as silicon oxide.

[0083] Specifically, forming the first core layer 37 on the target layer 31 on the substrate 20 includes:

[0084] A first mask layer 32 (eg, Figure 4 );

[0085] A first mask pattern M1 is formed on the first mask layer 32. The first mask pattern M1 includes a first spacer layer 35' located on the array area 201 and the mark area 202a, and a second cap layer 343' located on the blank area 202b. The second cap layer 343' has an inclined sidewall and a top dimension smaller than a bottom dimension (e.g., Figures 5 to 10 ), specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°;

[0086] The first mask layer 32 is etched using the first mask pattern M1 as a mask to form a first array core layer 371, a first mark core layer 372 and a first cap layer 373 (such as Figure 11 ).

[0087] like Figure 4 As shown, in one embodiment, the first mask layer 32 includes an initial main layer 321 and an initial cover layer 322 located on the initial main layer 321; Figure 11 As shown, in the step of etching the first mask layer 32 to form the first core layer 37, the initial body layer 321 is etched to form a body layer 321′, and the initial cap layer 322 is etched to form a cap layer 322′. The cap layer 322′ covers the upper surface of the body layer 321′. The material of the initial body layer 321 can be a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer. The material of the initial cap layer 322 can be silicon oxynitride.

[0088] In some embodiments, the first sidewall layer 35′ and the first array core layer 371 located on the array area 201 extend along a first direction, and the extension direction of the first sidewall layer 35′ and the first marking core layer 372 located on the marking area 202a and the extension direction of the first array core layer 371 can be the same or different.

[0089] See again Figures 5 to 10 , forming a first mask pattern M1 on the first mask layer 32, including:

[0090] A second mask layer 33 (eg, Figure 5 );

[0091] The second mask layer 33 is etched to form a second core layer 34, which includes a second array core layer 341 located on the array area 201, a second mark core layer 342 located on the mark area 202a, and a second initial cap layer 343 located on the blank area 202b (e.g., Figure 6 ); The second array core layer 341 extends along the first direction;

[0092] A second dielectric layer 35 is formed, and the second dielectric layer 35 covers the sidewalls and the upper surface of the second core layer 34 and the upper surface of the first mask layer 32 (eg, Figure 7 );

[0093] The second dielectric layer 35 is etched back to form a first spacer layer 35'. The first spacer layer 35' covers the sidewall of the second core layer 34 (eg, Figure 8 );

[0094] A first barrier layer 36 is formed, and the first barrier layer 36 covers the middle area of ​​the second initial cover layer 343 (eg Figure 9 );

[0095] The second array core layer 341, the second marking core layer 342 and the second initial capping layer 343 are etched using the first barrier layer 36 as a mask to remove the second array core layer 341 and the second marking core layer 342 and form a second capping layer 343′ (eg Figure 10 ).

[0096] like Figure 5 As shown, in one embodiment, the second mask layer 33 includes an initial main layer 331 and an initial cover layer 332 located on the initial main layer 331; Figure 6 As shown, in the step of etching the second mask layer 33 to form the second core layer 34, the initial body layer 331 is etched to form a body layer 331′, and the initial cap layer 332 is etched to form a cap layer 332′. The cap layer 332′ covers the upper surface of the body layer 331′. The material of the initial body layer 331 can be a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer. The material of the initial cap layer 332 can be silicon oxynitride. The material of the second dielectric layer 35 includes, but is not limited to, an oxide, such as silicon oxide.

[0097] In one embodiment, the second array core layer 341 , the second marking core layer 342 and the second initial capping layer 343 may be etched using a dry etching process, which may be chemical gas etching. Specifically, the disclosed embodiment uses a first barrier layer 36 to cover the middle region of the second initial capping layer 343, exposing the edge region of the second initial capping layer 343. Simultaneously, by increasing the carbon content of the etching gas introduced into the reaction chamber, the etching selectivity between the second core layer 34 and the first spacer layer 35' is increased, thereby retaining the first spacer layer 35'. Due to the barrier effect of the first spacer layer 35', the formed second capping layer 343' has inclined sidewalls, and the width of the top is smaller than the width of the bottom. Thus, during the step of etching the first mask layer 32 using the first mask pattern M1 as a mask, the pattern of the second capping layer 343' is transferred to the first mask layer 32, forming a first capping layer 373 also having inclined sidewalls. Specifically, the angle between the inclined sidewalls and the direction parallel to the surface of the substrate 20 ranges from 20° to 70°. The material of the first barrier layer 36 can be photoresist.

[0098] See again Figure 4In one embodiment, before forming the target layer 31 on the substrate 20, the process further includes: forming a conductive layer 27 on the substrate 20; forming a pattern transfer layer 28 on the conductive layer 27; and forming a hard mask layer 29 on the pattern transfer layer 28, with the hard mask layer 29 being located below the target layer 31. The pattern formed on the target layer 31 can subsequently be transferred to the conductive layer 27. In the disclosed embodiment, a multilayer structure including the pattern transfer layer 28, the hard mask layer 29, and the target layer 31 is formed on the conductive layer 27. When the pattern of the upper layer is subsequently transferred to the target layer 31 and then transferred from the target layer 31 to the conductive layer 27, the accuracy of the pattern transfer can be improved. The material of the conductive layer 27 includes, but is not limited to, titanium nitride; the material of the pattern transfer layer 28 can be an advanced patterning film (APF) material; and the material of the hard mask layer 29 includes, but is not limited to, nitride oxide, such as silicon oxynitride.

[0099] Continue to see Figure 4 Before forming the conductive layer 27 on the substrate 20, the method further includes:

[0100] An isolation structure 21 and a plurality of active areas AA separated by the isolation structure 21 are formed in the substrate 20 , wherein the isolation structure 21 and the active areas AA are both located in the array area 201 ;

[0101] A plurality of word line structures 22 extending along a third direction and a word line capping layer 23 covering the word line structures 22 are formed in the substrate 20 located in the array region 201 ;

[0102] forming a plurality of bit line structures 24 extending along a fourth direction on the array region 201;

[0103] A plurality of isolation fences 25 extending along a third direction are formed on the array region 201 , and the isolation fences 25 are arranged to intersect with the bit line structures 24 ;

[0104] An insulating layer 26 is formed on the peripheral region 202 .

[0105] In one embodiment, the third direction and the fourth direction are perpendicular to each other, and the first direction intersects the third direction and the fourth direction.

[0106] It should be noted that the embodiments of the present disclosure provide Figures 3 to 29This is a cross-sectional view taken along the extension direction of isolation fence 25. In actual operation, isolation fence 25 and bitline structure 24 intersect to define multiple gaps. The gaps expose active area AA, and portions of conductive layer 27 are located within these gaps. In some embodiments, before forming conductive layer 27, contact plugs (not shown) are formed within the gaps. The bottom of the contact plug (not shown) is electrically connected to active area AA, and the top is electrically connected to conductive layer 27. In the disclosed embodiment, isolation fence 25 and insulating layer 26 can be formed in the same process step. The materials of isolation fence 25 and insulating layer 26 can be nitride, such as silicon nitride.

[0107] Next, execute step 103, as Figure 12 As shown, a first dielectric layer 38 is formed, and the first dielectric layer 38 covers the sidewalls of the first core layer 37 .

[0108] Specifically, forming the first dielectric layer 38 includes: forming the first dielectric layer 38, the first dielectric layer 38 covering the sidewalls and the upper surface of the first core layer 37 and the upper surface of the target layer 31. The material of the first dielectric layer 38 includes oxide, such as silicon oxide.

[0109] Then, execute step 104, as shown in FIG. Figure 13 As shown, a first filling layer 39 is formed to cover the surface of the first dielectric layer 38 and fill the gap between adjacent first core layers 37 .

[0110] The first filling layer 39 covers the first dielectric layer 38 and fills the gaps between the first core layers 37. The first filling layer 39 may be a spin-on hard mask layer, which may include an amorphous carbon layer or an amorphous silicon layer.

[0111] The first cover layer 373 provided in the embodiment of the present disclosure plays the role of protecting the blank area 202b and supporting the first filling layer 39. In this way, the formation of a depression on the upper surface of the first filling layer 39 located on the blank area 202b is avoided. The first filling layer 39 has a flat surface. When the target layer 31 located thereunder is subsequently etched using the first filling layer 39 and the first core layer 37 as masks, over-etching in the blank area 202b can be avoided.

[0112] Next, execute step 105, as Figures 14 and 15 As shown, the first dielectric layer 38 and the target layer 31 are etched along the sidewalls of the first array core layer 371 and the first marking core layer 372 to transfer the patterns of the first core layer 37 and the first filling layer 39 to the target layer 31 .

[0113] Specifically, etching the first dielectric layer 38 and the target layer 31 along the sidewalls of the first array core layer 371 and the sidewalls of the first marking core layer 372 to transfer the patterns of the first core layer 37 and the first filling layer 39 to the target layer 31 includes:

[0114] The first filling layer 39 is etched back until the upper surface of the first dielectric layer 38 is exposed (eg Figure 14 );

[0115] The first dielectric layer 38 and the target layer 31 are etched using the first filling layer 39 and the first core layer 37 as masks to transfer the patterns of the first core layer 37 and the first filling layer 39 to the target layer 31 to form an initial target pattern 31′ (e.g. Figure 15 ).

[0116] In the embodiment of the present disclosure, the first capping layer 373 formed on the blank area 202b has an inclined sidewall and the top size is smaller than the bottom size. Specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°. In this way, etching the target layer 31 downward along the sidewall of the first capping layer 373 is avoided, and errors in pattern transfer are avoided.

[0117] like Figure 2 As shown, in one embodiment, the initial target pattern 31 ′ located in the array region 301 extends along a first direction, and the extension direction of the initial target pattern 31 ′ located in the marking region 202 a and the extension direction of the initial target pattern 31 ′ located in the array region 201 may be the same or different.

[0118] Next, if Figures 16 to 28 As shown, after forming the initial target pattern 31', the following steps are further included:

[0119] A buried layer 41 is formed to fill the gaps between the initial target patterns 31' (eg Figure 16 );

[0120] A third core layer 47 is formed on the initial target pattern 31′ and the buried layer 41. The third core layer 47 includes a third array core layer 471 located on the array region 201 and a third cap layer 472 located on the peripheral region 202. The third array core layer 471 extends along a second direction intersecting the first direction, and the third cap layer 472 has an inclined sidewall and a top dimension smaller than a bottom dimension (e.g., Figures 17 to 24 ), specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°;

[0121] A third dielectric layer 48 is formed, and the third dielectric layer 48 covers the sidewalls of the third core layer 47 (eg Figure 25 );

[0122] A second filling layer 49 is formed, which covers the surface of the third dielectric layer 48 and fills the gaps between adjacent third core layers 47 (eg, Figure 26 );

[0123] The third dielectric layer 48 and the initial target pattern 31' are etched along the sidewall of the third array core layer 471 to transfer the pattern of the second filling layer 49 and the third core layer 47 to the initial target pattern 31', forming a target pattern 31" (eg Figures 27 and 28 ).

[0124] See again Figures 17 to 24 , forming a third core layer 47 on the initial target pattern 31 ′ and the buried layer 41, comprising:

[0125] A third mask layer 42 (eg, Figure 17 );

[0126] A second mask pattern M2 is formed on the third mask layer 42. The second mask pattern M2 includes a second spacer layer 45' located on the array region 201 and a fourth cap layer 442' located on the peripheral region 202. The fourth cap layer 442' has an inclined sidewall and a top dimension smaller than a bottom dimension (e.g., Figures 18 to 23 ), specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°;

[0127] The third mask layer 42 is etched using the second mask pattern M2 as a mask to form a third array core layer 471 and a third cap layer 472 on the array region 201 and the peripheral region 202, respectively. Figure 24 ).

[0128] Continue to see 18 to Figure 23 , forming a second mask pattern M2 on the third mask layer 42, including:

[0129] A fourth mask layer 43 (eg, Figure 18 );

[0130] The fourth mask layer 43 is etched to form a fourth core layer 44, which includes a fourth array core layer 441 located on the array region 201 and a fourth initial cap layer 442 located on the peripheral region 202; wherein the fourth array core layer 441 extends along the second direction (eg Figure 19 );

[0131] A fourth dielectric layer 45 is formed, and the fourth dielectric layer 45 covers the sidewalls and the upper surface of the fourth core layer 44 and the upper surface of the third mask layer 42 (eg, Figure 20 );

[0132] The fourth dielectric layer 45 is etched back to form a second spacer layer 45', which covers the sidewall of the fourth core layer 44 (eg, Figure 21 );

[0133] A second barrier layer 46 is formed, and the second barrier layer 46 covers the middle region (eg, Figure 22 );

[0134] The fourth array core layer 441 and the fourth initial cover layer 442 are etched using the second barrier layer 46 as a mask to remove the fourth array core layer 441 and form a fourth cover layer 442′ (eg, Figure 23 ).

[0135] like Figure 2 As shown, the third array core layer 471 is located above the initial target pattern 31′ and the buried layer 41. The initial target pattern 31′ located on the array region 201 extends along a first direction, and the third array core layer 471 extends along a second direction. The second direction may be oblique to the first direction and intersect with the third and fourth directions. The buried layer 41 may be a spin-on hard mask layer, which may include an amorphous carbon layer or an amorphous silicon layer. The third mask layer 42, the fourth mask layer 43, the third core layer 47, and the fourth core layer 44 may each have a dual-layer structure. The materials of the third and fourth mask layers 42 and 43 may be the same as those of the first mask layer 32, and the materials of the third and fourth core layers 47 and 44 may be the same as those of the first core layer 37.

[0136] It is understandable that, although not shown in the figures, the second spacer layer 45 ′ also covers the sidewalls of the fourth initial capping layer 442 , and the fourth array core layer 441 and the fourth initial capping layer 442 can be etched using a chemical gas etching process. Specifically, the disclosed embodiment uses a second barrier layer 46 to cover the middle region of the fourth initial capping layer 442, exposing the edge regions of the fourth initial capping layer 442. Simultaneously, by increasing the carbon content of the etching gas introduced into the reaction chamber, the etching selectivity between the fourth core layer 44 and the second sidewall layer 45′ is increased, thereby preserving the second sidewall layer 45′. Due to the barrier effect of the second sidewall layer 45′, the formed fourth capping layer 442′ has inclined sidewalls, with the top width being smaller than the bottom width. Thus, during the step of etching the third mask layer 42 using the second mask pattern M2 as a mask, the pattern of the fourth capping layer 442′ is transferred onto the third mask layer 42, forming a third capping layer 472 also having inclined sidewalls. Specifically, the angle between the inclined sidewalls and a direction parallel to the surface of the substrate 20 ranges from 20° to 70°. The material of the fourth dielectric layer 45 includes an oxide, such as silicon oxide. The material of the second barrier layer 46 can be the same as that of the first barrier layer 36.

[0137] like Figure 25 As shown, in one embodiment, the third dielectric layer 48 covers the sidewalls and upper surface of the third core layer 47 and the upper surface of the buried layer 41 and the initial target pattern 31'. The material of the third dielectric layer 48 includes but is not limited to oxide, such as silicon oxide.

[0138] See again Figures 26 to 28 , etching the third dielectric layer 48 and the initial target pattern 31′ along the sidewalls of the third array core layer 47 to transfer the pattern of the second filling layer 49 and the third core layer 47 to the initial target pattern 31′ to form a target pattern 31″, including: etching back the second filling layer 49 to expose the upper surface of the third dielectric layer 48; etching the third dielectric layer 48 and the initial target pattern 31′ using the second filling layer 49 and the third core layer 47 as masks to transfer the pattern of the third core layer 47 and the second filling layer 49 to the initial target pattern 31′ to form a target pattern 31″. The second filling layer 49 can be a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer.

[0139] The third core layer 47 provided in the embodiment of the present disclosure includes a third cover layer 472 located above the peripheral area 202. The third cover layer 472 plays a role in protecting the peripheral area 202. Due to the supporting role of the third cover layer 472, the upper surface of the second filling layer 49 located in the peripheral area 202 will not be recessed. In this way, when etching the initial target pattern 31′ located below the third core layer 47, over-etching in the peripheral area 202 can be avoided to damage the initial target pattern 31′ or other layers located below the initial target pattern 31′; at the same time, the third cover layer 472 has an inclined side wall and the top size is smaller than the bottom size. Specifically, the angle between the inclined side wall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°. In this way, the initial target pattern 31′ is avoided from being etched downward along the side wall of the third cover layer 472, thereby avoiding errors in graphic transfer.

[0140] Next, if Figure 29 As shown, after forming the target pattern 31″, the process further includes: etching downward the hard mask layer 29, the pattern transfer layer 28 and the conductive layer 27 using the target pattern 31″ as a mask to transfer the pattern of the target pattern 31″ to the conductive layer 27. In some embodiments, before performing this step, the process further includes removing the buried layer 41 and other layers located above the target pattern 31″ and the buried layer 41, such as the third core layer 47, the second filling layer 49, etc.

[0141] like Figure 29 As shown, the target pattern 31″ is transferred to the conductive layer 27 to form a conductive pattern 27′. The conductive pattern 27′ located on the mark area 202a constitutes an alignment mark, and the conductive pattern 27′ located on the array area 201 constitutes a contact pad. Subsequently, a capacitor structure electrically connected to the contact pad can be formed on the substrate 20.

[0142] It should be noted that those skilled in the art can make possible changes to the sequence of the above steps without departing from the scope of protection of the present disclosure.

[0143] The present disclosure also provides a semiconductor structure, such as Figure 13 As shown, the semiconductor structure includes: a substrate 20, the substrate 20 includes an array area 201 and a peripheral area 202, the peripheral area 202 includes a mark area 202a and a blank area 202b adjacent to the mark area 202a; a target layer 31 and a first core layer 37 located on the target layer 31, the first core layer 37 includes a first array core layer 371 located on the array area 201, a first mark core layer 372 located above the mark area 202a, and a first cap layer 373 located above the blank area 202b, wherein the first cap layer 373 has an inclined sidewall and a top dimension smaller than a bottom dimension. Specifically, the inclined sidewall forms an angle in the range of 20° to 70° with a direction parallel to the surface of the substrate 20; a first dielectric layer 38, the first dielectric layer 38 covers the sidewalls of the first core layer 37; and a first filling layer 39, the first filling layer 39 is located on the first dielectric layer 38 and between adjacent first core layers 37.

[0144] Substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 20 is a silicon substrate, which may be doped or undoped. In actual operation, the semiconductor structure is formed on a wafer, and the mark area 202a may be placed on the dicing street of the wafer. Alignment marks may subsequently be formed on the mark area 202a.

[0145] The target layer 31 can be used as a mask layer, and the pattern of the upper layer can be subsequently transferred to the target layer 31, and then the pattern of the target layer 31 is transferred to the lower layer. The material of the target layer 31 includes but is not limited to oxides, such as silicon oxide.

[0146] In one embodiment, the first core layer 37 includes a main body layer (not labeled) and a cap layer (not labeled) covering the upper surface of the main body layer. In some embodiments, the first array core layer 371 extends along a first direction, and the extension direction of the first marking core layer 372 and the extension direction of the first array core layer 371 can be the same or different. The main body layer (not labeled) can be made of a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer. The cap layer (not labeled) can be made of silicon oxynitride.

[0147] In one embodiment, the first dielectric layer 38 covers the sidewalls and upper surface of the first core layer 37 and the upper surface of the target layer 31. The material of the first dielectric layer 38 includes, but is not limited to, an oxide, such as silicon oxide. The first filler layer 39 can be a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer.

[0148] In the disclosed embodiment, the first cap layer 373 serves to protect the blank area 202b. Due to the support provided by the first cap layer 373, when the first filling layer 39 is formed on the target layer 31 and the first core layer 37, the upper surface of the first filling layer 39 located in the blank area 202b does not produce a depression. The first filling layer 39 has a flat upper surface. Subsequently, the first dielectric layer 38 and the target layer 31 can be etched using the first filling layer 39 and the first core layer 37 as masks. This prevents over-etching in the blank area 202b. Furthermore, the first cap layer 373 has inclined sidewalls with a top dimension smaller than a bottom dimension. Specifically, the angle between the inclined sidewalls and the direction parallel to the surface of the substrate 20 ranges from 20° to 70°. This prevents etching of the target layer 31 downward along the sidewalls of the first cap layer 373, thereby preventing errors in pattern transfer.

[0149] In one embodiment, the semiconductor structure further includes: a conductive layer 27 located on the substrate 20; a pattern transfer layer 28 located on the conductive layer 27; and a hard mask layer 29 located on the pattern transfer layer 28, with the hard mask layer 29 being located below the target layer 31. The pattern formed on the target layer 31 can subsequently be transferred to the conductive layer 27. In the disclosed embodiment, a multilayer structure including the pattern transfer layer 28, the hard mask layer 29, and the target layer 31 is formed on the conductive layer 27. This improves the accuracy of the pattern transfer when the pattern of the upper layer is subsequently transferred to the target layer 31 and then from the target layer 31 to the conductive layer 27. The material of the conductive layer 27 includes, but is not limited to, titanium nitride; the material of the pattern transfer layer 28 can be an advanced patterning film (APF) material; and the material of the hard mask layer 29 includes, but is not limited to, oxynitride, such as silicon oxynitride.

[0150] In one embodiment, the semiconductor structure further includes: an isolation structure 21 located within the substrate 20 and defining a plurality of active areas AA within the substrate 20; both the isolation structure 21 and the active areas AA are located within the array region 201; a plurality of word line structures 22 extending along a third direction and a word line capping layer 23 covering the word line structures 22, located within the substrate 20 within the array region 201; a plurality of bit line structures 24 extending along a fourth direction and located on the array region 201; a plurality of isolation fences 25 extending along the third direction and located on the array region 201, the isolation fences 25 intersecting the bit line structures 24; and an insulating layer 26 located on the peripheral region 202. In some embodiments, the third and fourth directions are perpendicular to each other, and the first direction intersects both the third and fourth directions.

[0151] It should be noted that the embodiments of the present disclosure provide Figure 13This is a cross-sectional view taken along the extension direction of isolation fence 25. In actual operation, isolation fence 25 and bit line structure 24 intersect to define a plurality of gaps. The gaps expose active area AA, and portions of conductive layer 27 are located within these gaps. In some embodiments, the semiconductor structure further includes contact plugs (not shown) located within the gaps. The bottom of the contact plug (not shown) is electrically connected to active area AA, and the top of the contact plug is electrically connected to conductive layer 27.

[0152] In one embodiment, in actual operation, the first filling layer 39 can be etched back to expose the upper surface of the first dielectric layer 38 to form a Figure 14 Then, the first dielectric layer 38 and the target layer 31 are etched using the first filling layer 39 and the first core layer 37 as a mask to transfer the pattern of the first core layer 37 and the first filling layer 39 to the target layer 31 to form an initial target pattern 31 ', forming a Figure 15 The structure shown.

[0153] In one embodiment, in actual operation, a buried layer 41 may be formed subsequently, and the buried layer 41 fills the gaps between the initial target patterns 31 ′ to form a Figure 16 Next, a third core layer 47 is formed on the initial target pattern 31′ and the buried layer 41. The third core layer 47 includes a third array core layer 471 located on the array region 201 and a third cap layer 472 located on the peripheral region 202. The third array core layer 471 extends along a second direction intersecting the first direction, and the third cap layer 472 has an inclined sidewall and a top dimension smaller than a bottom dimension, forming a structure as shown in FIG. Figure 24 In the structure shown, specifically, the angle between the inclined sidewall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°. Figure 2 As shown, the third array core layer 471 is located above the initial target pattern 31′ and the buried layer 41. The initial target pattern 31′ located on the array area 201 extends along the first direction, and the third array core layer 471 extends along the second direction. The second direction can be oblique to the first direction, and the second direction intersects with the third direction and the fourth direction.

[0154] In actual operation, a third dielectric layer 48 may be formed subsequently, and the third dielectric layer 48 covers the sidewall of the third core layer 47 to form a Figure 25 Next, a second filling layer 49 is formed, the second filling layer 49 covers the surface of the third dielectric layer 48 and fills the gap between adjacent third core layers 47, forming a Figure 26 Then, the second filling layer 49 is etched back to expose the third dielectric layer 48, forming a Figure 27Next, the third dielectric layer 48 and the initial target pattern 31' are etched along the sidewall of the third array core layer 471 to transfer the pattern of the second filling layer 49 and the third core layer 47 to the initial target pattern 31' to form a target pattern 31", forming a Figure 28 The structure shown.

[0155] Here, the third core layer 47 includes a third cover layer 472 located above the peripheral area 202. The third cover layer 472 plays a role in protecting the peripheral area 202, and due to the supporting role of the third cover layer 472, the upper surface of the second filling layer 49 located in the peripheral area 202 will not be recessed. In this way, when etching the initial target pattern 31′ located below the third core layer 47, over-etching in the peripheral area 202 can be avoided to damage the initial target pattern 31′ or other layers located below the initial target pattern 31′; at the same time, the third cover layer 472 has an inclined side wall and the top size is smaller than the bottom size. Specifically, the angle between the inclined side wall and the direction parallel to the surface of the substrate 20 is in the range of 20° to 70°. In this way, the initial target pattern 31′ is avoided from being etched downward along the side wall of the third cover layer 472, thereby avoiding errors in graphic transfer.

[0156] In one embodiment, in actual operation, the hard mask layer 29, the pattern transfer layer 28 and the conductive layer 27 can be etched downward using the target pattern 31″ as a mask to transfer the pattern of the target pattern 31″ to the conductive layer 27 to form a conductive pattern 27′. Figure 29 The conductive pattern 27' located on the mark area 202a constitutes an alignment mark, and the conductive pattern 27' located on the array area 201 constitutes a contact pad. A capacitor structure electrically connected to the contact pad may be formed on the substrate 20 later.

[0157] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a blank region adjacent to the mark region; forming a target layer and a first core layer on the target layer on the substrate, wherein the first core layer includes a first array core layer on the array area, a first mark core layer above the mark area, and a first cap layer above the blank area, wherein the first cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension; forming a first dielectric layer, wherein the first dielectric layer covers a sidewall of the first core layer; forming a first filling layer to cover the surface of the first dielectric layer and fill the gap between adjacent first core layers; The first dielectric layer and the target layer are etched along sidewalls of the first array core layer and sidewalls of the first marking core layer to transfer patterns of the first core layer and the first filling layer to the target layer.

2. The manufacturing method according to claim 1, characterized in that forming a first core layer on the target layer on the substrate, comprising: forming a first mask layer on the target layer; forming a first mask pattern on the first mask layer, wherein the first mask pattern includes a first spacer layer located on the array area and the mark area, and a second cap layer located on the blank area, wherein the second cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension; The first mask layer is etched using the first mask pattern as a mask to form the first array core layer, the first mark core layer and the first cap layer on the array area, the mark area and the blank area respectively.

3. The manufacturing method according to claim 2, characterized in that Forming a first mask pattern on the first mask layer, comprising: forming a second mask layer on the first mask layer; Etching the second mask layer to form a second core layer, wherein the second core layer includes a second array core layer located on the array area, a second mark core layer located on the mark area, and a second initial cap layer located on the blank area; forming a second dielectric layer, wherein the second dielectric layer covers the sidewalls and the upper surface of the second core layer and the upper surface of the first mask layer; Etching back the second dielectric layer to form the first spacer layer, wherein the first spacer layer covers the sidewall of the second core layer; forming a first barrier layer, wherein the first barrier layer covers a middle region of the second initial cover layer; The second array core layer, the second marking core layer and the second initial capping layer are etched using the first barrier layer as a mask to remove the second array core layer and the second marking core layer and form the second capping layer.

4. The manufacturing method according to claim 1, characterized in that forming a first dielectric layer, wherein the first dielectric layer covers a sidewall of the first core layer, comprising: A first dielectric layer is formed, where the first dielectric layer covers the sidewalls and the upper surface of the first core layer and the upper surface of the target layer.

5. The manufacturing method according to claim 4, characterized in that Etching the first dielectric layer and the target layer along the sidewalls of the first array core layer and the sidewalls of the first mark core layer to transfer the patterns of the first core layer and the first filling layer to the target layer, comprising: Etching back the first filling layer until the upper surface of the first dielectric layer is exposed; The first dielectric layer and the target layer are etched using the first filling layer and the first core layer as masks to transfer patterns of the first core layer and the first filling layer to the target layer to form an initial target pattern.

6. The manufacturing method according to claim 5, characterized in that The first array core layer extends along a first direction; After forming the initial target pattern, it also includes: forming a buried layer, wherein the buried layer fills the gaps between the initial target patterns; forming a third core layer on the initial target pattern and the buried layer, the third core layer comprising a third array core layer located on the array region and a third cap layer located on the peripheral region; wherein the third array core layer extends along a second direction intersecting the first direction, and the third cap layer has an inclined sidewall and a top dimension smaller than a bottom dimension; forming a third dielectric layer, wherein the third dielectric layer covers the sidewalls of the third core layer; forming a second filling layer, wherein the second filling layer covers the surface of the third dielectric layer and fills the gaps between adjacent third core layers; The third dielectric layer and the initial target pattern are etched along the sidewalls of the third array core layer to transfer the patterns of the second filling layer and the third core layer to the initial target pattern to form a target pattern.

7. The manufacturing method according to claim 6, characterized in that forming a third core layer on the initial target pattern and the buried layer, wherein the third core layer includes a third array core layer located on the array region and a third cap layer located on the peripheral region, including: forming a third mask layer on the initial target pattern and the buried layer; forming a second mask pattern on the third mask layer, wherein the second mask pattern includes a second spacer layer located on the array region and a fourth capping layer located on the peripheral region, wherein the fourth capping layer has an inclined sidewall and a top dimension smaller than a bottom dimension; The third mask layer is etched using the second mask pattern as a mask to form the third array core layer and the third cap layer on the array region and the peripheral region respectively.

8. The manufacturing method according to claim 7, characterized in that A second mask pattern is formed on the third mask layer, wherein the second mask pattern includes a second spacer layer located on the array area and a fourth cap layer located on the peripheral area, including: forming a fourth mask layer on the third mask layer; Etching the fourth mask layer to form a fourth core layer, the fourth core layer comprising a fourth array core layer located on the array region and a fourth initial cap layer located on the peripheral region; wherein the fourth array core layer extends along the second direction; forming a fourth dielectric layer, wherein the fourth dielectric layer covers the sidewalls and the upper surface of the fourth core layer and the upper surface of the third mask layer; Etching back the fourth dielectric layer to form the second spacer layer, wherein the second spacer layer covers the sidewall of the fourth core layer; forming a second barrier layer, wherein the second barrier layer covers a middle region of the fourth initial cover layer; The fourth array core layer and the fourth initial cover layer are etched using the second barrier layer as a mask to remove the fourth array core layer and form the fourth cover layer.

9. The manufacturing method according to claim 6, characterized in that Before forming the target layer on the substrate, the method further includes: A conductive layer is formed on the substrate; a pattern transfer layer is formed on the conductive layer; and a hard mask layer is formed on the pattern transfer layer, wherein the hard mask layer is located below the target layer.

10. The manufacturing method according to claim 9, characterized in that: After etching the third dielectric layer and the initial target pattern along the sidewall of the third array core layer to transfer the patterns of the second filling layer and the third core layer to the initial target pattern to form a target pattern, the method further includes: The hard mask layer, the pattern transfer layer and the conductive layer are etched downwards using the target pattern as a mask to transfer the pattern of the target pattern to the conductive layer.

11. A semiconductor structure, characterized in that The semiconductor structure comprises: a substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a mark region and a blank region adjacent to the mark region; a target layer and a first core layer located on the target layer, wherein the first core layer includes a first array core layer located on the array area, a first marking core layer located above the marking area, and a first cover layer located above the blank area, wherein the first cover layer has an inclined sidewall and a top dimension smaller than a bottom dimension; a first dielectric layer, wherein the first dielectric layer covers a sidewall of the first core layer; A first filling layer is located on the first dielectric layer and between adjacent first core layers.

12. The semiconductor structure according to claim 11, wherein: The first dielectric layer covers the sidewalls and the upper surface of the first core layer and the upper surface of the target layer.

13. The semiconductor structure according to claim 11, wherein: The first filling layer has a flat upper surface.

14. The semiconductor structure according to claim 11, wherein: The first core layer includes a main body layer and a cover layer covering an upper surface of the main body layer.

15. The semiconductor structure according to claim 11, wherein: The semiconductor structure further includes: a conductive layer located on the substrate; a pattern transfer layer located on the conductive layer; and a hard mask layer located on the pattern transfer layer, wherein the hard mask layer is located below the target layer.

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