An implementation device of a configurable dead-band circuit

Abstract

The application discloses an implementation device of a configurable dead zone circuit. A dead zone control register receives and stores configuration data. A predetermined factor and a dead zone amplitude are output to a predetermined module, an enable signal is output to a dead zone counter module, and the dead zone amplitude is output to an output logic module. The predetermined module generates a frequency division signal according to the dead zone amplitude and the predetermined factor. The dead zone counter module controls the loading of a counting initial value in the dead zone counter module according to the frequency division signal, and counts when the enable signal is valid to obtain a counting signal. The output logic module compares the dead zone amplitude and the counting signal, and outputs a dead zone value according to a comparison result. The application changes the dead zone time according to the value of the configuration register, is convenient for synchronous timing inspection and verification, has small area and low power consumption, is convenient for implementation on a chip, and enhances the practicability of embedded application. When the application is used to configure the dead zone value, the processing flow is simple, easy to control, and the real-time change of the dead zone value can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to a configurable dead-time circuit implementation device, belonging to the field of computer technology. BACKGROUND

[0002] In the application of motor control and power electronic devices, two power devices (upper and lower) are usually connected in series to form a power conversion bridge arm. In order to avoid failure caused by breakdown, the conduction period of the two power devices cannot overlap. Therefore, a pair of non-overlapping pulse signals are needed to correctly open and close the two bridge arms. The dead-time circuit is a dead-time period inserted from when one transistor is turned on to when the other transistor is turned off. This delay ensures that the other transistor has been completely turned off before one transistor is turned on. The length of the specific delay time is usually determined by the switching characteristics of the power tube and the load characteristics in a specific application. However, it is currently not possible to programmably control the dead-time according to specific needs, which results in poor flexibility in applications and cannot meet the application scenarios. SUMMARY

[0003] The present application aims to overcome the above-mentioned defects, and provides a configurable dead-time circuit implementation device, which solves the technical problem of flexible control of dead-time, and the circuit device has a simple implementation structure and is an ideal structure for configurable dead-time circuit implementation.

[0004] To achieve the above-mentioned application purposes, the present application provides the following technical solutions:

[0005] A configurable dead-time circuit implementation device, comprising a preset module, a dead-time counter module, a dead-time control register and an output logic module;

[0006] The dead-time control register receives and stores the configuration data input from the outside, and the configuration data includes a preset factor, an enable signal and a dead-time amplitude; the preset factor and the dead-time amplitude are output to the preset module, the enable signal is output to the dead-time counter module, and the dead-time amplitude is output to the output logic module;

[0007] The preset module receives the preset factor and the dead-time amplitude input from the dead-time control register, generates a frequency division signal according to the dead-time amplitude and the preset factor, and outputs the frequency division signal to the dead-time counter module;

[0008] The dead-time counter module receives the enable signal input from the dead-time control register, the frequency division signal input from the preset module and the initial count value input from the outside, controls the loading of the initial count value in the dead-time counter module according to the frequency division signal, counts when the enable signal is valid, obtains a count signal, and outputs the count signal to the output logic module;

[0009] The output logic module receives the dead band value input by the dead band control register and the count signal input by the dead band counter module, compares the dead band value and the count signal, and outputs the dead band value according to the comparison result.

[0010] The preset module and the dead band counter module are controlled by the synchronous system clock signal and the system reset signal.

[0011] Further, the configuration data stored in the dead band control register is 8-bit data, wherein DB[2:0] is the preset factor, DB[6:3] is the dead band value, and DB[7] is the enable signal.

[0012] Further, the preset module also receives a global enable signal.

[0013] The preset module comprises a frequency division counter, an internal enable generation logic and a comparison logic.

[0014] The internal enable generation logic generates an internal enable signal according to the dead band value and the preset factor, and outputs the internal enable signal to the frequency division counter.

[0015] The frequency division counter receives the system clock signal, the system reset signal, the global enable signal and the internal enable signal, generates an internal count signal, and outputs the internal count signal to the comparison logic; when the global enable signal is valid, the frequency division counter starts counting, otherwise it does not count.

[0016] The comparison logic performs logical comparison on the internal count signal, and generates a frequency division signal.

[0017] Further, the frequency division counter is a 5-bit frequency division counter, and the internal enable generation logic generates 5 internal enable signals S1-S5.

[0018] The internal enable generation logic comprises an AND-NOT gate AOI_1, an AND-NOT gate AOI_2, a two-NOT gate nand1, a two-NOT gate nand2, a two-NOT gate nand3 and a four-NOT gate nand41.

[0019] DB[2:0] of the dead band control register are connected to three input terminals of the AND-NOT gate AOI_1 respectively, and the output terminal s1 of the AND-NOT gate AOI_1 outputs the internal enable signal S1.

[0020] DB[2:0]n of the dead band control register are connected to three input terminals of the AND-NOT gate AOI_2 respectively, and the output terminal s2 of the AND-NOT gate AOI_2 outputs the internal enable signal S2.

[0021] DB3n and DB4n of the dead band control register are connected to two input terminals of the two-NOT gate nand1 respectively, and one output terminal s4 of the two-NOT gate nand1 outputs the internal enable signal S4.

[0022] DB2n of the dead band control register and another output terminal of the NAND gate nand1 are connected to two input terminals of a NAND gate nand2, and an output terminal s3 of the NAND gate nand2 outputs an internal enable signal S3;

[0023] DBn[6:3] of the dead band control register are connected to four input terminals of a NAND gate nand41, an output terminal of the NAND gate nand41 and DB6 of the dead band control register are connected to two input terminals of a NAND gate nand3, and an output terminal s5 of the NAND gate nand3 outputs an internal enable signal S5.

[0024] Further, the frequency division counter comprises an inverter inv1, a NAND gate nand4, a NAND gate nand5, a NAND gate nand6, a NAND gate nand7, a NAND gate nand8, an AND gate and1, a NOR gate nor1, a NOR gate nor2, a NOR gate nor3, a NOR gate nor4, a half adder HADD1, a half adder HADD2, a half adder HADD3, an XOR gate xor1, a flip-flop dff_4, a flip-flop dff_5, a flip-flop dff_6, a flip-flop dff_7, a flip-flop dff_8;

[0025] Two input terminals of the NAND gate nand4 are connected to an output terminal of the inverter inv1 and an output terminal s5 of the NAND gate nand3 respectively;

[0026] Two input terminals of the AND gate and1 are connected to an output terminal of the NAND gate nand4 and an output terminal s3 of the NAND gate nand2 respectively, and an output terminal of the AND gate and1 is connected to an input terminal D of the flip-flop dff_4;

[0027] An input terminal g_en of the frequency division counter is connected to an input terminal of one of the NOR gate nor1, the NOR gate nor2, the NOR gate nor3 and the NOR gate nor4 respectively, and the input terminal g_en is connected to an externally input global enable signal EN;

[0028] Two input terminals of the half adder HADD1 are connected to an output terminal Q4 of the flip-flop dff_4 and an output terminal Q5 of the flip-flop dff_5, and an output terminal sum1 of the half adder HADD1 and an output terminal s1 of the AOI_1 are connected to two input terminals of the NAND gate nand5 respectively;

[0029] An output terminal of the NAND gate nand5 is connected to another input terminal of the NOR gate nor4, and an output terminal of the NOR gate nor4 is connected to an input terminal D of the flip-flop dff_5;

[0030] The two input terminals of the half adder HADD2 are connected to the output terminal Q6 of the flip-flop dff_6 and the output terminal c1 of the half adder HADD1 respectively, the output terminal sum2 of the half adder HADD2 and the output terminal s2 of the AND-OR inverter AOI_2 are connected to the two input terminals of the NAND gate nand6 respectively;

[0031] The output terminal of the NAND gate nand6 is connected to the other input terminal of the NOR gate nor3, and the output terminal of the NOR gate nor3 is connected to the input terminal D of the flip-flop dff_6;

[0032] The two input terminals of the half adder HADD3 are connected to the output terminal Q7 of the flip-flop dff_7 and the output terminal sum2 of the half adder HADD2 respectively, and the S output terminal sum3 of the half adder HADD3 and the DB4 of the dead band control register are connected to the two input terminals of the NAND gate nand7 respectively;

[0033] The output terminal of the NAND gate nand7 is connected to the other input terminal of the NOR gate nor2, and the output terminal of the NOR gate nor2 is connected to the input terminal D of the flip-flop dff_7;

[0034] The two input terminals of the XOR gate xor1 are connected to the output terminal Q8 of the flip-flop dff_8 and the output terminal c3 of the half adder HADD3 respectively, the two input terminals of the NAND gate nand8 are connected to the output terminal of the XOR gate xor1 and the output terminal s4 of the NAND gate nand1 respectively, the output terminal of the NAND gate nand8 is connected to the other input terminal of the NOR gate nor1, and the output terminal of the NOR gate nor1 is connected to the input terminal D of the flip-flop dff_8;

[0035] The system clock signal is connected to the clock terminals of the flip-flop dff_4, the flip-flop dff_5, the flip-flop dff_6, the flip-flop dff_7 and the flip-flop dff_8;

[0036] The system reset signal is connected to the reset terminals of the flip-flop dff_4, the flip-flop dff_5, the flip-flop dff_6, the flip-flop dff_7 and the flip-flop dff_8.

[0037] Further, the comparison logic includes a NOR gate nor5, a NOR gate nor6, an inverter inv2 and a three-input NAND gate nand32;

[0038] The output terminal Q4 of the flip-flop dff_4 and the output terminal Q7 of the flip-flop dff_7 are connected to the two input terminals of the NOR gate nor5 respectively;

[0039] The output terminal Q5 of the flip-flop dff_5 and the output terminal Q6 of the flip-flop dff_6 are connected to the two input terminals of the NOR gate nor6 respectively;

[0040] The output terminal Q8 of the trigger dff_8 is connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2, the output terminal of the two-NOR gate nor5, and the output terminal of the two-NOR gate nor6 are respectively connected to the three input terminals of the three-input NAND gate nand32. The output terminal out1 of the three-NAND gate nand32 outputs the divided signal.

[0041] Furthermore, the dead zone counter module is a 4-bit down counter;

[0042] The dead zone counter module includes a trigger dff_0, a trigger dff_1, a trigger dff_2, a trigger dff_3, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7, two NAND gates nand20, two NAND gates nand21, two NAND gates nand22, two NAND gates nand23, two NAND gates nand24, two NAND gates nand25, two NAND gates nand26, an exclusive OR gate xor20, an exclusive OR gate xor210, two AND gates and20, two OR gates or7, two OR gates or6, two OR gates or5, two OR gates or4, two OR gates or3, two OR gates or2, two OR gates or1 and two OR gates or0;

[0043] The system clock signal clk is connected to the clock terminals of the trigger dff_0, the trigger dff_1, the trigger dff_2, and the trigger dff_3;

[0044] The system reset signal rst is connected to the reset terminals of the trigger dff_0, trigger dff_1, trigger dff_2, and trigger dff_3;

[0045] The output terminal Q0 of the flip-flop dff_0, the output terminal Q1 of the flip-flop dff_1, the output terminal Q2 of the flip-flop dff_2 and the output terminal Q3 of the flip-flop dff_3 serve as a group of buses to output a counting signal;

[0046] The output end of the inverter inv4 and the output end of the inverter inv5 are respectively connected to the two input ends of the NAND gate nand20;

[0047] The output end of the inverter inv3 and the output end of the second NAND gate nand20 are connected to the two input ends of the exclusive OR gate xor20 respectively;

[0048] The output end of the inverter inv6 and the output end of the inverter inv7 are respectively connected to the two input ends of the NAND gate nand21;

[0049] The output end of the inverter inv5 and the output end of the second NAND gate nand21 are connected to the two input ends of the exclusive OR gate xor210 respectively;

[0050] The output terminal Q0 of the flip-flop dff_1 and the output terminal Q1 of the flip-flop dff_2 are connected to two input terminals of the NAND gate nand22 respectively;

[0051] The output terminal of the NAND gate nand21 and the output terminal of the NAND gate nand22 are connected to two input terminals of the AND gate and0 respectively;

[0052] The input terminal load[0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or7 respectively; the input terminal load[3:0] and the input terminal set are the initial value of counting and the frequency division signal respectively;

[0053] The input terminal count of the dead zone counter module and the output terminal Q0 of the flip-flop dff_0 are connected to two input terminals of the OR gate or6 respectively; the output terminal of the OR gate or6 and the output terminal of the OR gate or7 are connected to two input terminals of the NAND gate nand23 respectively; the output terminal of the NAND gate nand23 is connected to the input terminal D of the flip-flop dff_0; the input signal of the input terminal count is the enable signal;

[0054] The input terminal load[3:0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or5 respectively;

[0055] The input terminal count of the dead zone counter module and the output terminal of the AND gate and0 are connected to two input terminals of the OR gate or4 respectively; the output terminal of the OR gate or4 and the output terminal of the OR gate or5 are connected to two input terminals of the NAND gate nand24 respectively; the output terminal of the NAND gate nand24 is connected to the input terminal D of the flip-flop dff_1;

[0056] The input terminal load[3:0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or3 respectively;

[0057] The input terminal count of the dead zone counter module and the output terminal of the XOR gate xor1 are connected to two input terminals of the OR gate or2 respectively; the output terminal of the OR gate or2 and the output terminal of the OR gate or3 are connected to two input terminals of the NAND gate nand25 respectively; the output terminal of the NAND gate nand25 is connected to the input terminal D of the flip-flop dff_2;

[0058] The input terminal load[3:0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or1 respectively;

[0059] The input terminal count of the dead zone counter module and the output terminal of the XOR gate xor20 are connected to two input terminals of the OR gate or0 respectively;

[0060] The output ends of the two OR gates or0 and or1 are connected to two input ends of the NAND gate nand26, and the output end of the NAND gate nand26 is connected to the input end D of the flip-flop dff_3.

[0061] Further, the output logic module also receives an external input output enable signal DB_EN, compares the dead band amplitude and the count signal when the output enable signal DB_EN is valid, and outputs the dead band value according to the comparison result;

[0062] The output logic module comprises a comparison logic and a 16-bit comparison register.

[0063] The comparison register receives the dead band amplitude input by the dead band control register.

[0064] The comparison logic receives the count signal input by the output enable signal DB_EN and the dead band counter module, reads the dead band amplitude from the comparison register, compares the dead band amplitude and the count signal, and outputs the dead band value according to the comparison result when the output enable signal DB_EN is valid, otherwise, does not output the dead band value.

[0065] Further, if the comparison result is equal, the output enable signal is 1, otherwise, the output enable signal is 0, and the output enable signal enables or disables the generation of the dead band and outputs the dead band value.

[0066] In the application, the predetermined scaling factor, i.e., the frequency division value of the system clock, can be set as needed, the enable signal is determined according to the specific application scenario, the dead band amplitude is 4 bits, and the 4-bit dead band value can realize the change of 16 kinds of dead band states. By adjusting the dead band amplitude, the output dead band value can be adjusted, so as to obtain a kind of dead band state corresponding to the 4-bit dead band value, and one kind of dead band state corresponds to one kind of dead band time.

[0067] Further, in the dead band counter module, the loading process of the count initial value in the dead band counter module is controlled according to the frequency division signal as follows:

[0068] When the frequency division signal is valid, the count initial value is loaded to the dead band counter module, otherwise, is not loaded.

[0069] Compared with the prior art, the application has the following beneficial effects:

[0070] (1) The implementation method of the configurable dead band circuit can complete the generation of the dead band according to the configuration of the dead band control register, and calculate the dead band value through the counter according to the register configuration information, so that the circuit is simple and fast to realize.

[0071] (2) In the application, the dynamic power consumption is only generated when the dead zone enable signal is valid, and no dynamic power consumption is generated at other times, so the overall circuit power consumption is low; at the same time, the synchronous clock design is adopted, which facilitates timing inspection and verification and enhances the practicability of embedded applications;

[0072] (3) When the dead zone is generated by using the application, only the value of the dead zone register, a one-bit dead zone enable signal, and a clock and reset signal need to be configured to control the operation of the circuit, and the control flow is simple;

[0073] (4) The application can conveniently and flexibly select the dead zone value according to application needs. BRIEF DESCRIPTION OF DRAWINGS

[0074] Fig. 1 It is a structure diagram of the configurable dead zone circuit of the application;

[0075] Fig. 2 It is a dead zone control register schematic diagram of the application;

[0076] Fig. 3 It is a frequency division counter in the preset module circuit of the application;

[0077] Fig. 4 It is a count enable generation logic in the preset module circuit of the application;

[0078] Fig. 5 It is a comparison logic in the preset module circuit of the application;

[0079] Fig. 6 It is a dead zone counter module circuit diagram of the application. DETAILED DESCRIPTION

[0080] The characteristics and advantages of the application will become clearer and more explicit with the following detailed description of the application.

[0081] The special word "exemplary" here means "serving as an example, embodiment or illustration". Any embodiment described as "exemplary" here is not necessarily interpreted as superior or better than other embodiments.

[0082] The application provides an implementation device of a configurable dead zone circuit, which can set or change the register of the dead zone according to needs, generate the required dead zone value, and ensure that the two-way PWM output will not make the upper and lower arms of the power bridge conduct at the same time, that is, when one power device is not completely turned off, the other device will not be turned on. The application adopts a synchronous clock design, has a simple structure, small area and low power consumption, is convenient to implement on a chip, and has a simple processing flow when the dead zone circuit is used, is easy to control, improves the compatibility of the equipment, and enhances the practicability of embedded applications.

[0083] The technical solutions of the present application will be described in detail below. Figs. 1-6 The technical solutions of the present application will be described in detail below.

[0084] As shown in Fig. 1 , the implementation device of the configurable dead zone circuit comprises a dead zone control register, a preset module, a dead zone counter module and an output logic module.

[0085] The dead zone control register receives and stores the configuration data input from outside, such as Fig. 2 as shown, the configuration data comprises a preset factor, an enable signal and a dead zone amplitude; the preset factor and the dead zone amplitude are output to the preset module, the enable signal is output to the dead zone counter module, and the dead zone amplitude is output to the output logic module.

[0086] The preset module receives the system clock signal, the reset signal and the global enable signal, and the preset factor and the dead zone amplitude input from the dead zone control register, generates an internal enable signal according to the dead zone amplitude and the preset factor, then outputs the global enable signal, the internal enable signal, the clock signal and the reset signal to the frequency division counter, and outputs the frequency division count value to the comparison logic to generate a frequency division signal, which is output to the dead zone counter module; the global enable signal is input from outside the system and is used for enabling the counting of the frequency division counter, when the global enable signal is valid, the frequency division counter starts counting, otherwise it does not count.

[0087] The dead zone counter module receives the system clock signal, the reset signal, the external count initial value, the frequency division signal output from the preset module and the enable signal input from the dead zone control register. When the output signal of the preset module is valid, the external count initial value is loaded into the counter, otherwise it is not loaded. When the enable signal is valid, the counting is performed to obtain the output of the count value (referred to as the count signal), which is output to the output logic module.

[0088] The output logic module receives the dead zone amplitude input from the dead zone control register, the count signal output from the dead zone counter module and the output enable signal input from outside. When the output enable signal is valid, the dead zone amplitude and the count signal are compared, and the dead zone value is output according to the comparison result.

[0089] The preset module and the dead zone counter module are controlled by the synchronous system clock signal and the system reset signal.

[0090] Further, as shown in Fig. 3 , 4 , 5, the preset module comprises an internal enable generation logic, a 5-bit frequency division counter and a comparison logic.

[0091] Internal enable generation logic: the frequency divider is a 5-bit frequency divider, and the internal enable generation logic generates 5 internal enable signals S1-S5;

[0092] The internal enable generation logic includes an AND-NOT gate AOI_1, an AND-NOT gate AOI_2, a two-AND-NOT gate nand1, a two-AND-NOT gate nand2, a two-AND-NOT gate nand3, and a four-AND-NOT gate nand41.

[0093] The DB[2:0] of the dead band control register are connected to three input terminals of the AND-NOT gate AOI_1, and the output terminal s1 of the AND-NOT gate AOI_1 outputs the internal enable signal S1; the DB[2:0] of the dead band control register is the predetermined index factor;

[0094] The DB[2:0]n of the dead band control register are connected to three input terminals of the AND-NOT gate AOI_2, and the output terminal s2 of the AND-NOT gate AOI_2 outputs the internal enable signal S2; the DB[2:0]n of the dead band control register is the non of the predetermined index factor DB[2:0];

[0095] The DB3n and DB4n of the dead band control register are connected to two input terminals of the two-AND-NOT gate nand1, and one output terminal s4 of the two-AND-NOT gate nand1 outputs the internal enable signal S4; the input terminals DB3n and DB4n are the non of the DB[4:3] of the dead band control register;

[0096] The DB2n of the dead band control register and the other output terminal of the two-AND-NOT gate nand1 are connected to two input terminals of the two-AND-NOT gate nand2, and the output terminal s3 of the two-AND-NOT gate nand2 outputs the internal enable signal S3; the DB2n of the dead band control register is the non of the DB2 bit of the dead band control register;

[0097] The DBn[6:3] of the dead band control register are connected to four input terminals of the four-AND-NOT gate nand41, and the output terminal of the four-AND-NOT gate nand41 and the DB6 of the dead band control register are connected to two input terminals of the two-AND-NOT gate nand3, and the output terminal s5 of the two-AND-NOT gate nand3 outputs the internal enable signal S5; the DBn[6:3] of the dead band control register and the DB6 are the non of the DB[6:3] of the dead band control register and the DB6 bit of the dead band control register, respectively.

[0098] 5-bit frequency counter: two inputs of the NAND gate nand4 are connected to the output of the inverter invl and the output s5 of the NAND gate nand3, respectively. Two inputs of the AND gate andl are connected to the output of the NAND gate nand4 and the output s3 of the NAND gate nand2, respectively. The output of the AND gate andl is connected to the input D of the flip-flop dff_4. The input g_en is connected to one of the inputs of the NOR gate norl, the NOR gate nor2, the NOR gate nor3 and the NOR gate nor4, respectively. The input g_en is externally inputted with the signal EN. Two inputs of the half-adder HADDl are connected to the output Q4 of the flip-flop dff_4 and the output Q5 of the flip-flop dff_5, respectively. The output suml of the half-adder HADDl and the output s l of the AOI gate AOI_l are connected to two inputs of the NAND gate nand5, respectively. The output of the NAND gate nand5 is connected to the other input of the NOR gate nor4. The output of the NOR gate nor4 is connected to the output logic. Two inputs of the half-adder HADD2 are connected to the output Q6 of the flip-flop dff_6 and the output cl of the half-adder HADDl, respectively. The output sum2 of the half-adder HADD2 and the output s2 of the AOI gate AOI_2 are connected to two inputs of the NAND gate nand6, respectively. The output of the NAND gate nand6 is connected to the other input of the NOR gate nor3. The output of the NOR gate nor3 is connected to the input D of the flip-flop dff_6. Two inputs of the half-adder HADD3 are connected to the output Q7 of the flip-flop dff_7 and the output sum2 of the half-adder HADD2, respectively. The output sum3 of the half-adder HADD3 and DB4 of the dead-band control register are connected to two inputs of the NAND gate nand7, respectively. The output of the NAND gate nand7 is connected to the other input of the NOR gate nor2. The output of the NOR gate nor2 is connected to the output logic. Two inputs of the XOR gate xorl are connected to the output Q8 of the flip-flop dff_8 and the output c3 of the half-adder HADD3, respectively. Two inputs of the NAND gate nand8 are connected to the output of the XOR gate xorl and the output s4 of the NAND gate nandl, respectively. The output of the NAND gate nand8 is connected to the other input of the NOR gate norl. The output of the NOR gate norl is connected to the input D of the flip-flop dff_8. The system clock signal is connected to the clock terminals of the flip-flops dff_4, dff_5, dff_6, dff_7 and dff_8.

[0099] The comparison logic: the system clock signal clk contacts the clock terminal clk of the flip-flop dff_4, the flip-flop dff_5, the flip-flop dff_6, the flip-flop dff_7 and the flip-flop dff_8. The system reset signal rst contacts the reset terminal CLR of the flip-flop dff_4, the flip-flop dff_5, the flip-flop dff_6, the flip-flop dff_7 and the flip-flop dff_8. The output terminal Q4 of the flip-flop dff_4 and the output terminal Q7 of the flip-flop dff_7 are connected to two input terminals of the NOR gate nor5 respectively. The output terminal Q5 of the flip-flop dff_5 and the output terminal Q6 of the flip-flop dff_6 are connected to two input terminals of the NOR gate nor6 respectively. The output terminal Q8 of the flip-flop dff_8 is connected to the input terminal of the inverter inv2. The output terminal of the NOR gate nor5, the output terminal of the inverter inv2 and the output terminal of the NOR gate nor6 are connected to three input terminals of the NAND gate nand32 respectively. The output terminal of the NAND gate nand32 is connected to the output port out1.

[0100] Further, as shown in Fig. 2, the dead zone counter module comprises a 4-bit down counter. Fig. 6

[0101] The dead zone counter module comprises the flip-flop dff_0, the flip-flop dff_1, the flip-flop dff_2, the flip-flop dff_3, the inverter inv3, the inverter inv4, the inverter inv5, the inverter inv6, the inverter inv7, the NAND gate nand20, the NAND gate nand21, the NAND gate nand22, the NAND gate nand23, the NAND gate nand24, the NAND gate nand25, the NAND gate nand26, the XOR gate xor20, the XOR gate xor210, the AND gate and20, the OR gate or7, the OR gate or6, the OR gate or5, the OR gate or4, the OR gate or3, the OR gate or2, the OR gate or1 and the OR gate or0.

[0102] The system clock signal clk contacts the clock terminals of the flip-flop dff_0, the flip-flop dff_1, the flip-flop dff_2 and the flip-flop dff_3.

[0103] The system reset signal rst contacts the reset terminals of the flip-flop dff_0, the flip-flop dff_1, the flip-flop dff_2 and the flip-flop dff_3.

[0104] The output terminal Q0 of the flip-flop dff_0, the output terminal Q1 of the flip-flop dff_1, the output terminal Q2 of the flip-flop dff_2 and the output terminal Q3 of the flip-flop dff_3 are outputted as a bus to the output terminal out[3:0].

[0105] The output terminal of the inverter inv4 and the output terminal of the inverter inv5 are connected to two input terminals of the NAND gate nand20 respectively.​

[0106] The output terminal of the inverter inv3 and the output terminal of the NAND gate nand20 are connected to two input terminals of the XOR gate xor20 respectively;

[0107] The output terminal of the inverter inv6 and the output terminal of the inverter inv7 are connected to two input terminals of the NAND gate nand21 respectively;

[0108] The output terminal of the inverter inv5 and the output terminal of the NAND gate nand21 are connected to two input terminals of the XOR gate xor210 respectively;

[0109] The output terminal Q0 of the flip-flop dff_1 and the output terminal Q1 of the flip-flop dff_2 are connected to two input terminals of the NAND gate nand22 respectively;

[0110] The output terminal of the NAND gate nand21 and the output terminal of the NAND gate nand22 are connected to two input terminals of the AND gate and0 respectively;

[0111] The input terminal load[0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or7 respectively; the input terminal load[3:0] and the input terminal set are the output terminal out1 of the preset module and the initial value of the count respectively;

[0112] The input terminal count of the dead zone counter module and the output terminal Q0 of the flip-flop dff_0 are connected to two input terminals of the OR gate or6 respectively; the output terminal of the OR gate or6 and the output terminal of the OR gate or7 are connected to two input terminals of the NAND gate nand23 respectively; the output terminal of the NAND gate nand23 is connected to the input terminal D of the flip-flop dff_0; the input signal of the input terminal count is the D7 bit in the dead zone control register;

[0113] The input terminal load[3:0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or5 respectively;

[0114] The input terminal count of the dead zone counter module and the output terminal of the AND gate and0 are connected to two input terminals of the OR gate or4 respectively; the output terminal of the OR gate or4 and the output terminal of the OR gate or5 are connected to two input terminals of the NAND gate nand24 respectively; the output terminal of the NAND gate nand24 is connected to the input terminal D of the flip-flop dff_1;

[0115] The input terminal load[3:0] and the input terminal set of the dead zone counter module are connected to two input terminals of the OR gate or3 respectively;

[0116] The input end count of the dead zone counter module and the output end of the exclusive OR gate xor1 are connected to two input ends of a two OR gate or2 respectively, the output end of the two OR gate or2 and the output end of a two OR gate or3 are connected to two input ends of a two NAND gate nand25 respectively, and the output end of the two NAND gate nand25 is connected to the input end D of a flip-flop dff_2.

[0117] The input end load[3:0] of the dead zone counter module and the input end set are connected to two input ends of a two OR gate or1 respectively.

[0118] The input end count of the dead zone counter module and the output end of the exclusive OR gate xor20 are connected to two input ends of a two OR gate or0 respectively.

[0119] The output end of the two OR gate or0 and the output end of the two OR gate or1 are connected to two input ends of a two NAND gate nand26 respectively, and the output end of the two NAND gate nand26 is connected to the input end D of a flip-flop dff_3.

[0120] Further, the output logic module comprises a comparison logic and a 16-bit comparison register.

[0121] The comparison logic of the output logic module performs the following process:

[0122] In the first step, according to the dead zone amplitude in the dead zone control register, the dead zone amplitude is written into the comparison register through the clock clk.

[0123] In the second step, the dead zone amplitude is compared with the output value of the dead zone counter module constantly, if the compared values are equal, 1 is output, otherwise 0 is output.

[0124] In the third step, the comparison logic output enables the generation of the dead zone to be used or prohibited, and then the set dead zone value is output.

[0125] According to the value of the configuration register, the dead zone time is changed, the circuit device has simple structure, adopts synchronous clock design, is convenient for timing check and verification, has small area and low power consumption, is convenient for implementation on a chip, and the practicality of embedded application is enhanced; when the dead zone value is configured by using the application, the processing flow is simple, easy to control, and real-time change of the dead zone value can be realized; according to the dead zone time, the device can conveniently realize the dead zone requirement of the duty cycle period. In summary, the application is an ideal structure of the configurable dead zone circuit.

[0126] The present application is described in detail above in connection with specific embodiments and exemplary examples, but it is not understood that these descriptions and examples are intended to limit the present application. It is understood by those skilled in the art that various equivalent substitutions, modifications or improvements can be made to the technical solutions and embodiments of the present application without departing from the spirit and scope of the present application, and these all fall within the scope of the present application. The scope of protection of the present application is defined by the appended claims.

[0127] The contents not described in detail in the specification of the present application are the known technology of those skilled in the art.

Claims

1. A device for implementing a configurable dead zone circuit, characterized in that: It includes a pre-calibration module, a dead zone counter module, a dead zone control register and an output logic module; Dead zone control register: receives and stores external input configuration data, including pre-scaling factor, enable signal and dead zone amplitude; Outputting the pre-scaling factor and the dead zone amplitude to the pre-scaling module, outputting the enable signal to the dead zone counter module, and outputting the dead zone amplitude to the output logic module; Prescaler module: receives the prescaler factor and dead zone amplitude input from the dead zone control register, generates a frequency division signal according to the dead zone amplitude and the prescaler factor, and outputs the frequency division signal to the dead zone counter module; Dead zone counter module: receives the enable signal input from the dead zone control register, the frequency division signal input from the pre-scaling module, and the external input count initial value, controls the loading of the count initial value in the dead zone counter module according to the frequency division signal, counts when the enable signal is valid, obtains the count signal, and outputs the count signal to the output logic module; Output logic module: receives the dead zone amplitude input by the dead zone control register and the count signal input by the dead zone counter module, compares the dead zone amplitude and the count signal, and outputs the dead zone value according to the comparison result; The pre-scaling module and the dead-band counter module are controlled by a synchronized system clock signal and a system reset signal.

2. The device for implementing a configurable dead zone circuit according to claim 1, wherein: The configuration data stored in the dead zone control register is 8-bit data, where DB[2:0] is the pre-scaling factor, DB[6:3] is the dead zone amplitude, and DB[7] is the enable signal.

3. The device for implementing a configurable dead zone circuit according to claim 2, wherein: The pre-calibration module also receives a global enable signal; The pre-scaling module includes a frequency division counter, internal enable generation logic and comparison logic; The internal enable generation logic generates an internal enable signal according to the dead zone amplitude and the pre-scaling factor, and outputs the internal enable signal to the frequency division counter; The frequency division counter receives the system clock signal, system reset signal, global enable signal and internal enable signal, generates an internal count signal, and outputs the internal count signal to the comparison logic; when the global enable signal is valid, the frequency division counter starts counting, otherwise it does not count; The comparison logic performs a logical comparison on the internal counting signal to generate a frequency division signal.

4. The device for implementing a configurable dead zone circuit according to claim 3, wherein: The frequency division counter is a 5-bit frequency division counter, and the internal enable generation logic generates 5 internal enable signals S1 to S5; The internal enable generation logic includes NAND gate AOI_1, NAND gate AOI_2, two NAND gates nand1, two NAND gates nand2, two NAND gates nand3 and four NAND gates nand41; The DB[2:0] of the dead zone control register are connected to the three input terminals of the NOR gate AOI_1 respectively, and the output terminal s1 of the NOR gate AOI_1 outputs the internal enable signal S1; The DB[2:0]n of the dead zone control register is connected to the three input terminals of the NOR gate AOI_2 respectively, and the output terminal s2 of the NOR gate AOI_2 outputs the internal enable signal S2; DB3n and DB4n of the dead zone control register are respectively connected to the two input terminals of the second NAND gate nand1, and an output terminal s4 of the second NAND gate nand1 outputs the internal enable signal S4; DB2n of the dead zone control register and the other output terminal of the second NAND gate nand1 are connected to the two input terminals of the second NAND gate nand2, and the output terminal s3 of the second NAND gate nand2 outputs the internal enable signal S3; DBn[6:3] of the dead zone control register is connected to the four input ends of the four-NAND gate nand41, the output end of the four-NAND gate nand41 and DB6 of the dead zone control register are connected to the two input ends of the two-NAND gate nand3, and the output end s5 of the two-NAND gate nand3 outputs the internal enable signal S5.

5. The device for implementing a configurable dead zone circuit according to claim 4, wherein: The frequency division counter includes an inverter inv1, two NAND gates nand4, two NAND gates nand5, two NAND gates nand6, two NAND gates nand7, two NAND gates nand8, two AND gates and1, two NOR gates nor1, two NOR gates nor2, two NOR gates nor3, two NOR gates nor4, half adders HADD1, half adders HADD2, half adders HADD3, an exclusive OR gate xor1, a flip-flop dff_4, a flip-flop dff_5, a flip-flop dff_6, a flip-flop dff_7, and a flip-flop dff_8; The two input terminals of the second NAND gate nand4 are respectively connected to the output terminal of the inverter inv1 and the output terminal s5 of the second NAND gate nand3; The two input terminals of the second AND gate and1 are connected to the output terminals of the second NAND gate nand4 and the output terminal s3 of the second NAND gate nand2 respectively, and the output terminal of the second AND gate and1 is connected to the input terminal D of the trigger dff_4; The input terminal g_en of the frequency division counter is respectively connected to the input terminal of one of the two NOR gates nor1, nor2, nor3 and nor4, and the input terminal g_en is connected to the external input global enable signal EN; Two input terminals of the half adder HADD1 are connected to the output terminal Q4 of the flip-flop dff_4 and the output terminal Q5 of the flip-flop dff_5, and the output terminal sum1 of the half adder HADD1 and the output terminal s1 of the NOR gate AOI_1 are connected to the two input terminals of the NAND gate nand5 respectively; The output terminal of the second NAND gate nand5 is connected to the other input terminal of the second NOR gate nor4, and the output terminal of the second NOR gate nor4 is connected to the input terminal D of the trigger dff_5; The two input terminals of the half adder HADD2 are connected to the output terminal Q6 of the flip-flop dff_6 and the output terminal c1 of the half adder HADD1 respectively. The output terminal sum2 of the half adder HADD2 and the output terminal s2 of the NOR gate AOI_2 are connected to the two input terminals of the NAND gate nand6 respectively. The output terminal of the second NAND gate nand6 is connected to the other input terminal of the second NOR gate nor3, and the output terminal of the second NOR gate nor3 is connected to the input terminal D of the flip-flop dff_6; The two input terminals of the half adder HADD3 are connected to the output terminal Q7 of the flip-flop dff_7 and the output terminal sum2 of the half adder HADD2 respectively. The S output terminal sum3 of the half adder HADD3 and the DB4 of the dead zone control register are connected to the two input terminals of the NAND gate nand7 respectively. The output terminal of the second NAND gate nand7 is connected to the other input terminal of the second NOR gate nor2, and the output terminal of the second NOR gate nor2 is connected to the input terminal D of the flip-flop dff_7; The two input terminals of the XOR gate xor1 are connected to the output terminal Q8 of the flip-flop dff_8 and the output terminal c3 of the half adder HADD3 respectively; the two input terminals of the NAND gate nand8 are connected to the output terminal of the XOR gate xor1 and the output terminal s4 of the NAND gate nand1 respectively; the output terminal of the NAND gate nand8 is connected to the other input terminal of the NOR gate nor1; and the output terminal of the NOR gate nor1 is connected to the input terminal D of the flip-flop dff_8; The system clock signal is connected to the clock terminals of the flip-flop dff_4, the flip-flop dff_5, the flip-flop dff_6, the flip-flop dff_7 and the flip-flop dff_8; The system reset signal is connected to the reset terminals of dff_4, flip-flop dff_5, flip-flop dff_6, flip-flop dff_7 and flip-flop dff_8.

6. The device for implementing a configurable dead zone circuit according to claim 5, characterized in that: The comparison logic includes a two-input NOR gate nor5, a two-input NOR gate nor6, an inverter inv2 and a three-input NAND gate nand32; The output terminal Q4 of the flip-flop dff_4 and the output terminal Q7 of the flip-flop dff_7 are connected to the two input terminals of the NOR gate nor5 respectively; The output terminal Q5 of the flip-flop dff_5 and the output terminal Q6 of the flip-flop dff_6 are respectively connected to the two input terminals of the NOR gate nor6; The output terminal Q8 of the trigger dff_8 is connected to the input terminal of the inverter inv2. The output terminal of the inverter inv2, the output terminal of the two-NOR gate nor5, and the output terminal of the two-NOR gate nor6 are respectively connected to the three input terminals of the three-input NAND gate nand32. The output terminal out1 of the three-NAND gate nand32 outputs the divided signal.

7. The device for implementing a configurable dead zone circuit according to claim 1, wherein: The dead zone counter module is a 4-bit down counter; The dead zone counter module includes a trigger dff_0, a trigger dff_1, a trigger dff_2, a trigger dff_3, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7, two NAND gates nand20, two NAND gates nand21, two NAND gates nand22, two NAND gates nand23, two NAND gates nand24, two NAND gates nand25, two NAND gates nand26, an exclusive OR gate xor20, an exclusive OR gate xor210, two AND gates and20, two OR gates or7, two OR gates or6, two OR gates or5, two OR gates or4, two OR gates or3, two OR gates or2, two OR gates or1 and two OR gates or0; The system clock signal clk is connected to the clock terminals of the trigger dff_0, the trigger dff_1, the trigger dff_2, and the trigger dff_3; The system reset signal rst is connected to the reset terminals of the trigger dff_0, trigger dff_1, trigger dff_2, and trigger dff_3; The output terminal Q0 of the flip-flop dff_0, the output terminal Q1 of the flip-flop dff_1, the output terminal Q2 of the flip-flop dff_2 and the output terminal Q3 of the flip-flop dff_3 serve as a group of buses to output a counting signal; The output end of the inverter inv4 and the output end of the inverter inv5 are respectively connected to the two input ends of the NAND gate nand20; The output end of the inverter inv3 and the output end of the second NAND gate nand20 are connected to the two input ends of the exclusive OR gate xor20 respectively; The output end of the inverter inv6 and the output end of the inverter inv7 are respectively connected to the two input ends of the NAND gate nand21; The output end of the inverter inv5 and the output end of the second NAND gate nand21 are connected to the two input ends of the exclusive OR gate xor210 respectively; The output terminal Q0 of the flip-flop dff_1 and the output terminal Q1 of the flip-flop dff_2 are connected to the two input terminals of the NAND gate nand22 respectively; The output end of the second NAND gate nand21 and the output end of the second NAND gate nand22 are connected to the two input ends of the second AND gate and0 respectively; The input terminal load[0] and the input terminal set of the dead zone counter module are connected to the two input terminals of the binary OR gate or7 respectively; the input terminal load[3:0] and the input terminal set are the counting initial value and the frequency division signal respectively; The input terminal count of the dead zone counter module and the output terminal Q0 of the trigger dff_0 are respectively connected to the two input terminals of the two-OR gate or6, the output terminals of the two-OR gate or6 and the output terminals of the two-OR gate or7 are respectively connected to the two input terminals of the two-NAND gate nand23, and the output terminals of the two-NAND gate nand23 are connected to the input terminal D of the trigger dff_0; the input signal of the input terminal count is an enable signal; The input terminals load[3:0] and set of the dead zone counter module are connected to the two input terminals of the OR gate or5 respectively; The input terminal count of the dead zone counter module and the output terminal of the second AND gate and0 are respectively connected to the two input terminals of the second OR gate or4, the output terminal of the second OR gate or4 and the output terminal of the second OR gate or5 are respectively connected to the two input terminals of the second NAND gate nand24, and the output terminal of the second NAND gate nand24 is connected to the input terminal D of the trigger dff_1; The input terminals load[3:0] and set of the dead zone counter module are connected to the two input terminals of the OR gate or3 respectively; The input terminal count of the dead zone counter module and the output terminal of the XOR gate xor1 are respectively connected to the two input terminals of the XOR gate or2, the output terminal of the XOR gate or2 and the output terminal of the XOR gate or3 are respectively connected to the two input terminals of the NAND gate nand25, and the output terminal of the NAND gate nand25 is connected to the input terminal D of the trigger dff_2; The input terminals load[3:0] and set of the dead zone counter module are connected to the two input terminals of the OR gate or1 respectively; The input terminal count of the dead zone counter module and the output terminal of the XOR gate xor20 are connected to the two input terminals of the XOR gate or0 respectively; The output terminals of the two OR gates or0 and or1 are connected to the two input terminals of the two NAND gates nand26 respectively. The output terminals of the two NAND gates nand26 are connected to the input terminal D of the flip-flop dff_3.

8. The device for implementing a configurable dead zone circuit according to claim 1, wherein: The output logic module also receives an externally input output enable signal DB_EN, compares the dead zone amplitude with the count signal when the output enable signal DB_EN ​​is valid, and outputs the dead zone value according to the comparison result; The output logic module includes a comparison logic and a 16-bit comparison register; The comparison register receives the dead zone amplitude input by the dead zone control register; The comparison logic receives the count signal input by the output enable signal DB_EN ​​and the dead zone counter module, reads the dead zone amplitude from the comparison register, and compares the dead zone amplitude with the count signal. When the output enable signal DB_EN ​​is valid, the dead zone value is output according to the comparison result. Otherwise, the dead zone value is not output.

9. The device for implementing a configurable dead zone circuit according to claim 8, characterized in that: If the comparison result is equal, the output dead zone value is 1, otherwise the output dead zone value is 0.

10. The device for implementing a configurable dead zone circuit according to claim 1, wherein: In the dead zone counter module, the loading process of the counting initial value in the dead zone counter module is controlled by the frequency division signal as follows: When the frequency division signal is valid, the initial count value is loaded into the dead zone counter module, otherwise it is not loaded.

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