CMOS ultra-wideband high-gain low-noise amplifier based on noise cancellation structure

Abstract

The present invention discloses a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure, which relates to the field of radio frequency integrated circuit technology. The amplifier comprises an input impedance matching circuit for inputting radio frequency signals and achieving good impedance matching; a low-noise amplifier circuit for amplifying radio frequency signals and achieving global noise cancellation, including a common-gate amplifier circuit based on a transformer positive feedback structure, a common-source amplifier circuit based on a transformer negative feedback structure, and a differential common-source common-gate amplifier circuit based on gate-terminal shorting technology; and an output impedance matching circuit for outputting the radio frequency signal after noise processing and achieving good impedance matching. The overall circuit of the present invention can achieve higher gain and lower noise.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure. Background Art

[0002] With the rapid development of communication technologies such as satellite communications and radar communications, problems such as mutual interference between signals and insufficient spectrum resources are becoming increasingly serious. Especially in the military field, application scenarios such as satellite communications and deep space exploration have higher requirements for improving the performance of communication systems and increasing the operating frequency.

[0003] Broadband wireless communication has broad application prospects in the field of satellite communications due to its advantages such as high transmission rate and efficient frequency utilization. The broadband low-noise amplifier (LNA) serves as the first-stage active amplification circuit in broadband wireless communication systems. According to the cascade circuit noise formula, its noise level determines the overall noise of the receiving link. In addition, its related indicators require a larger operating frequency band while also meeting high gain, good gain flatness, and good matching of input and output ports.

[0004] In existing technologies, high-performance LNAs are usually used to implement RF front-end circuits, and their operating frequencies are mostly below 10 GHz. Faced with higher communication capability requirements, high-performance LNAs can no longer meet the requirements of higher frequency bands, resulting in poor anti-interference capabilities of RF front-end circuits.

[0005] Therefore, there is an urgent need to develop ultra-wideband low-noise amplifiers in the high frequency range. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present application provides a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure, comprising:

[0008] An input impedance matching circuit, comprising a radio frequency signal input terminal and a first node, for inputting a radio frequency signal;

[0009] A common-gate amplifier circuit based on a transformer positive feedback structure is electrically connected to the first node and includes a first transistor, a first transformer primary winding, and a first inter-stage matching module consisting of a first transformer secondary winding and a first transformer tertiary winding that are arranged opposite to each other;

[0010] A common source amplifier circuit based on a transformer negative feedback structure is electrically connected to the first node and includes a second transistor, a second transformer primary winding, and a second inter-stage matching module composed of a second transformer secondary winding and a second transformer tertiary winding arranged opposite to each other;

[0011] a differential cascode amplifier circuit, electrically connected to both the first inter-stage matching module and the second inter-stage matching module;

[0012] The output impedance matching circuit is electrically connected to the differential cascode amplifier circuit, includes a third transformer primary winding, a third transformer secondary winding and a radio frequency signal output terminal, and is used to output the radio frequency signal after noise processing.

[0013] Optionally, the input impedance matching circuit further includes a first capacitor and a first inductor, the first end of the first capacitor is electrically connected to the first node, the second end of the first capacitor is electrically connected to the first end of the first inductor, and the second end of the first inductor is electrically connected to the RF signal input end.

[0014] Optionally, the common-gate amplifier circuit based on the transformer positive feedback structure also includes a second inductor, the first end of the second inductor is electrically connected to the bias voltage signal end, and the second end of the second inductor is electrically connected to the gate of the first transistor; the drain of the first transistor is electrically connected to the first end of the secondary winding of the first transformer, and the second end of the secondary winding of the first transformer is electrically connected to the first fixed voltage signal end; the source of the first transistor is electrically connected to the first node; the first end of the primary winding of the first transformer is electrically connected to the first node, and the second end of the primary winding of the first transformer is electrically connected to the ground end.

[0015] Optionally, the common source amplifier circuit based on the transformer negative feedback structure also includes a second capacitor, a first resistor and a second node, the first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the second node; the first end of the first resistor is electrically connected to the second node, and the second end of the first resistor is electrically connected to the bias voltage signal end; the gate of the second transistor is electrically connected to the second node, the source of the second transistor is electrically connected to the first end of the primary winding of the second transformer, and the second end of the primary winding of the second transformer is electrically connected to the ground end; the drain of the second transistor is electrically connected to the first end of the secondary winding of the second transformer, and the second end of the secondary winding of the second transformer is electrically connected to the second fixed voltage signal end.

[0016] Optionally, the differential cascode amplifier circuit includes a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, a third resistor, a third node and a fourth node; the first end of the third capacitor is electrically connected to the first end of the third winding of the first transformer, the second end of the third winding of the first transformer is electrically connected to the ground terminal, and the second end of the third capacitor is electrically connected to the third node; the first end of the second resistor is electrically connected to the third node, and the second end of the second resistor is electrically connected to the bias voltage signal terminal; the gate of the third transistor is electrically connected to the third node, the source of the third transistor is electrically connected to the ground terminal, and the drain of the third transistor is electrically connected to the source of the fifth transistor The first terminal of the fourth capacitor is electrically connected to the first terminal of the third winding of the second transformer, the second terminal of the third winding of the second transformer is electrically connected to the ground terminal, and the second terminal of the fourth capacitor is electrically connected to the fourth node; the first end of the third resistor is electrically connected to the fourth node, and the second end of the third resistor is electrically connected to the bias voltage signal terminal; the gate of the fourth transistor is electrically connected to the fourth node, the source of the fourth transistor is electrically connected to the ground terminal, the drain of the fourth transistor is electrically connected to the source of the sixth transistor, and the gate of the sixth transistor is electrically connected to the first fixed voltage signal terminal; the gate of the fifth transistor is electrically connected to the gate of the sixth transistor.

[0017] Optionally, the output impedance matching circuit also includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor and a fourth resistor. The first end of the primary winding of the third transformer is electrically connected to the drain of the fifth transistor, and the second end of the primary winding of the third transformer is electrically connected to the drain of the sixth transistor; the center tap of the primary winding of the third transformer is electrically connected to the first end of the fifth capacitor, the second end of the fifth capacitor is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the ground; the center tap of the primary winding of the third transformer is also electrically connected to the first end of the sixth capacitor, the second end of the sixth capacitor is electrically connected to the ground, and the center tap of the primary winding of the third transformer is also electrically connected to the first fixed voltage signal end; the first end of the secondary winding of the third transformer is electrically connected to the first end of the eighth capacitor, and the second end of the eighth capacitor is electrically connected to the RF signal output end; the second end of the secondary winding of the third transformer is electrically connected to the ground; the first end of the secondary winding of the third transformer is also electrically connected to the first end of the seventh capacitor, and the second end of the secondary winding of the third transformer is also electrically connected to the second end of the seventh capacitor.

[0018] Optionally, the second capacitor and the eighth capacitor are both DC blocking capacitors.

[0019] Optionally, the transconductance of the first transistor is 30 mS to 60 mS, and the transconductance of the second transistor is 40 mS to 70 mS.

[0020] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all N-type metal-oxide-semiconductor field-effect transistors.

[0021] Beneficial effects of the present invention:

[0022] The present invention provides a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure, which comprises a low-noise amplifier circuit with a differential output noise cancellation structure formed by arranging an input impedance matching circuit, a common-gate amplifier circuit based on a transformer positive feedback structure, a common-source amplifier circuit based on a transformer negative feedback structure, a differential common-source common-gate amplifier circuit using a gate terminal short-circuiting technology, and an output impedance matching circuit. The common-gate amplifier circuit based on the transformer positive feedback structure can effectively solve the problem that the traditional common-gate amplifier circuit is difficult to achieve both good input impedance matching and good noise performance. The third winding of the first transformer and the secondary winding of the first transformer arranged relatively can achieve inter-stage matching, and the secondary winding of the first transformer is reused. Compared with the Compared with using an additional transformer for inter-stage matching, it can save more layout area and introduce less noise; the common source amplifier circuit based on the transformer negative feedback structure can reduce the influence of the common source structure gate-drain capacitance, reduce the Miller effect, increase the circuit gain, and improve the reverse isolation of the circuit. The relatively arranged third winding of the second transformer and the secondary winding of the second transformer can achieve inter-stage matching, and the secondary winding of the second transformer is reused. Compared with using an additional transformer for inter-stage matching, it can save more layout area and introduce less noise; the low-noise amplifier circuit with a differential output noise cancellation structure composed of a differential common source and common gate amplifier circuit using gate short-circuiting technology increases the output current, and the overall circuit can obtain higher gain and lower noise.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a structural diagram of a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure provided by an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a principle for eliminating noise provided by an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of an input matching simulation provided by an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of an output matching simulation provided by an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of gain simulation provided by an embodiment of the present invention;

[0029] Figure 6This is a schematic diagram of a noise figure comparison simulation provided by an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of reverse isolation simulation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0032] See Figure 1 , Figure 1 : This is a structural diagram of a CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure provided by an embodiment of the present invention. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure provided by this application includes:

[0033] An input impedance matching circuit, comprising a radio frequency signal input terminal RFin and a first node N1, for inputting a radio frequency signal;

[0034] A common-gate amplifier circuit based on a transformer positive feedback structure is electrically connected to a first node N1 and includes a first transistor M1, a first transformer primary winding T1-1, and a first inter-stage matching module composed of a first transformer secondary winding T1-2 and a first transformer tertiary winding T1-3 arranged opposite to each other;

[0035] A common-source amplifier circuit based on a transformer negative feedback structure is electrically connected to the first node N1 and includes a second transistor M2, a second transformer primary winding T2-1, and a second inter-stage matching module composed of a second transformer secondary winding T2-2 and a second transformer tertiary winding T2-3 arranged opposite to each other;

[0036] a differential cascode amplifier circuit, electrically connected to both the first inter-stage matching module and the second inter-stage matching module;

[0037] The output impedance matching circuit is electrically connected to the differential cascode amplifier circuit, and includes a third transformer primary winding T3-1, a third transformer secondary winding T3-2 and a radio frequency signal output terminal RFout, which is used to output the radio frequency signal after noise processing.

[0038] For more details, please see Figure 1As shown, the CMOS ultra-wideband high-gain low-noise amplifier based on the noise cancellation structure provided in this embodiment has an operating frequency range of 9GHz~17.5GHz and mainly includes five parts, namely an input impedance matching circuit, a common-gate amplifier circuit based on a transformer positive feedback structure, a common-source amplifier circuit based on a transformer negative feedback structure, a low-noise amplifier circuit with a differential output noise cancellation structure composed of a differential common-source common-gate amplifier circuit using a gate terminal short-circuiting technology, and an output impedance matching circuit; wherein, the common-gate amplifier circuit based on the transformer positive feedback structure can effectively solve the problem that the traditional common-gate amplifier circuit is difficult to achieve good input impedance matching and good noise performance at the same time, and the relatively arranged third winding T1-3 of the first transformer and the secondary winding T1-2 of the first transformer can achieve inter-stage matching, and the first transformer The secondary winding T1-2 of the transformer is reused, which can save layout area and introduce less noise compared with using an additional transformer for inter-stage matching; the common source amplifier circuit based on the transformer negative feedback structure can reduce the influence of the common source structure gate-drain capacitance, reduce the Miller effect, increase the circuit gain, and improve the reverse isolation of the circuit. The relatively arranged third winding T2-3 of the second transformer and the secondary winding T2-2 of the second transformer can achieve inter-stage matching. The secondary winding T2-2 of the second transformer is reused, which can save layout area and introduce less noise compared with using an additional transformer for inter-stage matching; the low-noise amplifier circuit with a differential output noise cancellation structure composed of a differential common-source and common-gate amplifier circuit using gate short-circuiting technology increases the output current, and the overall circuit can obtain higher gain and lower noise.

[0039] Specifically, see Figure 2 , Figure 2 This is a schematic diagram of the principle of noise elimination provided by an embodiment of the present invention. The radio frequency signal is transmitted from the input impedance matching circuit to the common-gate amplifier circuit based on the positive feedback structure of the transformer. During the transmission process, the radio frequency signal is mixed with the noise voltage. The noise voltages on the source side and the drain side of the first transistor M1 have opposite phases, that is, the noise voltage on the drain side of the first transistor M1 is V2, and the noise voltage on the source side of the first transistor M1 is V1, and the two have opposite phases. Next, the radio frequency signal carrying the noise voltage V1 passes through the second transistor M2 in the common-source amplifier circuit based on the negative feedback structure of the transformer, and is phase-adjusted to obtain a radio frequency signal carrying the noise voltage V3. The noise voltage V3 has the same phase as the noise voltage V1. The noise voltage V1 and the noise voltage V3 are then eliminated to achieve the purpose of noise elimination in this application.

[0040] In an optional embodiment of the present application, the input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, the first end of the first capacitor C1 is electrically connected to the first node N1, the second end of the first capacitor C1 is electrically connected to the first end of the first inductor L1, and the second end of the first inductor L1 is electrically connected to the radio frequency signal input terminal RFin.

[0041] In an optional embodiment of the present application, the common-gate amplifier circuit based on the transformer positive feedback structure also includes a second inductor L2, the first end of the second inductor L2 is electrically connected to the bias voltage signal terminal VB, and the second end of the second inductor L2 is electrically connected to the gate of the first transistor M1; the drain of the first transistor M1 is electrically connected to the first end of the first transformer secondary winding T1-2, and the second end of the first transformer secondary winding is electrically connected to the first fixed voltage signal terminal VDDA1; the source of the first transistor M1 is electrically connected to the first node N1; the first end of the first transformer primary winding T1-1 is electrically connected to the first node N1, and the second end of the first transformer primary winding T1-1 is electrically connected to the ground terminal GNDA.

[0042] It should be noted that the gate of the first transistor M1 is connected in series with the second inductor L2 , and the resonance between the second inductor L2 and the parasitic capacitance of the first transistor M1 can further improve the gain of the amplifier circuit.

[0043] Specifically, in this embodiment, the common-gate amplifier circuit adopts the transformer positive feedback technology, which can effectively solve the problem that the traditional common-gate amplifier circuit is difficult to achieve good input impedance matching and good noise performance at the same time.

[0044] In an optional embodiment of the present application, the common source amplifier circuit based on the transformer negative feedback structure also includes a second capacitor C2, a first resistor R1 and a second node N2, the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the second node N2; the first end of the first resistor R1 is electrically connected to the second node N2, and the second end of the first resistor R1 is electrically connected to the bias voltage signal terminal VB; the gate of the second transistor M2 is electrically connected to the second node N2, the source of the second transistor M2 is electrically connected to the first end of the second transformer primary winding T2-1, and the second end of the second transformer primary winding T2-1 is electrically connected to the ground terminal GNDA; the drain of the second transistor M2 is electrically connected to the first end of the second transformer secondary winding T2-2, and the second end of the second transformer secondary winding T2-2 is electrically connected to the second fixed voltage signal terminal VDDA2.

[0045] It should be noted that the gate of the second transistor M2 is electrically connected to the bias voltage terminal via the first resistor R1 . The first resistor R1 is used to provide a gate bias voltage and simultaneously block an AC signal from entering the bias circuit.

[0046] Specifically, in this embodiment, the common source amplifier circuit adopts transformer negative feedback technology to reduce the parasitic capacitance of the common source transistor gate drain. The resulting Miller effect achieves better high-frequency response, increases circuit gain, and improves reverse isolation.

[0047] In an optional embodiment of the present application, the differential cascode amplifier circuit includes a third capacitor C3, a fourth capacitor C4, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second resistor R2, a third resistor R3, a third node N3 and a fourth node N4; a first end of the third capacitor C3 is electrically connected to a first end of the third winding T1-3 of the first transformer, a second end of the third winding T1-3 of the first transformer is electrically connected to a ground terminal GNDA, and a second end of the third capacitor C3 is electrically connected to a third node N3; a first end of the second resistor R2 is electrically connected to the third node N3, and a second end of the second resistor R2 is electrically connected to a bias voltage signal terminal VB; a gate of the third transistor M3 is electrically connected to the third node N3, a source of the third transistor M3 is electrically connected to the ground terminal GNDA, and a drain of the third transistor M3 is electrically connected to the fifth transistor The source of the fifth transistor M5 is electrically connected to the first fixed voltage signal terminal VDDA1; the first end of the fourth capacitor C4 is electrically connected to the first end of the third winding T2-3 of the second transformer, the second end of the third winding T2-3 of the second transformer is electrically connected to the ground terminal GNDA, and the second end of the fourth capacitor C4 is electrically connected to the fourth node N4; the first end of the third resistor R3 is electrically connected to the fourth node N4, and the second end of the third resistor R3 is electrically connected to the bias voltage signal terminal VB; the gate of the fourth transistor M4 is electrically connected to the fourth node N4, and the source of the fourth transistor M4 is electrically connected to the ground terminal GNDA; the drain of the fourth transistor M4 is electrically connected to the source of the sixth transistor M6, and the gate of the sixth transistor M6 is electrically connected to the first fixed voltage signal terminal VDDA1; the gate of the fifth transistor M5 is electrically connected to the gate of the sixth transistor M6.

[0048] Specifically, in this embodiment, the differential cascode circuit adopts the gate terminal short-circuiting technology to increase the output terminal current, and the overall circuit can obtain higher gain and lower noise.

[0049] In an optional embodiment of the present application, the output impedance matching circuit further includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8 and a fourth resistor R4; the first end of the primary winding T3-1 of the third transformer is electrically connected to the drain of the fifth transistor M5, and the second end of the primary winding T3-1 of the third transformer is electrically connected to the drain of the sixth transistor M6; the center tap of the primary winding T3-1 of the third transformer is electrically connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is electrically connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is electrically connected to the ground terminal GNDA; the center tap of the primary winding T3-1 of the third transformer is electrically connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is electrically connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is electrically connected to the ground terminal GNDA; The head is also electrically connected to the first end of the sixth capacitor C6, the second end of the sixth capacitor C6 is electrically connected to the ground terminal GNDA, and the center tap of the third transformer primary winding T3-1 is also electrically connected to the first fixed voltage signal terminal; the first end of the third transformer secondary winding T3-2 is electrically connected to the first end of the eighth capacitor C8, and the second end of the eighth capacitor C8 is electrically connected to the radio frequency signal output terminal RFout; the second end of the third transformer secondary winding T3-2 is electrically connected to the ground terminal GNDA; the first end of the third transformer secondary winding T3-2 is also electrically connected to the first end of the seventh capacitor C7, and the second end of the third transformer secondary winding T3-2 is also electrically connected to the second end of the seventh capacitor C7.

[0050] Specifically, in the CMOS ultra-wideband high-gain low-noise amplifier based on the noise elimination structure provided in this embodiment, the radio frequency signal is input into the common-gate amplifier circuit by the input impedance matching circuit and is divided into two paths, wherein one path passes through the first transistor M1 and is transmitted to the differential common-source common-gate amplifier circuit by the first inter-stage matching module, and the other path passes through the second transistor M2 in the common-source amplifier circuit and is transmitted to the differential common-source common-gate amplifier circuit by the second inter-stage matching module. It can be understood that the first inter-stage matching module can achieve good inter-stage matching between the common-gate amplifier circuit and the common-source common-gate amplifier circuit, and the second inter-stage matching module can achieve good inter-stage matching between the common-source amplifier circuit and the common-source common-gate amplifier circuit. Inter-stage matching; further, the differential cascode amplifier circuit amplifies the two RF signals and realizes global noise elimination. First, the third capacitor C3 and the fourth capacitor C4 are respectively selected to adjust the phases of the two RF signals, and then the amplitudes of the two RF signals are respectively adjusted, so that the noise signals mixed in the two RF signals are eliminated with the same phase and amplitude as much as possible; in addition, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are electrically connected to realize gate short-circuiting, so that the current is increased, and the overall circuit can obtain higher gain and lower noise; finally, the two RF signals are converted to single-ended, and the noise-eliminated RF signals are output through a passive balun transformer, that is, the third transformer.

[0051] In an optional embodiment of the present application, the second capacitor C2 and the eighth capacitor C8 are both DC blocking capacitors.

[0052] Specifically, the second capacitor C2 and the eighth capacitor C8 in this embodiment are DC blocking capacitors; wherein, the second capacitor C2 can block the DC signal to prevent it from affecting the first transistor M1 and avoiding changing the working state of the first transistor M1; the eighth capacitor C8 can achieve output matching while blocking the RF signal output terminal RFout from outputting the DC signal, thereby preventing the DC signal from affecting the circuit.

[0053] In an optional embodiment of the present application, the first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 and the sixth transistor M6 are all N-type metal-oxide-semiconductor field-effect transistors.

[0054] It should be noted that the first transistor M1 is a common-gate transistor, the second transistor M2 is a common-source transistor, the third transistor M3 is a common-source transistor, the fourth transistor M4 is a common-source transistor, the fifth transistor M5 is a common-gate transistor, and the sixth transistor M6 is a common-gate transistor.

[0055] In an optional embodiment of the present application, the use of positive feedback technology combined with a common-gate circuit can effectively solve the problem that traditional common-gate amplifier circuits are difficult to achieve good input impedance matching and good noise performance at the same time; using a common-gate amplifier circuit based on transformer positive feedback, the expression of the circuit's input impedance is:

[0056] (1)

[0057] in, is the turns ratio of the first transformer primary winding T1-1 and the first transformer secondary winding T1-2, is the coupling coefficient between the primary winding T1-1 of the first transformer and the secondary winding of the first transformer, is the transconductance of the first transistor M1; From the above formula, it can be obtained that, with the structure in this embodiment, the input impedance has more variables than the input impedance of the traditional common-gate amplifier circuit. , thus achieving better noise performance while achieving good input matching.

[0058] Among them, the expression of the traditional common-gate amplifier noise coefficient is:

[0059] (2)

[0060] ;

[0061] in, is the internal resistance of the signal source, and are process-related parameters respectively; when the inputs match, , at this time, the noise figure is:

[0062] ;

[0063] The input matching conditions of the transformer positive feedback structure are:

[0064] (3)

[0065] Combining equations (2) and (3), we can get the expression of the noise coefficient of the common-gate amplifier circuit based on transformer positive feedback:

[0066] (4)

[0067] It can be concluded that the noise coefficient of the transformer positive feedback common-gate amplifier is smaller than that of the traditional common-gate amplifier. According to the noise coefficient of the multi-stage cascade system, this embodiment selects the common-gate amplifier based on transformer positive feedback as the first stage, which can significantly reduce the overall circuit noise.

[0068] In an optional embodiment of the present application, based on the transformer negative feedback technology combined with the common source circuit, it is possible to effectively solve the capacitance between the drain and gate of the MOS tube in the CMOS process. When the MOS tube works at a higher frequency band, A low-impedance path from the gate to the drain is provided for the RF signal, which reduces the gain of the circuit and worsens the reverse isolation. This embodiment uses the coupling between the second transformer primary winding T2-1 and the second transformer secondary winding T2-2 to form negative feedback, feeding back part of the output signal to the input end to offset the Miller capacitance. The resulting drain-to-gate feedback reduces the Miller capacitance impact.

[0069] In an optional embodiment of the present application, please continue to refer to Figure 2 As mentioned above, the simplified diagram of the working principle of the differential noise cancellation structure is as follows Figure 2 As shown, and is the noise voltage generated by the first transistor M1, is the noise voltage The noise voltage generated by the inverse amplification of the second transistor M2 is expressed as follows:

[0070]

[0071] (5)

[0072]

[0073] in, is the primary winding of the first transformer, is the secondary winding T1-2 of the first transformer, is the second transformer secondary winding T2-2, is the transconductance of the first transistor M1, is the transconductance of the second transistor M2, is the channel thermal noise current generated by the first transistor M1, and its expression is:

[0074] (6)

[0075] From the above equation, it can be obtained that the noise voltages at the output terminals of the first transistor M1 and the second transistor M2 are in phase, and noise cancellation is achieved during differential output. For full noise cancellation, the relevant parameters are reasonably selected to make the differential output noise as small as possible. In this embodiment, the first transistor M1 transconductance The value is adjusted and determined around 30m~60m Siemens. The inductance of the primary winding T1-1 of the first transformer is Adjust to around 600pH and determine the inductance of the secondary winding T1-2 of the first transformer The transconductance of the second transistor M2 is adjusted to be around 2.5nH. The value is adjusted to be around 40m~70m Siemens, and the inductance of the secondary winding T2-2 of the second transformer is Adjust it around 2.5nH.

[0076] In an optional embodiment of the present application, the differential cascode structure adopts gate terminal shorting technology, and the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are connected to obtain better gain and noise performance. The gate terminals of the common gate transistors are shorted to provide an AC ground for the differential mode signal.

[0077] For the traditional cascode circuit, the output current is:

[0078] (7)

[0079] For the cascode circuit using gate shorting technology, the output current is:

[0080] (8)

[0081] in, and are the gate parasitic capacitance and source parasitic capacitance of the fifth transistor M5, is the parasitic resistance of the gate of the fifth transistor M5; thus, when the gate shorting technology is adopted, the output current is increased. Since the transistor parameters and the overdrive voltage are unchanged, it is equivalent to an increase in the equivalent transconductance, the circuit gain is increased, and the noise performance is improved.

[0082] In an optional embodiment of the present application, further explanation is given through simulation experiments.

[0083] Simulation conditions:

[0084] In the frequency band of 9 GHz to 17.5 GHz, a SMIC 40 nm CMOS process model is adopted, the first fixed voltage signal terminal VDDA1 is 1.1 V, the second fixed voltage signal terminal VDDA2 is 0.9 V, and the simulation is performed using a Cadence simulation tool.

[0085] Simulation content:

[0086] Simulation 1: Under the above conditions, the input matching of the amplifier circuit proposed in this application is simulated. Figure 3 , Figure 3 This is a schematic diagram of the input matching simulation provided by an embodiment of the present invention. As can be seen from the figure, the present application can achieve good input matching, S11<-10dB, where S11 is the reflection coefficient of port 1 when port 2 is matched.

[0087] Simulation 2: Under the above conditions, the output matching of the circuit of the present invention is simulated. Figure 4 , Figure 4 This is a schematic diagram of the output matching simulation provided by an embodiment of the present invention. As can be seen from the figure, the present application can achieve good output matching, S22<-11.9dB, where S22 is the reflection coefficient of port 2 when port 1 is matched.

[0088] Simulation 3, under the above conditions, the gain of the circuit of the present invention is simulated, see Figure 5 , Figure 5 This is a schematic diagram of the gain simulation provided by an embodiment of the present invention. As can be seen from the figure, the present application achieves a relatively high gain, and the gain is 22.9dB~25.5dB in the simulation frequency band.

[0089] Simulation 4: Comparative simulation of the noise of the circuit of the present invention under the above conditions. Figure 6 , Figure 6 This is a schematic diagram of a noise figure comparison simulation provided by an embodiment of the present invention. As can be seen from the figure, the noise figure in the simulation frequency band is 3.2dB to 3.7dB, which can achieve good noise performance within a wider bandwidth. Through comparative simulation, it can be concluded that when a differential noise cancellation structure is used, the noise performance is greatly improved.

[0090] Simulation 5: Under the above conditions, the isolation of the circuit of the present invention is simulated. Figure 7 , Figure 7 This is a schematic diagram of the reverse isolation simulation provided by an embodiment of the present invention. As can be seen from the figure, S12<-44dB in the simulation frequency band, which has good reverse isolation, where S12 is the transmission coefficient from port 2 to port 1 when port 1 is matched.

[0091] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure, characterized in that: include: An input impedance matching circuit, comprising a radio frequency signal input terminal and a first node, for inputting a radio frequency signal; A common-gate amplifier circuit based on a transformer positive feedback structure is electrically connected to the first node and includes a first transistor, a first transformer primary winding, and a first inter-stage matching module consisting of a first transformer secondary winding and a first transformer tertiary winding that are arranged opposite to each other; a common-source amplifier circuit based on a transformer negative feedback structure, electrically connected to the first node, comprising a second transistor, a second transformer primary winding, and a second inter-stage matching module consisting of a second transformer secondary winding and a second transformer tertiary winding arranged opposite to each other; a differential cascode amplifier circuit, electrically connected to both the first inter-stage matching module and the second inter-stage matching module; The output impedance matching circuit is electrically connected to the differential cascode amplifier circuit, includes a third transformer primary winding, a third transformer secondary winding and a radio frequency signal output terminal, and is used to output the radio frequency signal after noise processing.

2. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The input impedance matching circuit also includes a first capacitor and a first inductor, wherein the first end of the first capacitor is electrically connected to the first node, the second end of the first capacitor is electrically connected to the first end of the first inductor, and the second end of the first inductor is electrically connected to the RF signal input end.

3. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The common-gate amplifier circuit based on the transformer positive feedback structure also includes a second inductor, a first end of the second inductor is electrically connected to the bias voltage signal end, and a second end of the second inductor is electrically connected to the gate of the first transistor; the drain of the first transistor is electrically connected to the first end of the secondary winding of the first transformer, and the second end of the secondary winding of the first transformer is electrically connected to the first fixed voltage signal end; the source of the first transistor is electrically connected to the first node; the first end of the primary winding of the first transformer is electrically connected to the first node, and the second end of the primary winding of the first transformer is electrically connected to the ground end.

4. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The common source amplifier circuit based on the transformer negative feedback structure also includes a second capacitor, a first resistor and a second node, the first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the second node; the first end of the first resistor is electrically connected to the second node, and the second end of the first resistor is electrically connected to the bias voltage signal end; the gate of the second transistor is electrically connected to the second node, the source of the second transistor is electrically connected to the first end of the primary winding of the second transformer, and the second end of the primary winding of the second transformer is electrically connected to the ground end; the drain of the second transistor is electrically connected to the first end of the secondary winding of the second transformer, and the second end of the secondary winding of the second transformer is electrically connected to the second fixed voltage signal end.

5. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The differential cascode amplifier circuit includes a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, a third resistor, a third node and a fourth node; a first end of the third capacitor is electrically connected to the first end of the third winding of the first transformer, a second end of the third winding of the first transformer is electrically connected to the ground terminal, and a second end of the third capacitor is electrically connected to the third node; a first end of the second resistor is electrically connected to the third node, and a second end of the second resistor is electrically connected to the bias voltage signal terminal; a gate of the third transistor is electrically connected to the third node, a source of the third transistor is electrically connected to the ground terminal, a drain of the third transistor is electrically connected to the source of the fifth transistor, and the The gate of the fifth transistor is electrically connected to the first fixed voltage signal terminal; the first end of the fourth capacitor is electrically connected to the first end of the third winding of the second transformer, the second end of the third winding of the second transformer is electrically connected to the ground terminal, and the second end of the fourth capacitor is electrically connected to the fourth node; the first end of the third resistor is electrically connected to the fourth node, and the second end of the third resistor is electrically connected to the bias voltage signal terminal; the gate of the fourth transistor is electrically connected to the fourth node, the source of the fourth transistor is electrically connected to the ground terminal, the drain of the fourth transistor is electrically connected to the source of the sixth transistor, and the gate of the sixth transistor is electrically connected to the first fixed voltage signal terminal; the gate of the fifth transistor is electrically connected to the gate of the sixth transistor.

6. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The output impedance matching circuit also includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor and a fourth resistor. The first end of the primary winding of the third transformer is electrically connected to the drain of the fifth transistor, and the second end of the primary winding of the third transformer is electrically connected to the drain of the sixth transistor; the center tap of the primary winding of the third transformer is electrically connected to the first end of the fifth capacitor, the second end of the fifth capacitor is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the ground terminal; the center tap of the primary winding of the third transformer is also electrically connected to the first end of the sixth capacitor, the second end of the sixth capacitor is electrically connected to the ground terminal, and the center tap of the primary winding of the third transformer is also electrically connected to the first end of the sixth capacitor; the first end of the secondary winding of the third transformer is electrically connected to the first end of the eighth capacitor, and the second end of the eighth capacitor is electrically connected to the RF signal output terminal; the second end of the secondary winding of the third transformer is electrically connected to the ground terminal; the first end of the secondary winding of the third transformer is also electrically connected to the first end of the seventh capacitor, and the second end of the secondary winding of the third transformer is also electrically connected to the second end of the seventh capacitor.

7. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 4 or 6, characterized in that: The second capacitor and the eighth capacitor are both DC blocking capacitors.

8. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The transconductance of the first transistor is 30mS~60mS, and the transconductance of the second transistor is 40mS~70mS.

9. The CMOS ultra-wideband high-gain low-noise amplifier based on a noise cancellation structure according to claim 5 or 6, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all N-type metal-oxide-semiconductor field-effect transistors.

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